coreboot-gerrit April 2019

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Change in ...coreboot[master]: sb/intel/{common,i82801dx}: Update debug code
by Jacob Garber (Code Review) 07 Apr '19

07 Apr '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32179 Change subject: sb/intel/{common,i82801dx}: Update debug code ...................................................................... sb/intel/{common,i82801dx}: Update debug code This finishes the work done in 3e3b858 (sb/intel/ibexpeak: Update debug code to match other chips). Found-by: Coverity Scan, CID 1229598 (DEADCODE) Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Change-Id: I65df8f3363c62b364e096368a36ba5e9e8894c13 --- M src/southbridge/intel/common/smihandler.c M src/southbridge/intel/i82801dx/smihandler.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/32179/1 diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index b2cf49a..8a16aaa 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -418,7 +418,7 @@ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ printk(BIOS_DEBUG, "TCO Timeout.\n"); - } else if (!tco_sts) { + } else { dump_tco_status(tco_sts); } } diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index 17bedab..18dc4d8 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -490,7 +490,7 @@ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ printk(BIOS_DEBUG, "TCO Timeout.\n"); - } else if (!tco_sts) { + } else { dump_tco_status(tco_sts); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/32179 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I65df8f3363c62b364e096368a36ba5e9e8894c13 Gerrit-Change-Number: 32179 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: device/pci: Rewrite PCI MMCONF with symbol reference
by Kyösti Mälkki (Code Review) 07 Apr '19

07 Apr '19

Kyösti Mälkki has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31752 ) Change subject: device/pci: Rewrite PCI MMCONF with symbol reference ...................................................................... device/pci: Rewrite PCI MMCONF with symbol reference The effect of pointer aliasing on writes is that any data on CPU registers that has been resolved from (non-const and non-volatile) memory objects has to be discarded and resolved. In other words, the compiler assumes that a pointer that does not have an absolute value at build-time, and is of type 'void *' or 'char *', may write over any memory object. Using a unique datatype for MMIO writes makes the pointer to _not_ qualify for pointer aliasing with any other objects in memory. This avoid constantly resolving the PCI MMCONF address, which is a derived value from a 'struct device *'. Change-Id: Id112aa5e729ffd8015bb806786bdee38783b7ea9 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31752 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/arch/x86/include/arch/pci_mmio_cfg_romcc.h M src/arch/x86/include/arch/pci_ops.h M src/device/Makefile.inc M src/device/pci_ops.c M src/include/device/pci_mmio_cfg.h M src/include/device/pci_type.h 6 files changed, 130 insertions(+), 19 deletions(-) Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved diff --git a/src/arch/x86/include/arch/pci_mmio_cfg_romcc.h b/src/arch/x86/include/arch/pci_mmio_cfg_romcc.h new file mode 100644 index 0000000..00e8e41 --- /dev/null +++ b/src/arch/x86/include/arch/pci_mmio_cfg_romcc.h @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _PCI_MMIO_CFG_ROMCC_H +#define _PCI_MMIO_CFG_ROMCC_H + +#include <stdint.h> +#include <device/mmio.h> +#include <device/pci_type.h> + + +static __always_inline +uint8_t pci_mmio_read_config8(pci_devfn_t dev, uint16_t reg) +{ + void *addr; + addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | reg); + return read8(addr); +} + +static __always_inline +uint16_t pci_mmio_read_config16(pci_devfn_t dev, uint16_t reg) +{ + void *addr; + addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~1)); + return read16(addr); +} + +static __always_inline +uint32_t pci_mmio_read_config32(pci_devfn_t dev, uint16_t reg) +{ + void *addr; + addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~3)); + return read32(addr); +} + +static __always_inline +void pci_mmio_write_config8(pci_devfn_t dev, uint16_t reg, uint8_t value) +{ + void *addr; + addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | reg); + write8(addr, value); +} + +static __always_inline +void pci_mmio_write_config16(pci_devfn_t dev, uint16_t reg, uint16_t value) +{ + void *addr; + addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~1)); + write16(addr, value); +} + +static __always_inline +void pci_mmio_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value) +{ + void *addr; + addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~3)); + write32(addr, value); +} + +#endif /* _PCI_MMIO_CFG_ROMCC_H */ diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h index e706216..4278ed0 100644 --- a/src/arch/x86/include/arch/pci_ops.h +++ b/src/arch/x86/include/arch/pci_ops.h @@ -15,6 +15,12 @@ #define ARCH_I386_PCI_OPS_H #include <arch/pci_io_cfg.h> + +#if defined(__ROMCC__) +/* Must come before <device/pci_mmio_cfg.h> */ +#include <arch/pci_mmio_cfg_romcc.h> +#endif + #include <device/pci_mmio_cfg.h> #endif /* ARCH_I386_PCI_OPS_H */ diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index 711a403..baa45be 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -26,9 +26,15 @@ ramstage-y += pci_class.c ramstage-y += pci_device.c -ramstage-y += pci_ops.c ramstage-y += pci_rom.c +bootblock-y += pci_ops.c +verstage-y += pci_ops.c +romstage-y += pci_ops.c +postcar-y += pci_ops.c +ramstage-y += pci_ops.c +smm-y += pci_ops.c + ramstage-$(CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT) += hypertransport.c ramstage-$(CONFIG_PCIX_PLUGIN_SUPPORT) += pcix_device.c ramstage-$(CONFIG_PCIEXP_PLUGIN_SUPPORT) += pciexp_device.c diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c index bdf8ec4..34f9d1e 100644 --- a/src/device/pci_ops.c +++ b/src/device/pci_ops.c @@ -10,3 +10,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ + +#include <stdint.h> + +u8 *const pci_mmconf = (void *)(uintptr_t)CONFIG_MMCONF_BASE_ADDRESS; diff --git a/src/include/device/pci_mmio_cfg.h b/src/include/device/pci_mmio_cfg.h index e701915..5567ed8 100644 --- a/src/include/device/pci_mmio_cfg.h +++ b/src/include/device/pci_mmio_cfg.h @@ -20,55 +20,74 @@ #include <device/mmio.h> #include <device/pci_type.h> +#if !defined(__ROMCC__) + +/* By not assigning this to CONFIG_MMCONF_BASE_ADDRESS here we + * prevent some sub-optimal constant folding. */ +extern u8 *const pci_mmconf; + +/* Using a unique datatype for MMIO writes makes the pointers to _not_ + * qualify for pointer aliasing with any other objects in memory. + * + * MMIO offset is a value originally derived from 'struct device *' + * in ramstage. For the compiler to not discard this MMIO offset value + * from CPU registers after any MMIO writes, -fstrict-aliasing has to + * be also set for the build. + * + * Bottom 12 bits (4 KiB) are reserved to address the registers of a + * single PCI function. Declare the bank as a union to avoid some casting + * in the functions below. + */ +union pci_bank { + uint8_t reg8[4096]; + uint16_t reg16[4096 / sizeof(uint16_t)]; + uint32_t reg32[4096 / sizeof(uint32_t)]; +}; + +static __always_inline +volatile union pci_bank *pcicfg(pci_devfn_t dev) +{ + return (void *)&pci_mmconf[PCI_DEVFN_OFFSET(dev)]; +} static __always_inline uint8_t pci_mmio_read_config8(pci_devfn_t dev, uint16_t reg) { - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | reg); - return read8(addr); + return pcicfg(dev)->reg8[reg]; } static __always_inline uint16_t pci_mmio_read_config16(pci_devfn_t dev, uint16_t reg) { - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~1)); - return read16(addr); + return pcicfg(dev)->reg16[reg / sizeof(uint16_t)]; } static __always_inline uint32_t pci_mmio_read_config32(pci_devfn_t dev, uint16_t reg) { - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~3)); - return read32(addr); + return pcicfg(dev)->reg32[reg / sizeof(uint32_t)]; } static __always_inline void pci_mmio_write_config8(pci_devfn_t dev, uint16_t reg, uint8_t value) { - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | reg); - write8(addr, value); + pcicfg(dev)->reg8[reg] = value; } static __always_inline void pci_mmio_write_config16(pci_devfn_t dev, uint16_t reg, uint16_t value) { - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~1)); - write16(addr, value); + pcicfg(dev)->reg16[reg / sizeof(uint16_t)] = value; } static __always_inline void pci_mmio_write_config32(pci_devfn_t dev, uint16_t reg, uint32_t value) { - void *addr; - addr = (void *)(uintptr_t)(CONFIG_MMCONF_BASE_ADDRESS | dev | (reg & ~3)); - write32(addr, value); + pcicfg(dev)->reg32[reg / sizeof(uint32_t)] = value; } +#endif /* !defined(__ROMCC__) */ + #if CONFIG(MMCONF_SUPPORT) /* Avoid name collisions as different stages have different signature diff --git a/src/include/device/pci_type.h b/src/include/device/pci_type.h index 27d3558..4d8c2a3 100644 --- a/src/include/device/pci_type.h +++ b/src/include/device/pci_type.h @@ -18,6 +18,10 @@ typedef u32 pci_devfn_t; +/* Convert pci_devfn_t to offset in MMCONF space. + * As it is one-to-one, nothing needs to be done. */ +#define PCI_DEVFN_OFFSET(x) ((x)) + #define PCI_DEV(SEGBUS, DEV, FN) ( \ (((SEGBUS) & 0xFFF) << 20) | \ (((DEV) & 0x1F) << 15) | \ -- To view, visit https://review.coreboot.org/c/coreboot/+/31752 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id112aa5e729ffd8015bb806786bdee38783b7ea9 Gerrit-Change-Number: 31752 Gerrit-PatchSet: 9 Gerrit-Owner: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: merged

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Change in ...coreboot[master]: Add empty stubs for KASAN to coreboot. Kconfig default settings set t...
by Abdullah Zafar (Code Review) 07 Apr '19

07 Apr '19

Abdullah Zafar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32220 Change subject: Add empty stubs for KASAN to coreboot. Kconfig default settings set to compile with KASAN. ...................................................................... Add empty stubs for KASAN to coreboot. Kconfig default settings set to compile with KASAN. Signed-off-by: 11abdullah11 <abdullahzafar4876(a)yahoo.com> Change-Id: I424dcb16fc33f356fca823866a7c869484c42870 modified: src/Kconfig modified: src/lib/Makefile.inc new file: src/lib/kasan.c Change-Id: Ib40ab0116550fd2a5cb208abc39f0df6d80192fa --- A .tmpconfig.lintkyQ0Qt A .tmpconfig.lintq3Y6J5 A .tmpconfig.linttyjU7F A .tmpconfig.lintvEnN0V M src/Kconfig M src/lib/Makefile.inc A src/lib/kasan.c 7 files changed, 46 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/32220/1 diff --git a/.tmpconfig.lintkyQ0Qt b/.tmpconfig.lintkyQ0Qt new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/.tmpconfig.lintkyQ0Qt diff --git a/.tmpconfig.lintq3Y6J5 b/.tmpconfig.lintq3Y6J5 new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/.tmpconfig.lintq3Y6J5 diff --git a/.tmpconfig.linttyjU7F b/.tmpconfig.linttyjU7F new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/.tmpconfig.linttyjU7F diff --git a/.tmpconfig.lintvEnN0V b/.tmpconfig.lintvEnN0V new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/.tmpconfig.lintvEnN0V diff --git a/src/Kconfig b/src/Kconfig index 62b3818..263cde3 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -219,6 +219,15 @@ coverage information in CBMEM for extraction from user space. If unsure, say N. +config KASAN + bool "Kernel Address sanitizer support" + default y + help + Instrument the code with checks for UAF and OOB erros. If unsure, + say N because it adds a small performance penalty and may abort + on code that happens to work in spite of the UB. + + config UBSAN bool "Undefined behavior sanitizer support" default n diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 1350152..88afaaa 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -19,6 +19,12 @@ CFLAGS_ramstage += -fsanitize=undefined endif +ifeq ($(CONFIG_KASAN),y) +ramstage-y += kasan.c +CFLAGS_ramstage += -fsanitize=kernel-address +endif + + decompressor-y += decompressor.c $(call src-to-obj,decompressor,$(dir)/decompressor.c): $(objcbfs)/bootblock.lz4 $(call src-to-obj,decompressor,$(dir)/decompressor.c): CCACHE_EXTRAFILES=$(objcbfs)/bootblock.lz4 @@ -83,7 +89,7 @@ romstage-y += memrange.c romstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c ramstage-$(CONFIG_PRIMITIVE_MEMTEST) += primitive_memtest.c -romstage-y += ramtest.c +romstage-$(CONFIG_CACHE_AS_RAM) += ramtest.c romstage-$(CONFIG_GENERIC_GPIO_LIB) += gpio.c ramstage-y += region_file.c romstage-y += region_file.c diff --git a/src/lib/kasan.c b/src/lib/kasan.c new file mode 100644 index 0000000..28ff1ed --- /dev/null +++ b/src/lib/kasan.c @@ -0,0 +1,30 @@ +#include <stddef.h> + +/* + *Empty stubs for required by gcc to add compiler code + */ + +void __asan_handle_no_return(void); +void __asan_load1_noabort(unsigned long addr); +void __asan_store1_noabort(unsigned long addr); +void __asan_load2_noabort(unsigned long addr); +void __asan_store2_noabort(unsigned long addr); +void __asan_load4_noabort(unsigned long addr); +void __asan_store4_noabort(unsigned long addr); +void __asan_load8_noabort(unsigned long addr); +void __asan_store8_noabort(unsigned long addr); +void __asan_loadN_noabort(unsigned long addr,size_t); +void __asan_storeN_noabort(unsigned long addr,size_t); + + +void __asan_handle_no_return(void){ } +void __asan_load1_noabort(unsigned long addr){ } +void __asan_store1_noabort(unsigned long addr){ } +void __asan_load2_noabort(unsigned long addr){ } +void __asan_store2_noabort(unsigned long addr){ } +void __asan_load4_noabort(unsigned long addr){ } +void __asan_store4_noabort(unsigned long addr){ } +void __asan_store8_noabort(unsigned long addr){ } +void __asan_load8_noabort(unsigned long addr){ } +void __asan_loadN_noabort(unsigned long addr,size_t i){ } +void __asan_storeN_noabort(unsigned long addr,size_t i){ } -- To view, visit https://review.coreboot.org/c/coreboot/+/32220 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib40ab0116550fd2a5cb208abc39f0df6d80192fa Gerrit-Change-Number: 32220 Gerrit-PatchSet: 1 Gerrit-Owner: Abdullah Zafar <abdullahzafar4876(a)yahoo.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src: Use include <delay.h> when appropriate
by HAOUAS Elyes (Code Review) 06 Apr '19

06 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32012 Change subject: src: Use include <delay.h> when appropriate ...................................................................... src: Use include <delay.h> when appropriate Change-Id: I23bc0191ca8fcd88364e5c08be7c90195019e399 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/riscv/misc.c M src/cpu/ti/am335x/monotonic_timer.c M src/drivers/aspeed/ast2050/ast2050.c M src/drivers/aspeed/common/ast_dp501.c M src/drivers/aspeed/common/ast_main.c M src/drivers/aspeed/common/ast_post.c M src/drivers/emulation/qemu/bochs.c M src/drivers/emulation/qemu/cirrus.c M src/drivers/intel/gma/intel_ddi.c M src/drivers/intel/gma/vbt.c M src/drivers/net/ne2k.c M src/drivers/siemens/nc_fpga/nc_fpga.c M src/drivers/sil/3114/sil_sata.c M src/drivers/spi/spi_flash.c M src/drivers/xgi/common/vb_init.c M src/drivers/xgi/common/vb_setmode.c M src/drivers/xgi/common/xgi_coreboot.c M src/drivers/xgi/common/xgi_coreboot.h M src/drivers/xgi/z9s/z9s.c M src/ec/google/chromeec/crosec_proto.c M src/ec/google/chromeec/ec_i2c.c M src/include/cpu/x86/lapic.h M src/lib/bootblock.c M src/lib/decompressor.c M src/lib/hardwaremain.c M src/mainboard/apple/macbook21/mainboard.c M src/mainboard/apple/macbook21/smihandler.c M src/mainboard/asus/kfsn4-dre/romstage.c M src/mainboard/cubietech/cubieboard/bootblock.c M src/mainboard/gizmosphere/gizmo/mainboard.c M src/mainboard/google/foster/mainboard.c M src/mainboard/google/gale/mainboard.c M src/mainboard/google/oak/bootblock.c M src/mainboard/google/slippy/variants/peppy/romstage.c M src/mainboard/google/slippy/variants/wolf/romstage.c M src/mainboard/google/smaug/romstage.c M src/mainboard/google/veyron/romstage.c M src/mainboard/google/veyron_mickey/mainboard.c M src/mainboard/google/veyron_mickey/romstage.c M src/mainboard/google/veyron_rialto/mainboard.c M src/mainboard/google/veyron_rialto/romstage.c M src/mainboard/hp/dl165_g6_fam10/romstage.c M src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c M src/mainboard/intel/galileo/vboot.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/lenovo/g505s/mainboard_smi.c M src/mainboard/lenovo/s230u/smihandler.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/x200/dock.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/lenovo/z61t/romstage.c M src/mainboard/msi/ms9652_fam10/romstage.c M src/mainboard/opencellular/elgon/mainboard.c M src/mainboard/packardbell/ms2290/mainboard.c M src/mainboard/packardbell/ms2290/romstage.c M src/mainboard/packardbell/ms2290/smihandler.c M src/mainboard/roda/rk886ex/mainboard.c M src/mainboard/roda/rk886ex/romstage.c M src/mainboard/siemens/mc_tcu3/ptn3460.c M src/mainboard/siemens/mc_tcu3/ptn3460.h M src/mainboard/supermicro/h8dmr_fam10/romstage.c M src/mainboard/supermicro/h8qme_fam10/romstage.c M src/mainboard/tyan/s2912_fam10/romstage.c M src/northbridge/amd/amdmct/wrappers/mcti_d.c M src/northbridge/amd/pi/agesawrapper.c M src/northbridge/intel/fsp_rangeley/northbridge.c M src/northbridge/intel/gm45/gma.c M src/northbridge/intel/haswell/minihd.c M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/x4x/gma.c M src/northbridge/intel/x4x/raminit.c M src/security/vboot/vboot_logic.c M src/soc/amd/common/block/pi/agesawrapper.c M src/soc/amd/stoneyridge/hda.c M src/soc/amd/stoneyridge/sata.c M src/soc/amd/stoneyridge/smihandler.c M src/soc/cavium/cn81xx/include/soc/timer.h M src/soc/cavium/cn81xx/spi.c M src/soc/cavium/common/bdk-coreboot.c M src/soc/cavium/common/bootblock.c M src/soc/intel/baytrail/gfx.c M src/soc/intel/braswell/sata.c M src/soc/intel/broadwell/adsp.c M src/soc/intel/broadwell/ehci.c M src/soc/intel/broadwell/hda.c M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/minihd.c M src/soc/intel/broadwell/pch.c M src/soc/intel/broadwell/romstage/uart.c M src/soc/intel/cannonlake/lpc.c M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/systemagent/systemagent_early.c M src/soc/intel/fsp_baytrail/gfx.c M src/soc/intel/fsp_broadwell_de/smihandler.c M src/soc/intel/icelake/lpc.c M src/soc/intel/quark/gpio_i2c.c M src/soc/intel/quark/include/soc/reg_access.h M src/soc/intel/quark/reg_access.c M src/soc/intel/quark/romstage/pcie.c M src/soc/intel/skylake/cpu.c M src/soc/intel/skylake/lpc.c M src/soc/mediatek/common/include/soc/rtc_common.h M src/soc/mediatek/common/rtc.c M src/soc/mediatek/common/timer.c M src/soc/mediatek/common/usb.c M src/soc/mediatek/mt8173/ddp.c M src/soc/mediatek/mt8173/dramc_pi_calibration_api.c M src/soc/mediatek/mt8173/emi.c M src/soc/mediatek/mt8173/rtc.c M src/soc/nvidia/tegra/gpio.c M src/soc/nvidia/tegra210/mipi_dsi.c M src/soc/qualcomm/ipq40xx/i2c.c M src/soc/qualcomm/ipq806x/i2c.c M src/soc/qualcomm/qcs405/timer.c M src/soc/qualcomm/sdm845/clock.c M src/soc/qualcomm/sdm845/gpio.c M src/soc/qualcomm/sdm845/timer.c M src/soc/rockchip/common/pwm.c M src/soc/rockchip/common/vop.c M src/soc/rockchip/rk3288/soc.c M src/soc/rockchip/rk3288/timer.c M src/soc/rockchip/rk3288/tsadc.c M src/soc/rockchip/rk3399/timer.c M src/soc/rockchip/rk3399/usb.c M src/soc/samsung/exynos5250/clock_init.c M src/soc/samsung/exynos5250/cpu.c M src/soc/samsung/exynos5250/timer.c M src/soc/samsung/exynos5420/clock_init.c M src/soc/samsung/exynos5420/cpu.c M src/soc/samsung/exynos5420/fimd.c M src/soc/samsung/exynos5420/timer.c M src/southbridge/amd/agesa/hudson/hda.c M src/southbridge/amd/agesa/hudson/imc.c M src/southbridge/amd/agesa/hudson/sata.c M src/southbridge/amd/agesa/hudson/sd.c M src/southbridge/amd/agesa/hudson/smihandler.c M src/southbridge/amd/pi/hudson/hda.c M src/southbridge/amd/pi/hudson/imc.c M src/southbridge/amd/pi/hudson/sata.c M src/southbridge/amd/pi/hudson/sd.c M src/southbridge/amd/pi/hudson/smihandler.c M src/southbridge/intel/bd82x6x/early_pch.c M src/southbridge/intel/fsp_rangeley/soc.c M src/southbridge/intel/lynxpoint/azalia.c M src/southbridge/intel/lynxpoint/smihandler.c M src/southbridge/nvidia/mcp55/early_setup_car.c M src/southbridge/nvidia/mcp55/sata.c 147 files changed, 94 insertions(+), 195 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/32012/1 diff --git a/src/arch/riscv/misc.c b/src/arch/riscv/misc.c index 1909dbc..bebaa70 100644 --- a/src/arch/riscv/misc.c +++ b/src/arch/riscv/misc.c @@ -11,8 +11,6 @@ * GNU General Public License for more details. */ -#include <delay.h> - void init_timer(void) { } diff --git a/src/cpu/ti/am335x/monotonic_timer.c b/src/cpu/ti/am335x/monotonic_timer.c index 94db418..0599417 100644 --- a/src/cpu/ti/am335x/monotonic_timer.c +++ b/src/cpu/ti/am335x/monotonic_timer.c @@ -14,7 +14,6 @@ */ #include <stdint.h> -#include <delay.h> #include <timer.h> #include "dmtimer.h" diff --git a/src/drivers/aspeed/ast2050/ast2050.c b/src/drivers/aspeed/ast2050/ast2050.c index 035d5c6..631372d 100644 --- a/src/drivers/aspeed/ast2050/ast2050.c +++ b/src/drivers/aspeed/ast2050/ast2050.c @@ -12,17 +12,15 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include <delay.h> + #include <stdlib.h> #include <arch/io.h> #include <edid.h> - #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> - #include <pc80/vga.h> #include "../common/aspeed_coreboot.h" diff --git a/src/drivers/aspeed/common/ast_dp501.c b/src/drivers/aspeed/common/ast_dp501.c index 46b76f5..2e8b897 100644 --- a/src/drivers/aspeed/common/ast_dp501.c +++ b/src/drivers/aspeed/common/ast_dp501.c @@ -15,6 +15,8 @@ * GNU General Public License for more details. */ +#include <delay.h> + #include "ast_drv.h" static void send_ack(struct ast_private *ast) diff --git a/src/drivers/aspeed/common/ast_main.c b/src/drivers/aspeed/common/ast_main.c index 3a0cf20..086b0a4 100644 --- a/src/drivers/aspeed/common/ast_main.c +++ b/src/drivers/aspeed/common/ast_main.c @@ -26,8 +26,10 @@ /* * Authors: Dave Airlie <airlied(a)redhat.com> */ -#include "ast_drv.h" +#include <delay.h> + +#include "ast_drv.h" #include "ast_dram_tables.h" void ast_set_index_reg_mask(struct ast_private *ast, diff --git a/src/drivers/aspeed/common/ast_post.c b/src/drivers/aspeed/common/ast_post.c index 0727443..5f935b9 100644 --- a/src/drivers/aspeed/common/ast_post.c +++ b/src/drivers/aspeed/common/ast_post.c @@ -29,8 +29,9 @@ #define COREBOOT_AST_FAILOVER_TIMEOUT 10000000 -#include "ast_drv.h" +#include <delay.h> +#include "ast_drv.h" #include "ast_dram_tables.h" static void ast_init_dram_2300(struct drm_device *dev); diff --git a/src/drivers/emulation/qemu/bochs.c b/src/drivers/emulation/qemu/bochs.c index 2310c9e..22095ef 100644 --- a/src/drivers/emulation/qemu/bochs.c +++ b/src/drivers/emulation/qemu/bochs.c @@ -12,11 +12,9 @@ */ #include <stdint.h> -#include <delay.h> #include <edid.h> #include <stdlib.h> #include <arch/io.h> - #include <boot/coreboot_tables.h> #include <console/console.h> #include <device/device.h> diff --git a/src/drivers/emulation/qemu/cirrus.c b/src/drivers/emulation/qemu/cirrus.c index 04edef4..ed5a4f4 100644 --- a/src/drivers/emulation/qemu/cirrus.c +++ b/src/drivers/emulation/qemu/cirrus.c @@ -15,17 +15,14 @@ */ #include <stdint.h> -#include <delay.h> #include <edid.h> #include <stdlib.h> - #include <boot/coreboot_tables.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> - #include <pc80/vga.h> #include <pc80/vga_io.h> diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c index 58134db..471a5d2 100644 --- a/src/drivers/intel/gma/intel_ddi.c +++ b/src/drivers/intel/gma/intel_ddi.c @@ -25,20 +25,19 @@ * Eugeni Dodonov <eugeni.dodonov(a)intel.com> * */ + #include <types.h> #include <stdlib.h> #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <console/console.h> -#include <delay.h> #include <arch/acpi.h> #include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include <smbios.h> #include <device/pci.h> #include <ec/google/chromeec/ec.h> - #include <cpu/x86/tsc.h> #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> diff --git a/src/drivers/intel/gma/vbt.c b/src/drivers/intel/gma/vbt.c index 7455704..fa50ae9 100644 --- a/src/drivers/intel/gma/vbt.c +++ b/src/drivers/intel/gma/vbt.c @@ -16,7 +16,6 @@ */ #include <device/pci_ops.h> -#include <delay.h> #include <device/device.h> #include <string.h> #include <device/pci.h> diff --git a/src/drivers/net/ne2k.c b/src/drivers/net/ne2k.c index 6f8aca2..e3dd948 100644 --- a/src/drivers/net/ne2k.c +++ b/src/drivers/net/ne2k.c @@ -29,7 +29,6 @@ #include <arch/io.h> #include <console/ne2k.h> -#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> diff --git a/src/drivers/siemens/nc_fpga/nc_fpga.c b/src/drivers/siemens/nc_fpga/nc_fpga.c index ef1f2f2..fb681ad 100644 --- a/src/drivers/siemens/nc_fpga/nc_fpga.c +++ b/src/drivers/siemens/nc_fpga/nc_fpga.c @@ -19,9 +19,9 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include <device/mmio.h> -#include <delay.h> #include <hwilib.h> #include <bootstate.h> + #include "nc_fpga.h" static void *nc_fpga_bar0; diff --git a/src/drivers/sil/3114/sil_sata.c b/src/drivers/sil/3114/sil_sata.c index 4908413f..dd6481a 100644 --- a/src/drivers/sil/3114/sil_sata.c +++ b/src/drivers/sil/3114/sil_sata.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <delay.h> #include <stdlib.h> #include <console/console.h> #include <device/device.h> diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 71dc660..82398dd 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -11,14 +11,13 @@ #include <assert.h> #include <boot_device.h> #include <cpu/x86/smm.h> -#include <delay.h> #include <stdlib.h> #include <string.h> #include <spi-generic.h> #include <spi_flash.h> +#include <timer.h> #include "spi_flash_internal.h" -#include <timer.h> static void spi_flash_addr(u32 addr, u8 *cmd) { diff --git a/src/drivers/xgi/common/vb_init.c b/src/drivers/xgi/common/vb_init.c index 0d25e25..a20c068 100644 --- a/src/drivers/xgi/common/vb_init.c +++ b/src/drivers/xgi/common/vb_init.c @@ -17,14 +17,16 @@ * GNU General Public License for more details. */ +#include <delay.h> + #include "xgi_coreboot.h" #include "vstruct.h" - #include "XGIfb.h" #include "vb_def.h" #include "vb_util.h" #include "vb_setmode.h" #include "vb_init.h" + static const unsigned short XGINew_DDRDRAM_TYPE340[4][2] = { { 16, 0x45}, { 8, 0x35}, diff --git a/src/drivers/xgi/common/vb_setmode.c b/src/drivers/xgi/common/vb_setmode.c index e80bc35..162d00c 100644 --- a/src/drivers/xgi/common/vb_setmode.c +++ b/src/drivers/xgi/common/vb_setmode.c @@ -14,11 +14,11 @@ * GNU General Public License for more details. */ +#include <delay.h> + #include "xgi_coreboot.h" #include "vstruct.h" - #include "XGIfb.h" - #include "vb_def.h" #include "vb_init.h" #include "vb_util.h" diff --git a/src/drivers/xgi/common/xgi_coreboot.c b/src/drivers/xgi/common/xgi_coreboot.c index 745baa2..5aba472 100644 --- a/src/drivers/xgi/common/xgi_coreboot.c +++ b/src/drivers/xgi/common/xgi_coreboot.c @@ -15,27 +15,23 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include <delay.h> + #include <stdlib.h> #include <vbe.h> - #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> - #include <pc80/vga.h> #include "xgi_coreboot.h" #include "vstruct.h" - #include "XGIfb.h" #include "XGI_main.h" #include "vb_init.h" #include "vb_util.h" #include "vb_setmode.h" - #include "XGI_main.c" static int xgi_vbe_valid; diff --git a/src/drivers/xgi/common/xgi_coreboot.h b/src/drivers/xgi/common/xgi_coreboot.h index dc8f49e..41952d6 100644 --- a/src/drivers/xgi/common/xgi_coreboot.h +++ b/src/drivers/xgi/common/xgi_coreboot.h @@ -19,12 +19,10 @@ #ifndef _XGI_COREBOOT_ #define _XGI_COREBOOT_ -#include <delay.h> #include <stdlib.h> #include <stdint.h> #include <arch/io.h> #include <device/mmio.h> - #include <console/console.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/drivers/xgi/z9s/z9s.c b/src/drivers/xgi/z9s/z9s.c index 3b46811..1925514 100644 --- a/src/drivers/xgi/z9s/z9s.c +++ b/src/drivers/xgi/z9s/z9s.c @@ -12,9 +12,8 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ -#include <delay.h> -#include <stdlib.h> +#include <stdlib.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/ec/google/chromeec/crosec_proto.c b/src/ec/google/chromeec/crosec_proto.c index 928cc6c..e2fa3dd 100644 --- a/src/ec/google/chromeec/crosec_proto.c +++ b/src/ec/google/chromeec/crosec_proto.c @@ -14,9 +14,9 @@ */ #include <console/console.h> -#include <delay.h> #include <stdint.h> #include <string.h> + #include "ec.h" #include "ec_commands.h" #include "ec_message.h" diff --git a/src/ec/google/chromeec/ec_i2c.c b/src/ec/google/chromeec/ec_i2c.c index 2eecced..c3e1968 100644 --- a/src/ec/google/chromeec/ec_i2c.c +++ b/src/ec/google/chromeec/ec_i2c.c @@ -14,7 +14,6 @@ */ #include <console/console.h> -#include <delay.h> #include <device/i2c_simple.h> #include <stdint.h> #include <string.h> diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 8108174..3d94b83 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -3,6 +3,7 @@ #include <cpu/x86/lapic_def.h> #include <cpu/x86/msr.h> +#include <delay.h> #include <halt.h> #include <smp/node.h> diff --git a/src/lib/bootblock.c b/src/lib/bootblock.c index 43674ef..19d6d67 100644 --- a/src/lib/bootblock.c +++ b/src/lib/bootblock.c @@ -17,7 +17,6 @@ #include <arch/exception.h> #include <bootblock_common.h> #include <console/console.h> -#include <delay.h> #include <pc80/mc146818rtc.h> #include <program_loading.h> #include <symbols.h> diff --git a/src/lib/decompressor.c b/src/lib/decompressor.c index 0529d113..5a2055b 100644 --- a/src/lib/decompressor.c +++ b/src/lib/decompressor.c @@ -16,7 +16,6 @@ #include <bootblock_common.h> #include <commonlib/compression.h> -#include <delay.h> #include <program_loading.h> #include <symbols.h> diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 2881162..9b23408 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -27,7 +27,6 @@ #include <version.h> #include <device/device.h> #include <device/pci.h> -#include <delay.h> #include <stdlib.h> #include <boot/tables.h> #include <program_loading.h> diff --git a/src/mainboard/apple/macbook21/mainboard.c b/src/mainboard/apple/macbook21/mainboard.c index 25c4660..798fc12 100644 --- a/src/mainboard/apple/macbook21/mainboard.c +++ b/src/mainboard/apple/macbook21/mainboard.c @@ -16,7 +16,6 @@ */ #include <device/device.h> -#include <delay.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <arch/interrupt.h> @@ -24,6 +23,7 @@ #include <arch/acpigen.h> #include <drivers/intel/gma/int15.h> #include <ec/acpi/ec.h> + #define PANEL INT15_5F35_CL_DISPLAY_DEFAULT static acpi_cstate_t cst_entries[] = { diff --git a/src/mainboard/apple/macbook21/smihandler.c b/src/mainboard/apple/macbook21/smihandler.c index baff7c1..88cc4c0 100644 --- a/src/mainboard/apple/macbook21/smihandler.c +++ b/src/mainboard/apple/macbook21/smihandler.c @@ -18,7 +18,6 @@ #include <cpu/x86/smm.h> #include <southbridge/intel/i82801gx/nvs.h> #include <southbridge/intel/common/pmutil.h> -#include <delay.h> #define GPE_EC_SCI 12 diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index dbf704b..91ec5f9 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -33,7 +33,6 @@ #include <cpu/amd/msr.h> #include <southbridge/amd/common/reset.h> #include <southbridge/nvidia/ck804/early_smbus.h> -#include <delay.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627thg/w83627thg.h> #include <cpu/x86/bist.h> diff --git a/src/mainboard/cubietech/cubieboard/bootblock.c b/src/mainboard/cubietech/cubieboard/bootblock.c index e1eb820..4002e56 100644 --- a/src/mainboard/cubietech/cubieboard/bootblock.c +++ b/src/mainboard/cubietech/cubieboard/bootblock.c @@ -23,7 +23,6 @@ #include <bootblock_common.h> #include <console/uart.h> #include <console/console.h> -#include <delay.h> #include <cpu/allwinner/a10/gpio.h> #include <cpu/allwinner/a10/clock.h> #include <cpu/allwinner/a10/dramc.h> diff --git a/src/mainboard/gizmosphere/gizmo/mainboard.c b/src/mainboard/gizmosphere/gizmo/mainboard.c index 5d4fbd7..ac6dad1 100644 --- a/src/mainboard/gizmosphere/gizmo/mainboard.c +++ b/src/mainboard/gizmosphere/gizmo/mainboard.c @@ -16,7 +16,6 @@ #include <device/mmio.h> #include <console/console.h> -#include <delay.h> #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> diff --git a/src/mainboard/google/foster/mainboard.c b/src/mainboard/google/foster/mainboard.c index d3091ad..daddf5c 100644 --- a/src/mainboard/google/foster/mainboard.c +++ b/src/mainboard/google/foster/mainboard.c @@ -16,7 +16,6 @@ #include <arch/mmu.h> #include <boot/coreboot_tables.h> -#include <delay.h> #include <device/device.h> #include <memrange.h> #include <soc/addressmap.h> diff --git a/src/mainboard/google/gale/mainboard.c b/src/mainboard/google/gale/mainboard.c index 5684f8f..c8ab88a 100644 --- a/src/mainboard/google/gale/mainboard.c +++ b/src/mainboard/google/gale/mainboard.c @@ -16,7 +16,6 @@ #include <boardid.h> #include <boot/coreboot_tables.h> -#include <delay.h> #include <device/device.h> #include <gpio.h> #include <soc/clock.h> diff --git a/src/mainboard/google/oak/bootblock.c b/src/mainboard/google/oak/bootblock.c index 4df7eeb..3c50389 100644 --- a/src/mainboard/google/oak/bootblock.c +++ b/src/mainboard/google/oak/bootblock.c @@ -15,7 +15,6 @@ #include <boardid.h> #include <bootblock_common.h> -#include <delay.h> #include <gpio.h> #include <device/mmio.h> #include <soc/gpio.h> diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index e47edc7..37c7853 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <delay.h> #include <stdint.h> #include <stdlib.h> #include <string.h> diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index 3125efe..731b357 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <delay.h> #include <stdint.h> #include <stdlib.h> #include <string.h> diff --git a/src/mainboard/google/smaug/romstage.c b/src/mainboard/google/smaug/romstage.c index fd7c07f..1d10d0e 100644 --- a/src/mainboard/google/smaug/romstage.c +++ b/src/mainboard/google/smaug/romstage.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <delay.h> #include <soc/addressmap.h> #include <device/i2c_simple.h> #include <soc/clock.h> diff --git a/src/mainboard/google/veyron/romstage.c b/src/mainboard/google/veyron/romstage.c index 9407528..3870b63 100644 --- a/src/mainboard/google/veyron/romstage.c +++ b/src/mainboard/google/veyron/romstage.c @@ -20,7 +20,6 @@ #include <cbmem.h> #include <console/console.h> #include <device/mmio.h> -#include <delay.h> #include <program_loading.h> #include <soc/sdram.h> #include <soc/clock.h> diff --git a/src/mainboard/google/veyron_mickey/mainboard.c b/src/mainboard/google/veyron_mickey/mainboard.c index f29c9d0..bb23973 100644 --- a/src/mainboard/google/veyron_mickey/mainboard.c +++ b/src/mainboard/google/veyron_mickey/mainboard.c @@ -16,7 +16,6 @@ #include <arch/cache.h> #include <device/mmio.h> #include <boot/coreboot_tables.h> -#include <delay.h> #include <device/device.h> #include <device/i2c_simple.h> #include <edid.h> diff --git a/src/mainboard/google/veyron_mickey/romstage.c b/src/mainboard/google/veyron_mickey/romstage.c index a2e8b36..c8a9842 100644 --- a/src/mainboard/google/veyron_mickey/romstage.c +++ b/src/mainboard/google/veyron_mickey/romstage.c @@ -20,7 +20,6 @@ #include <cbmem.h> #include <console/console.h> #include <device/mmio.h> -#include <delay.h> #include <program_loading.h> #include <soc/sdram.h> #include <soc/clock.h> diff --git a/src/mainboard/google/veyron_rialto/mainboard.c b/src/mainboard/google/veyron_rialto/mainboard.c index 0597305..074e6a4 100644 --- a/src/mainboard/google/veyron_rialto/mainboard.c +++ b/src/mainboard/google/veyron_rialto/mainboard.c @@ -17,7 +17,6 @@ #include <device/mmio.h> #include <boot/coreboot_tables.h> #include <console/console.h> -#include <delay.h> #include <device/device.h> #include <device/i2c_simple.h> #include <edid.h> diff --git a/src/mainboard/google/veyron_rialto/romstage.c b/src/mainboard/google/veyron_rialto/romstage.c index 64119c1..d9fc42b 100644 --- a/src/mainboard/google/veyron_rialto/romstage.c +++ b/src/mainboard/google/veyron_rialto/romstage.c @@ -20,7 +20,6 @@ #include <assert.h> #include <cbmem.h> #include <console/console.h> -#include <delay.h> #include <program_loading.h> #include <soc/sdram.h> #include <soc/clock.h> diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 0d6d99c..a1288db 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -27,12 +27,10 @@ #include <device/pci_ops.h> #include <arch/cpu.h> #include <cpu/x86/lapic.h> -#include "option_table.h" #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> #include <spd.h> -#include <delay.h> #include <superio/serverengines/pilot/pilot.h> #include <superio/nsc/pc87417/pc87417.h> #include <cpu/x86/bist.h> @@ -43,12 +41,13 @@ #include <cpu/amd/family_10h-family_15h/init_cpus.h> #include <arch/early_variables.h> #include <cbmem.h> +#include <reset.h> #include <southbridge/amd/common/reset.h> + +#include "option_table.h" +#include "cpu/amd/quadcore/quadcore.c" #include "southbridge/broadcom/bcm5785/early_smbus.c" #include "southbridge/broadcom/bcm5785/early_setup.c" -#include <reset.h> - -#include "cpu/amd/quadcore/quadcore.c" #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c index e1527d8..27b1ac2 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c @@ -18,16 +18,15 @@ * SMI handler -- mostly takes care of SMIs from the EC */ -#include "ec.h" - #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include <delay.h> #include <ec/compal/ene932/ec.h> #include <southbridge/amd/agesa/hudson/hudson.h> #include <southbridge/amd/agesa/hudson/smi.h> +#include "ec.h" + #define ACPI_PM1_CNT_SLEEP(state) ((1 << 13) | (state & 0x7) << 10) enum sleep_states { diff --git a/src/mainboard/intel/galileo/vboot.c b/src/mainboard/intel/galileo/vboot.c index b78ed1b..4b1f09f 100644 --- a/src/mainboard/intel/galileo/vboot.c +++ b/src/mainboard/intel/galileo/vboot.c @@ -14,17 +14,17 @@ #include <assert.h> #include <bootmode.h> -#include <delay.h> #include <device/i2c_simple.h> #include <soc/i2c.h> #include <soc/reg_access.h> -#include "reg_access.h" -#include "gen1.h" -#include "gen2.h" #include <spi_flash.h> #include <security/vboot/vboot_common.h> #include <security/vboot/vbnv.h> +#include "reg_access.h" +#include "gen1.h" +#include "gen2.h" + int clear_recovery_mode_switch(void) { /* Nothing to do */ diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 52432a0..bb4a1db 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -22,6 +22,7 @@ #include <cpu/intel/romstage.h> #include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> +#include <delay.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <device/pnp_ops.h> diff --git a/src/mainboard/lenovo/g505s/mainboard_smi.c b/src/mainboard/lenovo/g505s/mainboard_smi.c index 2eaf7ca..27b1ac2 100644 --- a/src/mainboard/lenovo/g505s/mainboard_smi.c +++ b/src/mainboard/lenovo/g505s/mainboard_smi.c @@ -17,16 +17,16 @@ /* * SMI handler -- mostly takes care of SMIs from the EC */ -#include "ec.h" #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include <delay.h> #include <ec/compal/ene932/ec.h> #include <southbridge/amd/agesa/hudson/hudson.h> #include <southbridge/amd/agesa/hudson/smi.h> +#include "ec.h" + #define ACPI_PM1_CNT_SLEEP(state) ((1 << 13) | (state & 0x7) << 10) enum sleep_states { diff --git a/src/mainboard/lenovo/s230u/smihandler.c b/src/mainboard/lenovo/s230u/smihandler.c index 2f79243..3c4df31 100644 --- a/src/mainboard/lenovo/s230u/smihandler.c +++ b/src/mainboard/lenovo/s230u/smihandler.c @@ -16,16 +16,15 @@ * GNU General Public License for more details. */ -#include "ec.h" - #include <console/console.h> #include <cpu/x86/smm.h> -#include <delay.h> #include <ec/acpi/ec.h> #include <ec/compal/ene932/ec.h> #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/pmutil.h> +#include "ec.h" + #define GPE_PALMDET1 2 #define GPE_PALMDET2 4 #define GPE_EC_SCI 7 diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 070ee59..74cd5692 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -19,6 +19,7 @@ #include <stdint.h> #include <arch/io.h> +#include <delay.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <device/pci_def.h> @@ -32,6 +33,7 @@ #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/common/gpio.h> + #include "dock.h" static void ich7_enable_lpc(void) diff --git a/src/mainboard/lenovo/x200/dock.c b/src/mainboard/lenovo/x200/dock.c index 6e87644..d5f774b 100644 --- a/src/mainboard/lenovo/x200/dock.c +++ b/src/mainboard/lenovo/x200/dock.c @@ -16,17 +16,18 @@ */ #define __SIMPLE_DEVICE__ + #include <console/console.h> #include <arch/io.h> #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> -#include <delay.h> -#include "dock.h" #include <southbridge/intel/i82801ix/i82801ix.h> #include <ec/lenovo/h8/h8.h> #include <ec/acpi/ec.h> +#include "dock.h" + #define LPC_DEV PCI_DEV(0, 0x1f, 0) void h8_mainboard_init_dock (void) diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 39e0ed5..a9dffed 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -19,6 +19,7 @@ #include <stdint.h> #include <arch/io.h> +#include <delay.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <device/pci_def.h> @@ -33,6 +34,7 @@ #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/common/gpio.h> + #include "dock.h" static void ich7_enable_lpc(void) diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 45cd9ec..6755763 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -19,6 +19,7 @@ #include <stdint.h> #include <arch/io.h> +#include <delay.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <device/pci_def.h> @@ -33,6 +34,7 @@ #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/common/gpio.h> + #include "dock.h" static void ich7_enable_lpc(void) diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 9ba90a8..53464e9 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -26,7 +26,6 @@ #include <timestamp.h> #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> -#include <delay.h> #include <cpu/amd/car.h> #include <cpu/amd/msr.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/opencellular/elgon/mainboard.c b/src/mainboard/opencellular/elgon/mainboard.c index d140bc1..74e31e1 100644 --- a/src/mainboard/opencellular/elgon/mainboard.c +++ b/src/mainboard/opencellular/elgon/mainboard.c @@ -20,7 +20,6 @@ #include <libbdk-hal/bdk-config.h> #include <libbdk-hal/bdk-twsi.h> #include <soc/gpio.h> -#include <delay.h> #include <soc/uart.h> #include <console/console.h> #include <soc/clock.h> diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index 8e4293b..09310ae 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -19,7 +19,6 @@ #include <console/console.h> #include <device/device.h> #include <arch/io.h> -#include <delay.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <northbridge/intel/nehalem/nehalem.h> diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index b20c445..df26862 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -29,7 +29,6 @@ #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> #include <ec/acpi/ec.h> -#include <delay.h> #include <timestamp.h> #include <arch/acpi.h> diff --git a/src/mainboard/packardbell/ms2290/smihandler.c b/src/mainboard/packardbell/ms2290/smihandler.c index e4c29b1d..ff13543 100644 --- a/src/mainboard/packardbell/ms2290/smihandler.c +++ b/src/mainboard/packardbell/ms2290/smihandler.c @@ -24,7 +24,6 @@ #include <northbridge/intel/nehalem/nehalem.h> #include <cpu/intel/model_2065x/model_2065x.h> #include <ec/acpi/ec.h> -#include <delay.h> static void mainboard_smm_init(void) { diff --git a/src/mainboard/roda/rk886ex/mainboard.c b/src/mainboard/roda/rk886ex/mainboard.c index 843ca60..91c11d5 100644 --- a/src/mainboard/roda/rk886ex/mainboard.c +++ b/src/mainboard/roda/rk886ex/mainboard.c @@ -18,10 +18,9 @@ #include <device/device.h> #include <arch/io.h> #include <arch/interrupt.h> -#include <delay.h> #include <drivers/intel/gma/int15.h> - #include <ec/acpi/ec.h> + #include "m3885.h" #define DUMP_RUNTIME_REGISTERS 0 diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index dbc4b6c..b3a55a9 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -19,6 +19,7 @@ #include <stdint.h> #include <arch/io.h> #include <device/pnp_ops.h> +#include <delay.h> #include <device/pci_ops.h> #include <device/pci_def.h> #include <cpu/x86/lapic.h> @@ -30,6 +31,7 @@ #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> + #include "option_table.h" static void ich7_enable_lpc(void) diff --git a/src/mainboard/siemens/mc_tcu3/ptn3460.c b/src/mainboard/siemens/mc_tcu3/ptn3460.c index 8143a16..9acc60a 100644 --- a/src/mainboard/siemens/mc_tcu3/ptn3460.c +++ b/src/mainboard/siemens/mc_tcu3/ptn3460.c @@ -16,6 +16,8 @@ #include <console/console.h> #include <hwilib.h> #include <string.h> +#include <delay.h> + #include "soc/i2c.h" #include "ptn3460.h" diff --git a/src/mainboard/siemens/mc_tcu3/ptn3460.h b/src/mainboard/siemens/mc_tcu3/ptn3460.h index 217c68a..8dc002d 100644 --- a/src/mainboard/siemens/mc_tcu3/ptn3460.h +++ b/src/mainboard/siemens/mc_tcu3/ptn3460.h @@ -16,7 +16,6 @@ #ifndef PTN3460_H_ #define PTN3460_H_ -#include <delay.h> #include "lcd_panel.h" #define PTN_SLAVE_ADR 0x20 diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 699808f..b8168c4 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -25,7 +25,6 @@ #include <timestamp.h> #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> -#include <delay.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/x86/bist.h> @@ -37,12 +36,11 @@ #include <cpu/amd/family_10h-family_15h/init_cpus.h> #include <arch/early_variables.h> #include <cbmem.h> - -#include <southbridge/nvidia/mcp55/mcp55.h> // for enable the FAN #include <reset.h> +#include <southbridge/nvidia/mcp55/mcp55.h> // for enable the FAN +#include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "cpu/amd/quadcore/quadcore.c" -#include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index ef6dee9..6d22447 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -26,7 +26,6 @@ #include <timestamp.h> #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> -#include <delay.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/x86/bist.h> @@ -38,11 +37,11 @@ #include <cpu/amd/family_10h-family_15h/init_cpus.h> #include <arch/early_variables.h> #include <cbmem.h> -#include <southbridge/nvidia/mcp55/mcp55.h> // for enable the FAN #include <reset.h> +#include <southbridge/nvidia/mcp55/mcp55.h> // for enable the FAN +#include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "cpu/amd/quadcore/quadcore.c" -#include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 7fca06b..29c71d8 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -25,7 +25,6 @@ #include <timestamp.h> #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> -#include <delay.h> #include <cpu/amd/car.h> #include <cpu/amd/msr.h> #include <superio/winbond/common/winbond.h> diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c index e42085d..7aaf016 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c +++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c @@ -17,9 +17,9 @@ /* Call-backs */ #include <arch/cpu.h> -#include <delay.h> #include <cpu/amd/msr.h> #include <console/console.h> + #include "mcti.h" #define NVRAM_DDR2_800 0 diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index 28f2876..cfa64c4 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -16,7 +16,6 @@ #include <AGESA.h> #include <cbfs.h> #include <cbmem.h> -#include <delay.h> #include <cpu/x86/mtrr.h> #include <FchPlatform.h> #include <heapManager.h> diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index 7663b26..0c08197 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -19,7 +19,6 @@ #include <arch/acpi.h> #include <device/pci_ops.h> #include <stdint.h> -#include <delay.h> #include <cpu/intel/fsp_model_406dx/model_406dx.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 648aa48..23fca16 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -16,10 +16,12 @@ #include <device/mmio.h> #include <console/console.h> -#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <drivers/intel/gma/edid.h> +#include <drivers/intel/gma/opregion.h> +#include <drivers/intel/gma/libgfxinit.h> #include <string.h> #include <device/pci_ops.h> #include <commonlib/helpers.h> @@ -29,9 +31,6 @@ #include "drivers/intel/gma/i915_reg.h" #include "chip.h" #include "gm45.h" -#include <drivers/intel/gma/edid.h> -#include <drivers/intel/gma/opregion.h> -#include <drivers/intel/gma/libgfxinit.h> static struct resource *gtt_res = NULL; diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c index 9a1df0f..a646071 100644 --- a/src/northbridge/intel/haswell/minihd.c +++ b/src/northbridge/intel/haswell/minihd.c @@ -21,7 +21,6 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/mmio.h> -#include <delay.h> #include <stdlib.h> #include <southbridge/intel/lynxpoint/hda_verb.h> diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 3f62d10..107be5f 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -30,8 +30,8 @@ #include <southbridge/intel/bd82x6x/me.h> #include <southbridge/intel/common/smbus.h> #include <cpu/x86/msr.h> -#include <delay.h> #include <lib.h> + #include "raminit_native.h" #include "raminit_common.h" #include "sandybridge.h" diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 2c045e6..261ff16 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -16,17 +16,12 @@ */ #include <console/console.h> -#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> #include <commonlib/helpers.h> #include <cbmem.h> - -#include "drivers/intel/gma/i915_reg.h" -#include "chip.h" -#include "x4x.h" #include <drivers/intel/gma/intel_bios.h> #include <drivers/intel/gma/edid.h> #include <drivers/intel/gma/i915.h> @@ -35,6 +30,10 @@ #include <pc80/vga.h> #include <pc80/vga_io.h> +#include "chip.h" +#include "drivers/intel/gma/i915_reg.h" +#include "x4x.h" + #if CONFIG(SOUTHBRIDGE_INTEL_I82801JX) #include <southbridge/intel/i82801jx/nvs.h> #elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX) diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 72ef1a9..f284ff1 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -21,16 +21,13 @@ #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> #include <arch/cpu.h> -#include <delay.h> #include <halt.h> #include <lib.h> -#include "iomap.h" #if CONFIG(SOUTHBRIDGE_INTEL_I82801GX) #include <southbridge/intel/i82801gx/i82801gx.h> /* smbus_read_byte */ #else #include <southbridge/intel/i82801jx/i82801jx.h> /* smbus_read_byte */ #endif -#include "x4x.h" #include <spd.h> #include <string.h> #include <device/dram/ddr2.h> @@ -38,6 +35,9 @@ #include <mrc_cache.h> #include <timestamp.h> +#include "iomap.h" +#include "x4x.h" + #define MRC_CACHE_VERSION 0 static inline int spd_read_byte(unsigned int device, unsigned int address) diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 0b5763b..2a6f7a6 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -18,7 +18,6 @@ #include <bootmode.h> #include <console/console.h> #include <console/vtxprintf.h> -#include <delay.h> #include <string.h> #include <timestamp.h> #include <vb2_api.h> diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index 485dfd7..4ff6e1a 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -16,7 +16,6 @@ #include <arch/acpi.h> #include <cbmem.h> -#include <delay.h> #include <timestamp.h> #include <amdblocks/s3_resume.h> #include <amdblocks/agesawrapper.h> diff --git a/src/soc/amd/stoneyridge/hda.c b/src/soc/amd/stoneyridge/hda.c index 475fc55..0ab2f91 100644 --- a/src/soc/amd/stoneyridge/hda.c +++ b/src/soc/amd/stoneyridge/hda.c @@ -17,7 +17,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include <delay.h> #include <soc/southbridge.h> static const unsigned short pci_device_ids[] = { diff --git a/src/soc/amd/stoneyridge/sata.c b/src/soc/amd/stoneyridge/sata.c index fc6cdce..52932e2 100644 --- a/src/soc/amd/stoneyridge/sata.c +++ b/src/soc/amd/stoneyridge/sata.c @@ -14,7 +14,6 @@ */ #include <device/device.h> -#include <delay.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index c053d90..c3f4b67 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -21,7 +21,6 @@ #include <cpu/x86/cache.h> #include <arch/acpi.h> #include <arch/hlt.h> -#include <delay.h> #include <device/pci_def.h> #include <soc/smi.h> #include <soc/southbridge.h> diff --git a/src/soc/cavium/cn81xx/include/soc/timer.h b/src/soc/cavium/cn81xx/include/soc/timer.h index 5c4cbd2..4e41311 100644 --- a/src/soc/cavium/cn81xx/include/soc/timer.h +++ b/src/soc/cavium/cn81xx/include/soc/timer.h @@ -18,7 +18,6 @@ #include <inttypes.h> #include <types.h> -#include <delay.h> /* Watchdog functions */ void watchdog_set(const size_t index, unsigned int timeout_ms); diff --git a/src/soc/cavium/cn81xx/spi.c b/src/soc/cavium/cn81xx/spi.c index dd0baf6..2ba25a2 100644 --- a/src/soc/cavium/cn81xx/spi.c +++ b/src/soc/cavium/cn81xx/spi.c @@ -19,7 +19,6 @@ #include <device/mmio.h> #include <assert.h> #include <console/console.h> -#include <delay.h> #include <endian.h> #include <soc/addressmap.h> #include <soc/spi.h> diff --git a/src/soc/cavium/common/bdk-coreboot.c b/src/soc/cavium/common/bdk-coreboot.c index f8fa8d4..740f8e4 100644 --- a/src/soc/cavium/common/bdk-coreboot.c +++ b/src/soc/cavium/common/bdk-coreboot.c @@ -15,13 +15,13 @@ * * This file consists of data imported from bdk-config.c */ + // coreboot #include <string.h> #include <assert.h> #include <device/i2c.h> #include <device/i2c_simple.h> #include <endian.h> -#include <delay.h> #include <soc/timer.h> // BDK diff --git a/src/soc/cavium/common/bootblock.c b/src/soc/cavium/common/bootblock.c index c3f0866..89dc71f 100644 --- a/src/soc/cavium/common/bootblock.c +++ b/src/soc/cavium/common/bootblock.c @@ -16,7 +16,6 @@ #include <arch/exception.h> #include <console/console.h> -#include <delay.h> #include <program_loading.h> #include <symbols.h> #include <timestamp.h> diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 73c0d15..5d6d504 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -16,14 +16,12 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <console/console.h> -#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <drivers/intel/gma/opregion.h> #include <reg_script.h> #include <stdlib.h> - #include <soc/gfx.h> #include <soc/iosf.h> #include <soc/nvs.h> diff --git a/src/soc/intel/braswell/sata.c b/src/soc/intel/braswell/sata.c index ab16745..80031e6 100644 --- a/src/soc/intel/braswell/sata.c +++ b/src/soc/intel/braswell/sata.c @@ -18,7 +18,6 @@ #include <soc/ramstage.h> #include <soc/sata.h> #include <console/console.h> -#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> diff --git a/src/soc/intel/broadwell/adsp.c b/src/soc/intel/broadwell/adsp.c index d0296e0..7658515 100644 --- a/src/soc/intel/broadwell/adsp.c +++ b/src/soc/intel/broadwell/adsp.c @@ -20,7 +20,6 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/mmio.h> -#include <delay.h> #include <soc/adsp.h> #include <soc/device_nvs.h> #include <soc/iobp.h> diff --git a/src/soc/intel/broadwell/ehci.c b/src/soc/intel/broadwell/ehci.c index 53af617..6e4a767 100644 --- a/src/soc/intel/broadwell/ehci.c +++ b/src/soc/intel/broadwell/ehci.c @@ -14,7 +14,6 @@ * GNU General Public License for more details. */ -#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> diff --git a/src/soc/intel/broadwell/hda.c b/src/soc/intel/broadwell/hda.c index 9ef51c6..d1aee92 100644 --- a/src/soc/intel/broadwell/hda.c +++ b/src/soc/intel/broadwell/hda.c @@ -22,7 +22,6 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/mmio.h> -#include <delay.h> #include <soc/intel/common/hda_verb.h> #include <soc/pch.h> #include <soc/ramstage.h> diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index c831c2c..8438ab4 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -15,7 +15,6 @@ */ #include <console/console.h> -#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> diff --git a/src/soc/intel/broadwell/minihd.c b/src/soc/intel/broadwell/minihd.c index 1b2489c..d44e153 100644 --- a/src/soc/intel/broadwell/minihd.c +++ b/src/soc/intel/broadwell/minihd.c @@ -21,7 +21,6 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/mmio.h> -#include <delay.h> #include <stdlib.h> #include <soc/intel/common/hda_verb.h> #include <soc/ramstage.h> diff --git a/src/soc/intel/broadwell/pch.c b/src/soc/intel/broadwell/pch.c index 06c05c0..e555588 100644 --- a/src/soc/intel/broadwell/pch.c +++ b/src/soc/intel/broadwell/pch.c @@ -15,7 +15,6 @@ */ #include <console/console.h> -#include <delay.h> #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/soc/intel/broadwell/romstage/uart.c b/src/soc/intel/broadwell/romstage/uart.c index a3c4c61..58450dd 100644 --- a/src/soc/intel/broadwell/romstage/uart.c +++ b/src/soc/intel/broadwell/romstage/uart.c @@ -14,7 +14,6 @@ */ #include <arch/early_variables.h> -#include <delay.h> #include <device/pci_def.h> #include <reg_script.h> #include <stdint.h> diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index 7c6025c..56fefa5 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -15,8 +15,6 @@ * GNU General Public License for more details. */ -#include "chip.h" -#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <pc80/isa-dma.h> @@ -34,6 +32,8 @@ #include <soc/pci_devs.h> #include <soc/pcr_ids.h> +#include "chip.h" + /* * As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve * certain memory range as reserved range for BIOS usage. diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 9dbfbd4..c847390 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -21,7 +21,6 @@ #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <arch/cpu.h> -#include <delay.h> #include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> #include <soc/cpu.h> diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index a3e278f..61f14a9 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -15,7 +15,6 @@ #include <device/mmio.h> #include <device/pci_ops.h> -#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <intelblocks/systemagent.h> diff --git a/src/soc/intel/fsp_baytrail/gfx.c b/src/soc/intel/fsp_baytrail/gfx.c index 6bde32e..dab9972 100644 --- a/src/soc/intel/fsp_baytrail/gfx.c +++ b/src/soc/intel/fsp_baytrail/gfx.c @@ -15,13 +15,11 @@ */ #include <console/console.h> -#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <reg_script.h> #include <stdlib.h> - #include <soc/gfx.h> #include <soc/iosf.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/fsp_broadwell_de/smihandler.c b/src/soc/intel/fsp_broadwell_de/smihandler.c index 36a01c6..854bd76 100644 --- a/src/soc/intel/fsp_broadwell_de/smihandler.c +++ b/src/soc/intel/fsp_broadwell_de/smihandler.c @@ -15,7 +15,6 @@ * GNU General Public License for more details. */ -#include <delay.h> #include <types.h> #include <console/console.h> #include <cpu/x86/cache.h> diff --git a/src/soc/intel/icelake/lpc.c b/src/soc/intel/icelake/lpc.c index a3bce93..8fe0507 100644 --- a/src/soc/intel/icelake/lpc.c +++ b/src/soc/intel/icelake/lpc.c @@ -13,9 +13,7 @@ * GNU General Public License for more details. */ -#include "chip.h" #include <console/console.h> -#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <pc80/isa-dma.h> @@ -33,6 +31,8 @@ #include <soc/pci_devs.h> #include <soc/pcr_ids.h> +#include "chip.h" + /* * As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve * certain memory range as reserved range for BIOS usage. diff --git a/src/soc/intel/quark/gpio_i2c.c b/src/soc/intel/quark/gpio_i2c.c index b2bb572..02b5892 100644 --- a/src/soc/intel/quark/gpio_i2c.c +++ b/src/soc/intel/quark/gpio_i2c.c @@ -14,7 +14,6 @@ */ #include <console/console.h> -#include <delay.h> #include <device/device.h> #include <device/i2c_simple.h> #include <device/pci.h> diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h index d06ed82..27231f9 100644 --- a/src/soc/intel/quark/include/soc/reg_access.h +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -19,7 +19,6 @@ #include <cpu/x86/cr.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> -#include <delay.h> #include <fsp/util.h> #include <reg_script.h> #include <soc/IntelQNCConfig.h> diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index df171f5..1063525 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -19,6 +19,7 @@ #include <assert.h> #include <cpu/x86/mtrr.h> #include <console/console.h> +#include <delay.h> #include <device/pci_ops.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> diff --git a/src/soc/intel/quark/romstage/pcie.c b/src/soc/intel/quark/romstage/pcie.c index dc54a32..747ac2b 100644 --- a/src/soc/intel/quark/romstage/pcie.c +++ b/src/soc/intel/quark/romstage/pcie.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <delay.h> #include <device/device.h> #include <soc/pci_devs.h> #include <soc/reg_access.h> diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 0343a23..3e77b03 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -33,7 +33,6 @@ #include <cpu/x86/cache.h> #include <cpu/x86/name.h> #include <cpu/x86/smm.h> -#include <delay.h> #include <intelblocks/cpulib.h> #include <intelblocks/fast_spi.h> #include <intelblocks/mp_init.h> diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index 0110022..8d6228c 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -15,8 +15,6 @@ * GNU General Public License for more details. */ -#include "chip.h" -#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <pc80/isa-dma.h> @@ -30,6 +28,8 @@ #include <soc/pcr_ids.h> #include <soc/intel/common/block/lpc/lpc_def.h> +#include "chip.h" + /** PCH preserved MMIO range, 24 MB, from 0xFD000000 to 0xFE7FFFFF **/ diff --git a/src/soc/mediatek/common/include/soc/rtc_common.h b/src/soc/mediatek/common/include/soc/rtc_common.h index 24bad00..d92868d 100644 --- a/src/soc/mediatek/common/include/soc/rtc_common.h +++ b/src/soc/mediatek/common/include/soc/rtc_common.h @@ -19,7 +19,6 @@ #include <assert.h> #include <bcd.h> #include <console/console.h> -#include <delay.h> #include <rtc.h> /* diff --git a/src/soc/mediatek/common/rtc.c b/src/soc/mediatek/common/rtc.c index 6e95f5b..b810819 100644 --- a/src/soc/mediatek/common/rtc.c +++ b/src/soc/mediatek/common/rtc.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <delay.h> #include <soc/rtc_common.h> #include <soc/rtc.h> #include <soc/pmic_wrap.h> diff --git a/src/soc/mediatek/common/timer.c b/src/soc/mediatek/common/timer.c index 0762c2b..1857f984 100644 --- a/src/soc/mediatek/common/timer.c +++ b/src/soc/mediatek/common/timer.c @@ -15,9 +15,7 @@ #include <device/mmio.h> #include <timer.h> -#include <delay.h> #include <thread.h> - #include <soc/addressmap.h> #include <soc/timer.h> diff --git a/src/soc/mediatek/common/usb.c b/src/soc/mediatek/common/usb.c index 116e5db..dcb9307 100644 --- a/src/soc/mediatek/common/usb.c +++ b/src/soc/mediatek/common/usb.c @@ -15,7 +15,6 @@ #include <device/mmio.h> #include <console/console.h> -#include <delay.h> #include <soc/addressmap.h> #include <soc/usb.h> #include <timer.h> diff --git a/src/soc/mediatek/mt8173/ddp.c b/src/soc/mediatek/mt8173/ddp.c index 09ea200..0b78c3e 100644 --- a/src/soc/mediatek/mt8173/ddp.c +++ b/src/soc/mediatek/mt8173/ddp.c @@ -14,7 +14,6 @@ */ #include <device/mmio.h> -#include <delay.h> #include <edid.h> #include <stdlib.h> #include <stddef.h> diff --git a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c index 9e4cb11..529ebde 100644 --- a/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8173/dramc_pi_calibration_api.c @@ -15,7 +15,6 @@ #include <device/mmio.h> #include <assert.h> -#include <delay.h> #include <stdlib.h> #include <soc/addressmap.h> #include <soc/dramc_common.h> diff --git a/src/soc/mediatek/mt8173/emi.c b/src/soc/mediatek/mt8173/emi.c index 68b178f..d4cd02a 100644 --- a/src/soc/mediatek/mt8173/emi.c +++ b/src/soc/mediatek/mt8173/emi.c @@ -17,7 +17,6 @@ #include <assert.h> #include <boardid.h> #include <console/console.h> -#include <delay.h> #include <soc/addressmap.h> #include <soc/dramc_common.h> #include <soc/dramc_register.h> diff --git a/src/soc/mediatek/mt8173/rtc.c b/src/soc/mediatek/mt8173/rtc.c index 5b7d486..3b2df8a 100644 --- a/src/soc/mediatek/mt8173/rtc.c +++ b/src/soc/mediatek/mt8173/rtc.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <delay.h> #include <soc/rtc_common.h> #include <soc/rtc.h> #include <soc/mt6391.h> diff --git a/src/soc/nvidia/tegra/gpio.c b/src/soc/nvidia/tegra/gpio.c index 4964967..6800c5d 100644 --- a/src/soc/nvidia/tegra/gpio.c +++ b/src/soc/nvidia/tegra/gpio.c @@ -18,7 +18,6 @@ #include <soc/addressmap.h> #include <stddef.h> #include <stdint.h> -#include <delay.h> #include "pinmux.h" diff --git a/src/soc/nvidia/tegra210/mipi_dsi.c b/src/soc/nvidia/tegra210/mipi_dsi.c index 6b5319a..23d9274 100644 --- a/src/soc/nvidia/tegra210/mipi_dsi.c +++ b/src/soc/nvidia/tegra210/mipi_dsi.c @@ -38,10 +38,10 @@ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE * USE OR OTHER DEALINGS IN THE SOFTWARE. */ + #include <console/console.h> #include <stdint.h> #include <stdlib.h> -#include <delay.h> #include <string.h> #include <soc/addressmap.h> #include <soc/clock.h> diff --git a/src/soc/qualcomm/ipq40xx/i2c.c b/src/soc/qualcomm/ipq40xx/i2c.c index b727f6d..f5c9943 100644 --- a/src/soc/qualcomm/ipq40xx/i2c.c +++ b/src/soc/qualcomm/ipq40xx/i2c.c @@ -31,7 +31,6 @@ #include <assert.h> #include <console/console.h> -#include <delay.h> #include <device/i2c_simple.h> #include <stdlib.h> #include <string.h> diff --git a/src/soc/qualcomm/ipq806x/i2c.c b/src/soc/qualcomm/ipq806x/i2c.c index 4898d9b..cd57591 100644 --- a/src/soc/qualcomm/ipq806x/i2c.c +++ b/src/soc/qualcomm/ipq806x/i2c.c @@ -29,7 +29,6 @@ #include <assert.h> #include <console/console.h> -#include <delay.h> #include <device/i2c_simple.h> #include <stdlib.h> #include <string.h> diff --git a/src/soc/qualcomm/qcs405/timer.c b/src/soc/qualcomm/qcs405/timer.c index 5df2430..6b0d0ed 100644 --- a/src/soc/qualcomm/qcs405/timer.c +++ b/src/soc/qualcomm/qcs405/timer.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <delay.h> #include <arch/lib_helpers.h> #include <commonlib/helpers.h> diff --git a/src/soc/qualcomm/sdm845/clock.c b/src/soc/qualcomm/sdm845/clock.c index 5f0c305..382e5a6 100644 --- a/src/soc/qualcomm/sdm845/clock.c +++ b/src/soc/qualcomm/sdm845/clock.c @@ -16,7 +16,6 @@ #include <device/mmio.h> #include <types.h> #include <console/console.h> -#include <delay.h> #include <commonlib/helpers.h> #include <assert.h> #include <soc/clock.h> diff --git a/src/soc/qualcomm/sdm845/gpio.c b/src/soc/qualcomm/sdm845/gpio.c index afa461d..faa0133 100644 --- a/src/soc/qualcomm/sdm845/gpio.c +++ b/src/soc/qualcomm/sdm845/gpio.c @@ -15,7 +15,6 @@ #include <device/mmio.h> #include <types.h> -#include <delay.h> #include <gpio.h> void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, diff --git a/src/soc/qualcomm/sdm845/timer.c b/src/soc/qualcomm/sdm845/timer.c index 5df2430..6b0d0ed 100644 --- a/src/soc/qualcomm/sdm845/timer.c +++ b/src/soc/qualcomm/sdm845/timer.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include <delay.h> #include <arch/lib_helpers.h> #include <commonlib/helpers.h> diff --git a/src/soc/rockchip/common/pwm.c b/src/soc/rockchip/common/pwm.c index e4045a8..ad0453b 100644 --- a/src/soc/rockchip/common/pwm.c +++ b/src/soc/rockchip/common/pwm.c @@ -15,7 +15,6 @@ #include <device/mmio.h> #include <assert.h> -#include <delay.h> #include <soc/addressmap.h> #include <soc/grf.h> #include <soc/soc.h> diff --git a/src/soc/rockchip/common/vop.c b/src/soc/rockchip/common/vop.c index 1ee861c..9c70b78 100644 --- a/src/soc/rockchip/common/vop.c +++ b/src/soc/rockchip/common/vop.c @@ -14,7 +14,6 @@ */ #include <device/mmio.h> -#include <delay.h> #include <stdlib.h> #include <stddef.h> #include <soc/addressmap.h> diff --git a/src/soc/rockchip/rk3288/soc.c b/src/soc/rockchip/rk3288/soc.c index 19ad0eb..bda9553 100644 --- a/src/soc/rockchip/rk3288/soc.c +++ b/src/soc/rockchip/rk3288/soc.c @@ -16,7 +16,6 @@ #include <arch/cache.h> #include <bootmode.h> #include <console/console.h> -#include <delay.h> #include <device/device.h> #include <gpio.h> #include <soc/display.h> diff --git a/src/soc/rockchip/rk3288/timer.c b/src/soc/rockchip/rk3288/timer.c index ea235b3..f16af91 100644 --- a/src/soc/rockchip/rk3288/timer.c +++ b/src/soc/rockchip/rk3288/timer.c @@ -14,7 +14,6 @@ */ #include <device/mmio.h> -#include <delay.h> #include <soc/timer.h> #include <stdint.h> #include <timer.h> diff --git a/src/soc/rockchip/rk3288/tsadc.c b/src/soc/rockchip/rk3288/tsadc.c index 8104361..a34105d 100644 --- a/src/soc/rockchip/rk3288/tsadc.c +++ b/src/soc/rockchip/rk3288/tsadc.c @@ -15,7 +15,6 @@ #include <device/mmio.h> #include <assert.h> -#include <delay.h> #include <soc/clock.h> #include <soc/grf.h> #include <soc/pmu.h> diff --git a/src/soc/rockchip/rk3399/timer.c b/src/soc/rockchip/rk3399/timer.c index be5f20f..ba032e2 100644 --- a/src/soc/rockchip/rk3399/timer.c +++ b/src/soc/rockchip/rk3399/timer.c @@ -14,7 +14,6 @@ */ #include <device/mmio.h> -#include <delay.h> #include <soc/timer.h> #include <stdint.h> #include <timer.h> diff --git a/src/soc/rockchip/rk3399/usb.c b/src/soc/rockchip/rk3399/usb.c index 78facb5..e016fbf 100644 --- a/src/soc/rockchip/rk3399/usb.c +++ b/src/soc/rockchip/rk3399/usb.c @@ -16,7 +16,6 @@ #include <device/mmio.h> #include <assert.h> #include <console/console.h> -#include <delay.h> #include <soc/clock.h> #include <soc/grf.h> #include <soc/soc.h> diff --git a/src/soc/samsung/exynos5250/clock_init.c b/src/soc/samsung/exynos5250/clock_init.c index d67b596..fa19eb1 100644 --- a/src/soc/samsung/exynos5250/clock_init.c +++ b/src/soc/samsung/exynos5250/clock_init.c @@ -16,7 +16,6 @@ /* Clock setup for SMDK5250 board based on EXYNOS5 */ #include <device/mmio.h> -#include <delay.h> #include <soc/clk.h> #include <soc/dp.h> #include <soc/setup.h> diff --git a/src/soc/samsung/exynos5250/cpu.c b/src/soc/samsung/exynos5250/cpu.c index 81f6f38..f00351e 100644 --- a/src/soc/samsung/exynos5250/cpu.c +++ b/src/soc/samsung/exynos5250/cpu.c @@ -17,7 +17,6 @@ #include <arch/cache.h> #include <console/console.h> #include <device/mmio.h> -#include <delay.h> #include <device/device.h> #include <soc/clk.h> #include <soc/cpu.h> diff --git a/src/soc/samsung/exynos5250/timer.c b/src/soc/samsung/exynos5250/timer.c index 47a6f37..609ca6a 100644 --- a/src/soc/samsung/exynos5250/timer.c +++ b/src/soc/samsung/exynos5250/timer.c @@ -14,7 +14,6 @@ */ #include <device/mmio.h> -#include <delay.h> #include <soc/clk.h> #include <stdint.h> #include <timer.h> diff --git a/src/soc/samsung/exynos5420/clock_init.c b/src/soc/samsung/exynos5420/clock_init.c index 806de6e..eae08a8 100644 --- a/src/soc/samsung/exynos5420/clock_init.c +++ b/src/soc/samsung/exynos5420/clock_init.c @@ -16,7 +16,6 @@ /* Clock setup for SMDK5420 board based on EXYNOS5 */ #include <device/mmio.h> -#include <delay.h> #include <soc/clk.h> #include <soc/cpu.h> #include <soc/dp.h> diff --git a/src/soc/samsung/exynos5420/cpu.c b/src/soc/samsung/exynos5420/cpu.c index 1c354e6..55b0512 100644 --- a/src/soc/samsung/exynos5420/cpu.c +++ b/src/soc/samsung/exynos5420/cpu.c @@ -17,7 +17,6 @@ #include <arch/cache.h> #include <console/console.h> #include <device/mmio.h> -#include <delay.h> #include <device/device.h> #include <ec/google/chromeec/ec.h> #include <soc/dp.h> diff --git a/src/soc/samsung/exynos5420/fimd.c b/src/soc/samsung/exynos5420/fimd.c index 6b69f18..756d2fb 100644 --- a/src/soc/samsung/exynos5420/fimd.c +++ b/src/soc/samsung/exynos5420/fimd.c @@ -18,7 +18,6 @@ #include <device/mmio.h> #include <console/console.h> -#include <delay.h> #include <soc/clk.h> #include <soc/dp.h> #include <soc/fimd.h> diff --git a/src/soc/samsung/exynos5420/timer.c b/src/soc/samsung/exynos5420/timer.c index 47a6f37..609ca6a 100644 --- a/src/soc/samsung/exynos5420/timer.c +++ b/src/soc/samsung/exynos5420/timer.c @@ -14,7 +14,6 @@ */ #include <device/mmio.h> -#include <delay.h> #include <soc/clk.h> #include <stdint.h> #include <timer.h> diff --git a/src/southbridge/amd/agesa/hudson/hda.c b/src/southbridge/amd/agesa/hudson/hda.c index 1cd8953..2368bb2 100644 --- a/src/southbridge/amd/agesa/hudson/hda.c +++ b/src/southbridge/amd/agesa/hudson/hda.c @@ -17,9 +17,8 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include <delay.h> -#include "hudson.h" +#include "hudson.h" static void hda_init(struct device *dev) { diff --git a/src/southbridge/amd/agesa/hudson/imc.c b/src/southbridge/amd/agesa/hudson/imc.c index 68ff7fb..9ba0731 100644 --- a/src/southbridge/amd/agesa/hudson/imc.c +++ b/src/southbridge/amd/agesa/hudson/imc.c @@ -15,7 +15,6 @@ #include "imc.h" #include <device/mmio.h> -#include <delay.h> #include <Porting.h> #include <AGESA.h> #include <amdlib.h> diff --git a/src/southbridge/amd/agesa/hudson/sata.c b/src/southbridge/amd/agesa/hudson/sata.c index 75ec439..f6d3689 100644 --- a/src/southbridge/amd/agesa/hudson/sata.c +++ b/src/southbridge/amd/agesa/hudson/sata.c @@ -14,12 +14,11 @@ */ #include <device/device.h> -#include <delay.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "hudson.h" +#include "hudson.h" static void sata_init(struct device *dev) { diff --git a/src/southbridge/amd/agesa/hudson/sd.c b/src/southbridge/amd/agesa/hudson/sd.c index ec447ef..cc9470e 100644 --- a/src/southbridge/amd/agesa/hudson/sd.c +++ b/src/southbridge/amd/agesa/hudson/sd.c @@ -14,10 +14,10 @@ */ #include <device/device.h> -#include <delay.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> + #include "hudson.h" static void sd_init(struct device *dev) diff --git a/src/southbridge/amd/agesa/hudson/smihandler.c b/src/southbridge/amd/agesa/hudson/smihandler.c index a87b75d..1b9442b 100644 --- a/src/southbridge/amd/agesa/hudson/smihandler.c +++ b/src/southbridge/amd/agesa/hudson/smihandler.c @@ -19,12 +19,11 @@ */ #include <arch/io.h> +#include <cpu/x86/smm.h> + #include "hudson.h" #include "smi.h" -#include <cpu/x86/smm.h> -#include <delay.h> - #define SMI_0x88_ACPI_COMMAND (1 << 11) enum smi_source { diff --git a/src/southbridge/amd/pi/hudson/hda.c b/src/southbridge/amd/pi/hudson/hda.c index d5c92b4..9cdc1b4 100644 --- a/src/southbridge/amd/pi/hudson/hda.c +++ b/src/southbridge/amd/pi/hudson/hda.c @@ -17,7 +17,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include <delay.h> + #include "hudson.h" static const unsigned short pci_device_ids[] = { diff --git a/src/southbridge/amd/pi/hudson/imc.c b/src/southbridge/amd/pi/hudson/imc.c index 461d7b4..9ea8172 100644 --- a/src/southbridge/amd/pi/hudson/imc.c +++ b/src/southbridge/amd/pi/hudson/imc.c @@ -19,7 +19,6 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <device/device.h> -#include <delay.h> #include <Porting.h> #include <AGESA.h> #include <Lib/amdlib.h> diff --git a/src/southbridge/amd/pi/hudson/sata.c b/src/southbridge/amd/pi/hudson/sata.c index 153fe6d..08e967d 100644 --- a/src/southbridge/amd/pi/hudson/sata.c +++ b/src/southbridge/amd/pi/hudson/sata.c @@ -14,12 +14,11 @@ */ #include <device/device.h> -#include <delay.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include "hudson.h" +#include "hudson.h" static void sata_init(struct device *dev) { diff --git a/src/southbridge/amd/pi/hudson/sd.c b/src/southbridge/amd/pi/hudson/sd.c index c419378..e4ace38 100644 --- a/src/southbridge/amd/pi/hudson/sd.c +++ b/src/southbridge/amd/pi/hudson/sd.c @@ -14,10 +14,10 @@ */ #include <device/device.h> -#include <delay.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> + #include "hudson.h" static void sd_init(struct device *dev) diff --git a/src/southbridge/amd/pi/hudson/smihandler.c b/src/southbridge/amd/pi/hudson/smihandler.c index a87b75d..1b9442b 100644 --- a/src/southbridge/amd/pi/hudson/smihandler.c +++ b/src/southbridge/amd/pi/hudson/smihandler.c @@ -19,12 +19,11 @@ */ #include <arch/io.h> +#include <cpu/x86/smm.h> + #include "hudson.h" #include "smi.h" -#include <cpu/x86/smm.h> -#include <delay.h> - #define SMI_0x88_ACPI_COMMAND (1 << 11) enum smi_source { diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 23942fe..8843621 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -18,12 +18,11 @@ #include <arch/cbfs.h> #include <ip_checksum.h> #include <device/pci_def.h> -#include <delay.h> - -#include "pch.h" /* For DMI bar. */ #include <northbridge/intel/sandybridge/sandybridge.h> +#include "pch.h" + #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) static void diff --git a/src/southbridge/intel/fsp_rangeley/soc.c b/src/southbridge/intel/fsp_rangeley/soc.c index ec5cd07..ec66c43 100644 --- a/src/southbridge/intel/fsp_rangeley/soc.c +++ b/src/southbridge/intel/fsp_rangeley/soc.c @@ -17,10 +17,10 @@ */ #include <console/console.h> -#include <delay.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> + #include "soc.h" static int soc_revision_id = -1; diff --git a/src/southbridge/intel/lynxpoint/azalia.c b/src/southbridge/intel/lynxpoint/azalia.c index 5dd46b2..e088f81 100644 --- a/src/southbridge/intel/lynxpoint/azalia.c +++ b/src/southbridge/intel/lynxpoint/azalia.c @@ -21,8 +21,8 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/mmio.h> -#include <delay.h> #include <device/azalia_device.h> + #include "pch.h" #include "hda_verb.h" diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index bfa112a..88c599f 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -15,7 +15,6 @@ * GNU General Public License for more details. */ -#include <delay.h> #include <types.h> #include <arch/io.h> #include <device/pci_ops.h> @@ -29,12 +28,11 @@ #include <southbridge/intel/common/finalize.h> #include <northbridge/intel/haswell/haswell.h> #include <cpu/intel/haswell/haswell.h> + #include "me.h" #include "pch.h" - #include "nvs.h" - static u8 smm_initialized = 0; /* GNVS needs to be updated by an 0xEA PM Trap (B2) after it has been located diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c index 3099a09..09414af 100644 --- a/src/southbridge/nvidia/mcp55/early_setup_car.c +++ b/src/southbridge/nvidia/mcp55/early_setup_car.c @@ -16,6 +16,7 @@ */ #include <arch/io.h> +#include <delay.h> #ifdef UNUSED_CODE int set_ht_link_buffer_counts_chain(u8 ht_c_num, unsigned vendorid, unsigned val); diff --git a/src/southbridge/nvidia/mcp55/sata.c b/src/southbridge/nvidia/mcp55/sata.c index 4c2830e..27f6073 100644 --- a/src/southbridge/nvidia/mcp55/sata.c +++ b/src/southbridge/nvidia/mcp55/sata.c @@ -19,10 +19,10 @@ #include <console/console.h> #include <device/device.h> -#include <delay.h> #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> + #include "mcp55.h" static void sata_init(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/32012 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I23bc0191ca8fcd88364e5c08be7c90195019e399 Gerrit-Change-Number: 32012 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 10

Change in ...coreboot[master]: mb/amd/bettong/mainboard: Drop unused include <agesawrapper.h>
by HAOUAS Elyes (Code Review) 06 Apr '19

06 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32013 Change subject: mb/amd/bettong/mainboard: Drop unused include <agesawrapper.h> ...................................................................... mb/amd/bettong/mainboard: Drop unused include <agesawrapper.h> Change-Id: I020c1b9558f6aec47b048fa575c64c619b8c592a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/amd/bettong/mainboard.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/32013/1 diff --git a/src/mainboard/amd/bettong/mainboard.c b/src/mainboard/amd/bettong/mainboard.c index 80b888e..5b93751 100644 --- a/src/mainboard/amd/bettong/mainboard.c +++ b/src/mainboard/amd/bettong/mainboard.c @@ -15,7 +15,6 @@ #include <console/console.h> #include <device/device.h> -#include <agesawrapper.h> #include <southbridge/amd/common/amd_pci_util.h> /*********************************************************** -- To view, visit https://review.coreboot.org/c/coreboot/+/32013 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I020c1b9558f6aec47b048fa575c64c619b8c592a Gerrit-Change-Number: 32013 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 2

Change in ...coreboot[master]: src: Use #include <timer.h> when appropriate
by HAOUAS Elyes (Code Review) 06 Apr '19

06 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32009 Change subject: src: Use #include <timer.h> when appropriate ...................................................................... src: Use #include <timer.h> when appropriate Change-Id: I5e739233f3742fd68d537f671642bb04886e3009 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/commonlib/storage/sd.c M src/commonlib/storage/sd_mmc.c M src/commonlib/storage/sdhci_adma.c M src/cpu/allwinner/a10/timer.c M src/cpu/x86/mp_init.c M src/drivers/i2c/tpm/tis.c M src/lib/thread.c M src/soc/cavium/cn81xx/include/soc/timer.h M src/soc/intel/apollolake/pmutil.c M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/cannonlake/reset.c M src/soc/intel/common/block/systemagent/systemagent_early.c M src/soc/intel/icelake/pmutil.c M src/soc/intel/icelake/reset.c M src/soc/intel/quark/storage_test.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/skylake/reset.c M src/soc/mediatek/common/include/soc/pmic_wrap_common.h M src/soc/mediatek/common/include/soc/rtc_common.h M src/soc/mediatek/common/pmic_wrap.c M src/soc/mediatek/common/rtc.c M src/soc/mediatek/mt8183/pmic_wrap.c M src/soc/nvidia/tegra210/romstage.c M src/soc/nvidia/tegra210/soc.c M src/soc/nvidia/tegra210/spi.c M src/soc/qualcomm/ipq40xx/blobs_init.c M src/soc/qualcomm/sdm845/clock.c M src/soc/qualcomm/sdm845/gpio.c M src/soc/samsung/exynos5420/dp.c M src/soc/samsung/exynos5420/dp_lowlevel.c M src/soc/samsung/exynos5420/fimd.c 31 files changed, 21 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/32009/1 diff --git a/src/commonlib/storage/sd.c b/src/commonlib/storage/sd.c index 1389ffb..2e1ae85 100644 --- a/src/commonlib/storage/sd.c +++ b/src/commonlib/storage/sd.c @@ -24,9 +24,9 @@ #include <commonlib/storage.h> #include <delay.h> #include <endian.h> + #include "sd_mmc.h" #include "storage.h" -#include <timer.h> int sd_send_if_cond(struct storage_media *media) { diff --git a/src/commonlib/storage/sd_mmc.c b/src/commonlib/storage/sd_mmc.c index bda8d74..fd59bd0 100644 --- a/src/commonlib/storage/sd_mmc.c +++ b/src/commonlib/storage/sd_mmc.c @@ -24,11 +24,11 @@ #include <commonlib/storage.h> #include <delay.h> #include <endian.h> +#include <string.h> + #include "mmc.h" #include "sd_mmc.h" #include "storage.h" -#include <string.h> -#include <timer.h> uint64_t sd_mmc_extract_uint32_bits(const uint32_t *array, int start, int count) { diff --git a/src/commonlib/storage/sdhci_adma.c b/src/commonlib/storage/sdhci_adma.c index e95742b..1bae3fb 100644 --- a/src/commonlib/storage/sdhci_adma.c +++ b/src/commonlib/storage/sdhci_adma.c @@ -22,11 +22,11 @@ #include <commonlib/storage.h> #include <delay.h> #include <endian.h> +#include <string.h> + #include "sdhci.h" #include "sd_mmc.h" #include "storage.h" -#include <string.h> -#include <timer.h> static void sdhci_alloc_adma_descs(struct sdhci_ctrlr *sdhci_ctrlr, u32 need_descriptors) diff --git a/src/cpu/allwinner/a10/timer.c b/src/cpu/allwinner/a10/timer.c index c91d492..87228a0 100644 --- a/src/cpu/allwinner/a10/timer.c +++ b/src/cpu/allwinner/a10/timer.c @@ -17,11 +17,10 @@ * */ -#include "timer.h" - #include <device/mmio.h> #include <delay.h> -#include <timer.h> + +#include "timer.h" struct a1x_timer_module *const timer_module = (void *)A1X_TIMER_BASE; struct a1x_timer *const tmr0 = diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 138f194..9d51b3e 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -36,6 +36,7 @@ #include <smp/atomic.h> #include <smp/spinlock.h> #include <symbols.h> +#include <timer.h> #include <thread.h> #define MAX_APIC_IDS 256 diff --git a/src/drivers/i2c/tpm/tis.c b/src/drivers/i2c/tpm/tis.c index 92c8921..fd56ade 100644 --- a/src/drivers/i2c/tpm/tis.c +++ b/src/drivers/i2c/tpm/tis.c @@ -18,15 +18,14 @@ #include <string.h> #include <assert.h> #include <commonlib/endian.h> +#include <console/console.h> #include <delay.h> #include <device/i2c_simple.h> #include <endian.h> #include <lib.h> #include <security/tpm/tis.h> -#include "tpm.h" -#include <timer.h> -#include <console/console.h> +#include "tpm.h" /* global structure for tpm chip data */ static struct tpm_chip g_chip CAR_GLOBAL; diff --git a/src/lib/thread.c b/src/lib/thread.c index 57a0f8c..281885f 100644 --- a/src/lib/thread.c +++ b/src/lib/thread.c @@ -12,6 +12,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ + #include <stddef.h> #include <stdint.h> #include <stdlib.h> @@ -19,6 +20,7 @@ #include <bootstate.h> #include <console/console.h> #include <thread.h> +#include <timer.h> static void idle_thread_init(void); diff --git a/src/soc/cavium/cn81xx/include/soc/timer.h b/src/soc/cavium/cn81xx/include/soc/timer.h index 4507b0b..5c4cbd2 100644 --- a/src/soc/cavium/cn81xx/include/soc/timer.h +++ b/src/soc/cavium/cn81xx/include/soc/timer.h @@ -18,7 +18,6 @@ #include <inttypes.h> #include <types.h> -#include <timer.h> #include <delay.h> /* Watchdog functions */ diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index e766c77..22f5309 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -35,8 +35,8 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/smbus.h> -#include <timer.h> #include <security/vboot/vbnv.h> + #include "chip.h" static uintptr_t read_pmc_mmio_bar(void) diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index 37d1365..fadd35d 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -38,8 +38,8 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/smbus.h> -#include <timer.h> #include <security/vboot/vbnv.h> + #include "chip.h" /* diff --git a/src/soc/intel/cannonlake/reset.c b/src/soc/intel/cannonlake/reset.c index a6f8092..e92396f 100644 --- a/src/soc/intel/cannonlake/reset.c +++ b/src/soc/intel/cannonlake/reset.c @@ -20,7 +20,6 @@ #include <fsp/util.h> #include <soc/intel/common/reset.h> #include <string.h> -#include <timer.h> #include <soc/pci_devs.h> /* Reset Request */ diff --git a/src/soc/intel/common/block/systemagent/systemagent_early.c b/src/soc/intel/common/block/systemagent/systemagent_early.c index 93fa5df..a3e278f 100644 --- a/src/soc/intel/common/block/systemagent/systemagent_early.c +++ b/src/soc/intel/common/block/systemagent/systemagent_early.c @@ -22,8 +22,8 @@ #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/systemagent.h> + #include "systemagent_def.h" -#include <timer.h> #if !ENV_RAMSTAGE void bootblock_systemagent_early_init(void) diff --git a/src/soc/intel/icelake/pmutil.c b/src/soc/intel/icelake/pmutil.c index fa2411d..96ff52d 100644 --- a/src/soc/intel/icelake/pmutil.c +++ b/src/soc/intel/icelake/pmutil.c @@ -37,8 +37,8 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/smbus.h> -#include <timer.h> #include <security/vboot/vbnv.h> + #include "chip.h" /* diff --git a/src/soc/intel/icelake/reset.c b/src/soc/intel/icelake/reset.c index 854723c..470b5f4 100644 --- a/src/soc/intel/icelake/reset.c +++ b/src/soc/intel/icelake/reset.c @@ -20,7 +20,6 @@ #include <fsp/util.h> #include <soc/intel/common/reset.h> #include <string.h> -#include <timer.h> #include <soc/pci_devs.h> /* Reset Request */ diff --git a/src/soc/intel/quark/storage_test.c b/src/soc/intel/quark/storage_test.c index 79901f2..bdf86b1 100644 --- a/src/soc/intel/quark/storage_test.c +++ b/src/soc/intel/quark/storage_test.c @@ -25,6 +25,7 @@ #include <soc/iomap.h> #include <soc/pci_devs.h> #include <soc/storage_test.h> +#include <timer.h> #include <string.h> #if CONFIG(STORAGE_LOG) diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index b517e6d..7d0dc0a 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -37,8 +37,8 @@ #include <soc/pm.h> #include <soc/pmc.h> #include <soc/smbus.h> -#include <timer.h> #include <security/vboot/vbnv.h> + #include "chip.h" /* diff --git a/src/soc/intel/skylake/reset.c b/src/soc/intel/skylake/reset.c index f73563e..ff1a959 100644 --- a/src/soc/intel/skylake/reset.c +++ b/src/soc/intel/skylake/reset.c @@ -20,7 +20,6 @@ #include <soc/intel/common/reset.h> #include <soc/me.h> #include <soc/pm.h> -#include <timer.h> static void do_force_global_reset(void) { diff --git a/src/soc/mediatek/common/include/soc/pmic_wrap_common.h b/src/soc/mediatek/common/include/soc/pmic_wrap_common.h index bf0b752..0b9f2d3 100644 --- a/src/soc/mediatek/common/include/soc/pmic_wrap_common.h +++ b/src/soc/mediatek/common/include/soc/pmic_wrap_common.h @@ -17,7 +17,6 @@ #define SOC_MEDIATEK_PMIC_WRAP_COMMON_H #include <console/console.h> -#include <timer.h> #define PWRAPTAG "[PWRAP] " #define pwrap_err(fmt, arg ...) printk(BIOS_ERR, PWRAPTAG "ERROR,line=%d" fmt, \ diff --git a/src/soc/mediatek/common/include/soc/rtc_common.h b/src/soc/mediatek/common/include/soc/rtc_common.h index 41e772e..24bad00 100644 --- a/src/soc/mediatek/common/include/soc/rtc_common.h +++ b/src/soc/mediatek/common/include/soc/rtc_common.h @@ -21,7 +21,6 @@ #include <console/console.h> #include <delay.h> #include <rtc.h> -#include <timer.h> /* * Default values for RTC initialization diff --git a/src/soc/mediatek/common/pmic_wrap.c b/src/soc/mediatek/common/pmic_wrap.c index 9e1163b..1b8bc5d 100644 --- a/src/soc/mediatek/common/pmic_wrap.c +++ b/src/soc/mediatek/common/pmic_wrap.c @@ -16,6 +16,7 @@ #include <device/mmio.h> #include <assert.h> #include <soc/pmic_wrap.h> +#include <timer.h> u32 wait_for_state_idle(u32 timeout_us, void *wacs_register, void *wacs_vldclr_register, u32 *read_reg) diff --git a/src/soc/mediatek/common/rtc.c b/src/soc/mediatek/common/rtc.c index fd40cb5..6e95f5b 100644 --- a/src/soc/mediatek/common/rtc.c +++ b/src/soc/mediatek/common/rtc.c @@ -16,6 +16,7 @@ #include <soc/rtc_common.h> #include <soc/rtc.h> #include <soc/pmic_wrap.h> +#include <timer.h> /* ensure rtc write success */ int rtc_busy_wait(void) diff --git a/src/soc/mediatek/mt8183/pmic_wrap.c b/src/soc/mediatek/mt8183/pmic_wrap.c index 2593b7a..65584ab 100644 --- a/src/soc/mediatek/mt8183/pmic_wrap.c +++ b/src/soc/mediatek/mt8183/pmic_wrap.c @@ -17,6 +17,7 @@ #include <soc/infracfg.h> #include <soc/pll.h> #include <soc/pmic_wrap.h> +#include <timer.h> #define PRIORITY_FIELD(x) ((x % 4) * 8) #define PRIORITY_IN(id, priority) (id << PRIORITY_FIELD(priority)) diff --git a/src/soc/nvidia/tegra210/romstage.c b/src/soc/nvidia/tegra210/romstage.c index bfa3c0a..3bd1a5b 100644 --- a/src/soc/nvidia/tegra210/romstage.c +++ b/src/soc/nvidia/tegra210/romstage.c @@ -28,7 +28,6 @@ #include <soc/romstage.h> #include <soc/nvidia/tegra/apbmisc.h> #include <symbols.h> -#include <timer.h> #include <vendorcode/google/chromeos/chromeos.h> void __weak romstage_mainboard_init(void) diff --git a/src/soc/nvidia/tegra210/soc.c b/src/soc/nvidia/tegra210/soc.c index c013099..cedcc18 100644 --- a/src/soc/nvidia/tegra210/soc.c +++ b/src/soc/nvidia/tegra210/soc.c @@ -26,7 +26,6 @@ #include <soc/cpu.h> #include <soc/mc.h> #include <soc/nvidia/tegra/apbmisc.h> -#include <timer.h> #include <soc/sdram.h> #include <soc/sdram_configs.h> diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c index 6542df1..edb052d 100644 --- a/src/soc/nvidia/tegra210/spi.c +++ b/src/soc/nvidia/tegra210/spi.c @@ -29,8 +29,6 @@ #include <stdint.h> #include <stdlib.h> #include <symbols.h> -#include <timer.h> - #if defined(CONFIG_DEBUG_SPI) && CONFIG_DEBUG_SPI # define DEBUG_SPI(x,...) printk(BIOS_DEBUG, "TEGRA_SPI: " x) diff --git a/src/soc/qualcomm/ipq40xx/blobs_init.c b/src/soc/qualcomm/ipq40xx/blobs_init.c index 761b571..5cda9fc 100644 --- a/src/soc/qualcomm/ipq40xx/blobs_init.c +++ b/src/soc/qualcomm/ipq40xx/blobs_init.c @@ -19,9 +19,7 @@ #include <cbfs.h> #include <console/console.h> #include <string.h> -#include <timer.h> #include <program_loading.h> - #include <soc/iomap.h> #include <soc/soc_services.h> diff --git a/src/soc/qualcomm/sdm845/clock.c b/src/soc/qualcomm/sdm845/clock.c index bdbcfb8..5f0c305 100644 --- a/src/soc/qualcomm/sdm845/clock.c +++ b/src/soc/qualcomm/sdm845/clock.c @@ -17,10 +17,8 @@ #include <types.h> #include <console/console.h> #include <delay.h> -#include <timer.h> #include <commonlib/helpers.h> #include <assert.h> - #include <soc/clock.h> #define DIV(div) (2*div - 1) diff --git a/src/soc/qualcomm/sdm845/gpio.c b/src/soc/qualcomm/sdm845/gpio.c index a2a6fb9..afa461d 100644 --- a/src/soc/qualcomm/sdm845/gpio.c +++ b/src/soc/qualcomm/sdm845/gpio.c @@ -16,8 +16,6 @@ #include <device/mmio.h> #include <types.h> #include <delay.h> -#include <timer.h> - #include <gpio.h> void gpio_configure(gpio_t gpio, uint32_t func, uint32_t pull, diff --git a/src/soc/samsung/exynos5420/dp.c b/src/soc/samsung/exynos5420/dp.c index 190842e..5ad3dd3 100644 --- a/src/soc/samsung/exynos5420/dp.c +++ b/src/soc/samsung/exynos5420/dp.c @@ -23,7 +23,6 @@ #include <soc/sysreg.h> #include <stdlib.h> #include <string.h> -#include <timer.h> /* * Here is the rough outline of how we bring up the display: diff --git a/src/soc/samsung/exynos5420/dp_lowlevel.c b/src/soc/samsung/exynos5420/dp_lowlevel.c index 5381657..164704b 100644 --- a/src/soc/samsung/exynos5420/dp_lowlevel.c +++ b/src/soc/samsung/exynos5420/dp_lowlevel.c @@ -23,7 +23,6 @@ #include <soc/power.h> #include <soc/sysreg.h> #include <stdlib.h> -#include <timer.h> /* FIXME: I think the DP controller shouldn't be hardcoded here... */ static struct exynos_dp * const dp_regs = (void *)EXYNOS5_DP1_BASE; diff --git a/src/soc/samsung/exynos5420/fimd.c b/src/soc/samsung/exynos5420/fimd.c index 2987598..6b69f18 100644 --- a/src/soc/samsung/exynos5420/fimd.c +++ b/src/soc/samsung/exynos5420/fimd.c @@ -24,7 +24,6 @@ #include <soc/fimd.h> #include <soc/periph.h> #include <soc/sysreg.h> -#include <timer.h> /* fairly useful debugging stuff. */ #if 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/32009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e739233f3742fd68d537f671642bb04886e3009 Gerrit-Change-Number: 32009 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 7

Change in ...coreboot[master]: Correct lint errors in kasan.c
by Abdullah Zafar (Code Review) 06 Apr '19

06 Apr '19

Abdullah Zafar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32221 Change subject: Correct lint errors in kasan.c ...................................................................... Correct lint errors in kasan.c Signed-off-by: 11abdullah11 <abdullahzafar4876(a)yahoo.com> modified: src/lib/kasan.c Change-Id: I51b1666888e2a355199918871b4234063f27690c --- M src/lib/kasan.c 1 file changed, 13 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/32221/1 diff --git a/src/lib/kasan.c b/src/lib/kasan.c index 28ff1ed..057be97 100644 --- a/src/lib/kasan.c +++ b/src/lib/kasan.c @@ -13,18 +13,18 @@ void __asan_store4_noabort(unsigned long addr); void __asan_load8_noabort(unsigned long addr); void __asan_store8_noabort(unsigned long addr); -void __asan_loadN_noabort(unsigned long addr,size_t); -void __asan_storeN_noabort(unsigned long addr,size_t); +void __asan_loadN_noabort(unsigned long addr, size_t x); +void __asan_storeN_noabort(unsigned long addr, size_t x); -void __asan_handle_no_return(void){ } -void __asan_load1_noabort(unsigned long addr){ } -void __asan_store1_noabort(unsigned long addr){ } -void __asan_load2_noabort(unsigned long addr){ } -void __asan_store2_noabort(unsigned long addr){ } -void __asan_load4_noabort(unsigned long addr){ } -void __asan_store4_noabort(unsigned long addr){ } -void __asan_store8_noabort(unsigned long addr){ } -void __asan_load8_noabort(unsigned long addr){ } -void __asan_loadN_noabort(unsigned long addr,size_t i){ } -void __asan_storeN_noabort(unsigned long addr,size_t i){ } +void __asan_handle_no_return(void) { } +void __asan_load1_noabort(unsigned long addr) { } +void __asan_store1_noabort(unsigned long addr) { } +void __asan_load2_noabort(unsigned long addr) { } +void __asan_store2_noabort(unsigned long addr) { } +void __asan_load4_noabort(unsigned long addr) { } +void __asan_store4_noabort(unsigned long addr) { } +void __asan_store8_noabort(unsigned long addr) { } +void __asan_load8_noabort(unsigned long addr) { } +void __asan_loadN_noabort(unsigned long addr, size_t i) { } +void __asan_storeN_noabort(unsigned long addr, size_t i) { } -- To view, visit https://review.coreboot.org/c/coreboot/+/32221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51b1666888e2a355199918871b4234063f27690c Gerrit-Change-Number: 32221 Gerrit-PatchSet: 1 Gerrit-Owner: Abdullah Zafar <abdullahzafar4876(a)yahoo.com> Gerrit-MessageType: newchange

1 1

Change in ...coreboot[master]: [WIP] Nvidia Optimus support for ThinkPads
by Patrick Rudolph (Code Review) 06 Apr '19

06 Apr '19

Patrick Rudolph has uploaded a new patch set (#12) to the change originally created by Evgeny Zinoviev. ( https://review.coreboot.org/c/coreboot/+/28380 ) Change subject: [WIP] Nvidia Optimus support for ThinkPads ...................................................................... [WIP] Nvidia Optimus support for ThinkPads Based on siro's work #23041. Adds ACPI code for dGPU power management using the dGPU kernel module. With Nvidia Optimus active the idle power consumption drops from 22,8W to 13,8W with maximum screen brightness. Depends on: https://review.coreboot.org/#/c/coreboot/+/28392 https://review.coreboot.org/#/c/coreboot/+/28393 What works (tested on 4.16.13-gentoo kernel): - power management via _PS0 and _DSM + _PS3 ACPI calls - nouveau driver - bumblebee (from the "develop" branch) - bbswitch lspci turns on the dGPU, but that is expected, as otherwise it can't access the device's address space. The Nvidia Optimus driver needs to be enabled by setting CONFIG_NVIDIA_OPTIMUS=y Tested on ThinkPad W530 and Thinkpad T520. Known problems: - nvidia driver doens't work: [ 275.244113] NVRM: failed to copy vbios to system memory. [ 275.244345] NVRM: RmInitAdapter failed! (0x30:0xffff:663) [ 275.244433] NVRM: rm_init_adapter failed for device bearing minor number 0 [ 275.347956] NVRM: failed to copy vbios to system memory. [ 275.348140] NVRM: RmInitAdapter failed! (0x30:0xffff:663) [ 275.348163] NVRM: rm_init_adapter failed for device bearing minor number 0 - Random CPU core lockups TODO: - Disable PEG clock to decrease idle power by 1W. - Do longterm stability tests. - Document _DSM and code. Change-Id: I277808d6c1d8bd6e0a267a53f25471597698f8d5 Signed-off-by: Evgeny Zinoviev <me(a)ch1p.com> Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- A src/drivers/nvidia/optimus/Kconfig A src/drivers/nvidia/optimus/acpi/optimus.asl A src/ec/lenovo/pmh7/acpi/optimus_sandy_ivy.asl A src/ec/lenovo/pmh7/acpi/pmh7.asl M src/ec/lenovo/pmh7/pmh7.h M src/mainboard/lenovo/t420/Kconfig M src/mainboard/lenovo/t420/acpi/ec.asl M src/mainboard/lenovo/t420s/Kconfig M src/mainboard/lenovo/t420s/acpi/ec.asl M src/mainboard/lenovo/t430/Kconfig M src/mainboard/lenovo/t430/acpi/ec.asl M src/mainboard/lenovo/t430s/Kconfig M src/mainboard/lenovo/t430s/acpi/ec.asl M src/mainboard/lenovo/t520/Kconfig M src/mainboard/lenovo/t520/acpi/ec.asl M src/mainboard/lenovo/t520/cmos.default M src/mainboard/lenovo/t530/Kconfig M src/mainboard/lenovo/t530/acpi/ec.asl M src/northbridge/intel/sandybridge/acpi/hostbridge.asl M src/northbridge/intel/sandybridge/acpi/peg.asl 20 files changed, 679 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/28380/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/28380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I277808d6c1d8bd6e0a267a53f25471597698f8d5 Gerrit-Change-Number: 28380 Gerrit-PatchSet: 12 Gerrit-Owner: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Name of user not set #1002090 Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: Doc/mb/asrock/h110m: Fix the links
by Maxim Polyakov (Code Review) 06 Apr '19

06 Apr '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32052 Change subject: Doc/mb/asrock/h110m: Fix the links ...................................................................... Doc/mb/asrock/h110m: Fix the links Change-Id: I7b925518416a4268037efac9060ef911e4ae74cd Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M Documentation/mainboard/asrock/h110m-dvs.md 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/32052/1 diff --git a/Documentation/mainboard/asrock/h110m-dvs.md b/Documentation/mainboard/asrock/h110m-dvs.md index 5a3bb3e..8ceb7c8 100644 --- a/Documentation/mainboard/asrock/h110m-dvs.md +++ b/Documentation/mainboard/asrock/h110m-dvs.md @@ -5,9 +5,9 @@ ## Required proprietary blobs Mainboard is based on Intel Skylake/Kaby Lake processor and H110 Chipset. -Intel company provides [Firmware Support Package (2.0)](../../Documentation/soc/intel/fsp/index.md) +Intel company provides [Firmware Support Package (2.0)](../../../Documentation/soc/intel/fsp/index.md) (intel FSP 2.0) to initialize this generation silicon. Please see this -[document](../../Documentation/soc/intel/code_development_model/code_development_model.md). +[document](../../../Documentation/soc/intel/code_development_model/code_development_model.md). FSP Information: @@ -62,7 +62,7 @@ the BIOS region of the flash is writable. If you wish to change any other region, such as the Management Engine or firmware descriptor, then an external programmer is required (unless you find a clever way around -the flash protection). More information about this [here](../../Documentation/flash_tutorial/index.md). +the flash protection). More information about this [here](../../../Documentation/flash_tutorial/index.md). ### External programming -- To view, visit https://review.coreboot.org/c/coreboot/+/32052 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7b925518416a4268037efac9060ef911e4ae74cd Gerrit-Change-Number: 32052 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mainboard/lenovo/t410: Add new port
by Patrick Rudolph (Code Review) 06 Apr '19

06 Apr '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/11791 ) Change subject: mainboard/lenovo/t410: Add new port ...................................................................... Patch Set 12: The nehalem code base should be cleaned first, as the mainboard ports contain lot's of unreadable, unnecessary and duplicated code. -- To view, visit https://review.coreboot.org/c/coreboot/+/11791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Gerrit-Change-Number: 11791 Gerrit-PatchSet: 12 Gerrit-Owner: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eloy Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Okashi Odayakana <brianblevins316(a)gmail.com> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Comment-Date: Sat, 06 Apr 2019 13:47:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit April 2019