coreboot-gerrit April 2019

coreboot-gerrit@coreboot.org

1 participants
1219 discussions

Change in ...coreboot[master]: src/soc/intel/braswell: Remove disabled LPE ACPI code
by Frans Hendriks (Code Review) 08 Apr '19

08 Apr '19

Hello Patrick Rudolph, Piotr Król, build bot (Jenkins), Hannah Williams, Michał Żygowski, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29414 to look at the new patch set (#6). Change subject: src/soc/intel/braswell: Remove disabled LPE ACPI code ...................................................................... src/soc/intel/braswell: Remove disabled LPE ACPI code The ACPI code for LPE device was included regardless of the availability of the LPE controller. Move the LPE ACPI code to seperate SSDT and hide it when LPE is disabled. BUG=N/A TEST=Intel CherryHill CRB Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/mainboard/google/cyan/Makefile.inc M src/mainboard/google/cyan/acpi/codec_maxim.asl M src/mainboard/google/cyan/acpi/codec_realtek.asl A src/mainboard/google/cyan/acpi/jack_board.asl A src/mainboard/google/cyan/acpi/jack_detect.asl A src/mainboard/google/cyan/ssdtlpe.asl A src/mainboard/google/cyan/variants/banon/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/celes/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/cyan/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/edgar/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/kefka/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/reks/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/relm/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/setzer/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/terra/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/ultima/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/wizpig/include/variant/acpi/lpe.asl M src/mainboard/intel/strago/Makefile.inc M src/mainboard/intel/strago/acpi/mainboard.asl A src/mainboard/intel/strago/ssdtlpe.asl M src/soc/intel/braswell/acpi/southcluster.asl M src/soc/intel/braswell/include/soc/acpi.h M src/soc/intel/braswell/lpe.c 23 files changed, 392 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/29414/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/29414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73 Gerrit-Change-Number: 29414 Gerrit-PatchSet: 6 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: src/soc/intel/braswell: Remove disabled LPE acpi code
by Paul Menzel (Code Review) 08 Apr '19

08 Apr '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29414 ) Change subject: src/soc/intel/braswell: Remove disabled LPE acpi code ...................................................................... Patch Set 5: (5 comments) https://review.coreboot.org/#/c/29414/5//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29414/5//COMMIT_MSG@7 PS5, Line 7: acpi ACPI https://review.coreboot.org/#/c/29414/5//COMMIT_MSG@7 PS5, Line 7: src/ Please remove. https://review.coreboot.org/#/c/29414/5//COMMIT_MSG@9 PS5, Line 9: The ACPI code for LPE device was included regardless : of the availability of the LPE controller. : Move the LPE ACPI code to seperate SSDT and hide it when : LPE is disabled. Please use the full text width, and add a blank line between paragraphs. https://review.coreboot.org/#/c/29414/5/src/mainboard/google/cyan/acpi/code… File src/mainboard/google/cyan/acpi/codec_maxim.asl: https://review.coreboot.org/#/c/29414/5/src/mainboard/google/cyan/acpi/code… PS5, Line 39: Method(_CRS, 0x0, Serialized) Please make this a separate commit. https://review.coreboot.org/#/c/29414/5/src/soc/intel/braswell/include/soc/… File src/soc/intel/braswell/include/soc/acpi.h: https://review.coreboot.org/#/c/29414/5/src/soc/intel/braswell/include/soc/… PS5, Line 29: unsigned long current, Doesn’t this fit on the line above? -- To view, visit https://review.coreboot.org/c/coreboot/+/29414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73 Gerrit-Change-Number: 29414 Gerrit-PatchSet: 5 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 08 Apr 2019 12:34:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: src/soc/intel/cannonlake: Remove ITSS IPC restore
by Aamir Bohra (Code Review) 08 Apr '19

08 Apr '19

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32174 Change subject: src/soc/intel/cannonlake: Remove ITSS IPC restore ...................................................................... src/soc/intel/cannonlake: Remove ITSS IPC restore Remove ITSS IPC restore for cannonlake, as it does not take effect since the ITSS PCR regsisters are locked post FSP-S. Change-Id: Ie39e0d43644cb7b03b6c3432f0965f1d76d1bc37 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/cannonlake/chip.c 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/32174/1 diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c index d50c689..845e9ef 100644 --- a/src/soc/intel/cannonlake/chip.c +++ b/src/soc/intel/cannonlake/chip.c @@ -24,7 +24,6 @@ #include <intelblocks/xdci.h> #include <romstage_handoff.h> #include <soc/intel/common/vbt.h> -#include <soc/itss.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> @@ -168,19 +167,12 @@ void soc_init_pre_device(void *chip_info) { - /* Snapshot the current GPIO IRQ polarities. FSP is setting a - * default policy that doesn't honor boards' requirements. */ - itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); - /* Perform silicon specific init. */ fsp_silicon_init(romstage_handoff_is_resume()); /* Display FIRMWARE_VERSION_INFO_HOB */ fsp_display_fvi_version_hob(); - /* Restore GPIO IRQ polarities back to previous settings. */ - itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); - /* TODO(furquan): Get rid of this workaround once FSP is fixed. */ cnl_configure_pads(NULL, 0); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32174 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie39e0d43644cb7b03b6c3432f0965f1d76d1bc37 Gerrit-Change-Number: 32174 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

4 6

Change in ...coreboot[master]: TEMP: NOT FOR REVIEW: qcs405: Add bl31 stage and elf
by build bot (Jenkins) (Code Review) 08 Apr '19

08 Apr '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29981 ) Change subject: TEMP: NOT FOR REVIEW: qcs405: Add bl31 stage and elf ...................................................................... Patch Set 20: (1 comment) https://review.coreboot.org/#/c/29981/20/src/soc/qualcomm/qcs405/soc.c File src/soc/qualcomm/qcs405/soc.c: https://review.coreboot.org/#/c/29981/20/src/soc/qualcomm/qcs405/soc.c@26 PS20, Line 26: bootmem_add_range((uintptr_t)_dram_reserved, _dram_reserved_size, BM_MEM_BL31); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/29981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I967c0b78a3561574609bf8332a22838c85e43429 Gerrit-Change-Number: 29981 Gerrit-PatchSet: 20 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 08 Apr 2019 06:30:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: TEMP: NOT FOR REVIEW: Mistral: QCS405: Added RPM support
by Name of user not set (Code Review) 08 Apr '19

08 Apr '19

Hello Julius Werner, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29970 to look at the new patch set (#21). Change subject: TEMP: NOT FOR REVIEW: Mistral: QCS405: Added RPM support ...................................................................... TEMP: NOT FOR REVIEW: Mistral: QCS405: Added RPM support This patch adds support to read RPM image from 3rdparty/blobs and load it. It takes RPM out of reset. Note that, clock_reset_rpm function to touch the GCC registers actually should reside in clock.c, but for now keeping it here till clock patches are posted. Change-Id: I17f491f0a4bd0dce7522b7e80e1bac97ec18b945 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/Makefile.inc M src/soc/qualcomm/qcs405/include/soc/memlayout.ld A src/soc/qualcomm/qcs405/include/soc/rpm.h M src/soc/qualcomm/qcs405/include/soc/symbols.h M src/soc/qualcomm/qcs405/mmu.c A src/soc/qualcomm/qcs405/rpm_load_reset.c M src/soc/qualcomm/qcs405/soc.c 7 files changed, 105 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/29970/21 -- To view, visit https://review.coreboot.org/c/coreboot/+/29970 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17f491f0a4bd0dce7522b7e80e1bac97ec18b945 Gerrit-Change-Number: 29970 Gerrit-PatchSet: 21 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: qcs405: Add UART support
by Name of user not set (Code Review) 08 Apr '19

08 Apr '19

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29964 to look at the new patch set (#19). Change subject: qcs405: Add UART support ...................................................................... qcs405: Add UART support Add support for UART driver in coreboot. Change-Id: Id9626c68eadead8b8ec5ffbc08cab7b0ec36478f Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Prudhvi Yarlagadda<pyarlaga(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org>TEST=build & run --- M src/soc/qualcomm/qcs405/Kconfig M src/soc/qualcomm/qcs405/Makefile.inc A src/soc/qualcomm/qcs405/include/soc/blsp.h A src/soc/qualcomm/qcs405/include/soc/cdp.h A src/soc/qualcomm/qcs405/include/soc/iomap.h A src/soc/qualcomm/qcs405/include/soc/uart.h A src/soc/qualcomm/qcs405/uart.c 7 files changed, 941 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/29964/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/29964 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9626c68eadead8b8ec5ffbc08cab7b0ec36478f Gerrit-Change-Number: 29964 Gerrit-PatchSet: 19 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: libpayload: Add UART for qcs405
by Name of user not set (Code Review) 08 Apr '19

08 Apr '19

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29957 to look at the new patch set (#20). Change subject: libpayload: Add UART for qcs405 ...................................................................... libpayload: Add UART for qcs405 TEST=build Change-Id: I43164cf9eacc844af1d048f7b6ebbda96fc9d202 Signed-off-by: Prudhvi Yarlagadda <pyarlaga(a)codeaurora.org> Signed-off-by: Sricharan R <sricharan(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M payloads/libpayload/Kconfig M payloads/libpayload/configs/config.mistral M payloads/libpayload/drivers/Makefile.inc A payloads/libpayload/drivers/serial/qcs405.c 4 files changed, 570 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/29957/20 -- To view, visit https://review.coreboot.org/c/coreboot/+/29957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43164cf9eacc844af1d048f7b6ebbda96fc9d202 Gerrit-Change-Number: 29957 Gerrit-PatchSet: 20 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: tint: introduce the new tint build system with checksum verification
by build bot (Jenkins) (Code Review) 07 Apr '19

07 Apr '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23856 ) Change subject: tint: introduce the new tint build system with checksum verification ...................................................................... Patch Set 12: (15 comments) https://review.coreboot.org/#/c/23856/12/payloads/external/tint/generate_co… File payloads/external/tint/generate_core.sh: https://review.coreboot.org/#/c/23856/12/payloads/external/tint/generate_co… PS12, Line 38: sed -n "/^${start}/,/^${end}/{/^${start}/{p;n};{p}}" $source >> $destination line over 80 characters https://review.coreboot.org/#/c/23856/12/payloads/external/tint/generate_co… PS12, Line 40: sed -n "/^${start}/,/^${end}/{/^${start}/{p;n};/^${end}/{q};{p}}" $source >> $destination line over 80 characters https://review.coreboot.org/#/c/23856/12/payloads/external/tint/generate_co… PS12, Line 54: FUNCTIONS="please_install searchtool download compute_hash error_hash_mismatch verify_hash unpack_and_patch" line over 80 characters https://review.coreboot.org/#/c/23856/12/payloads/external/tint/generate_co… PS12, Line 64: import_from_file $buildgcc $corescript "# Find all the required tools" "# Allow" last_line_disabled || exit "$?" line over 80 characters https://review.coreboot.org/#/c/23856/12/payloads/external/tint/generate_co… PS12, Line 70: import_from_file $buildgcc $corescript "if \[ \"\$HALT_FOR_TOOLS" "fi" || exit "$?" line over 80 characters https://review.coreboot.org/#/c/23856/12/payloads/external/tint/generate_co… PS12, Line 86: sed -i -e "s/\tknown_hash=\"\$(get_known_hash.*/\tknown_hash=\"\$2\"/g" $corescript line over 80 characters https://review.coreboot.org/#/c/23856/12/payloads/external/tint/generate_co… PS12, Line 95: # Insert prepare_${package} function call between the unpack and patch operations line over 80 characters https://review.coreboot.org/#/c/23856/12/payloads/external/tint/generate_co… PS12, Line 99: sed -i -e "/\$TAR \$FLAGS \"\$(basename \"\$archive\")\"/a prepare_\${package} || exit \"\$?\"" $corescript line over 80 characters https://review.coreboot.org/#/c/23856/12/payloads/external/tint/tintify_cor… File payloads/external/tint/tintify_core.sh: https://review.coreboot.org/#/c/23856/12/payloads/external/tint/tintify_cor… PS12, Line 12: # <TINT_ARCHIVE_LINK> <TINT_ARCHIVE> <TINT_DIR> <TINT_CHECKSUM> line over 80 characters https://review.coreboot.org/#/c/23856/12/payloads/external/tint/tintify_cor… PS12, Line 54: echo "if [ ! -z ./\${TINT_DIR} ] && [ -e ./\${TINT_DIR}/debian ]; then" >> $tintified line over 80 characters https://review.coreboot.org/#/c/23856/12/payloads/external/tint/tintify_cor… PS12, Line 55: echo "rm -rf ./\${TINT_DIR}/debian ./\${TINT_DIR}/typedefs.h ./\${TINT_DIR}/Makefile;" >> $tintified line over 80 characters https://review.coreboot.org/#/c/23856/12/payloads/external/tint/tintify_cor… PS12, Line 70: sed -i -e "/download() {/a package=\$1\narchive_link=\"\$(eval echo \\\\\$\$package\"_ARCHIVE_LINK\")\"" $tintified line over 80 characters https://review.coreboot.org/#/c/23856/12/payloads/external/tint/tintify_cor… PS12, Line 72: sed -i -e "s/$download_showing_percentage \"\$archive$./\1_link\"\nreplace_plus_with_minus/g" $tintified line over 80 characters https://review.coreboot.org/#/c/23856/12/payloads/external/tint/tintify_cor… PS12, Line 83: echo "printf \"Downloaded TINT tarball ... \${green}ok\${NC}\\n\"" >> ${tintified} line over 80 characters https://review.coreboot.org/#/c/23856/12/payloads/external/tint/tintify_cor… PS12, Line 87: echo "printf \"Unpacked and patched TINT... \${green}ok\${NC}\\n\"" >> ${tintified} line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/23856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d24f222d1b92030b81bba3951e243a2a9f37290 Gerrit-Change-Number: 23856 Gerrit-PatchSet: 12 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Comment-Date: Sun, 07 Apr 2019 16:40:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: lenovo/x230: introduce FHD variant
by Sergey Alirzaev (Code Review) 07 Apr '19

07 Apr '19

Sergey Alirzaev has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28950 ) Change subject: lenovo/x230: introduce FHD variant ...................................................................... Patch Set 7: > Patch Set 7: > > > Patch Set 7: > > > > > At the moment the fhd mod board requires 3.3V from a separate cable, which causes elevated power consumption especially when the lid is closed or the machine is sleeping. > > > This is because the tapped source is always on. > > > Though if it was possible to provide power through the VCC3P power rail instead, the board could be supplied with power only when the display is supposed to be on. This would eliminate the extra cable and only requires that J1 jumper is closed on the board. I tried it myself and also measured a the corresponding pad but there seems to be no voltage present from the lvds connector with the current state of this patch. > > > > > > Maybe someone more knowledgeable has an idea on how to implement this? > > > > Did you also measure the voltage when Linux has booted? > > I would assume that it works in Linux. If that is the > > case, all that is left (as mentioned before) is to make > > libgfxinit aware of the panel at the DP connector (needs > > some restructuring, though). > > I have some hopefully relevant code: > --- a/src/northbridge/intel/sandybridge/gma.c > +++ b/src/northbridge/intel/sandybridge/gma.c > @@ -557,6 +557,10 @@ static void gma_pm_init_post_vbios(struct device *dev) > gtt_write(0xc4030, reg32); > } > > + /* Turn the panel power on using eDP VDD Override */ > + gtt_write(PCH_PP_CONTROL, gtt_read(PCH_PP_CONTROL) | PCH_PP_UNLOCK | EDP_FORCE_VDD); > + udelay(125000); /* And wait until it powers up */ > + > /* Setup Panel Power On Delays */ > reg32 = gtt_read(0xc7208); > if (!reg32) { Linux won't switch off the display when the lid is closed tho. -- To view, visit https://review.coreboot.org/c/coreboot/+/28950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0 Gerrit-Change-Number: 28950 Gerrit-PatchSet: 7 Gerrit-Owner: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Slindee Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Holger Levsen <holger(a)layer-acht.org> Gerrit-CC: Kilian Neuner <cb(a)9-r.net> Gerrit-CC: Matthias Wiedhalm Gerrit-CC: Sergey Alirzaev <zl29ah(a)gmail.com> Gerrit-CC: Tom Hiller <thrilleratplay(a)gmail.com> Gerrit-Comment-Date: Sun, 07 Apr 2019 14:18:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: src: Remove unused variables
by HAOUAS Elyes (Code Review) 07 Apr '19

07 Apr '19

Hello Kyösti Mälkki, Patrick Rudolph, Angel Pons, Julius Werner, build bot (Jenkins), Patrick Georgi, Huang Jin, York Yang, Philipp Deppenwiese, Damien Zammit, David Guckian, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29917 to look at the new patch set (#36). Change subject: src: Remove unused variables ...................................................................... src: Remove unused variables If we enable Wunused in the compiler, we'll have some 'unused variables'. This patch corrects some of them. Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/dram/ddr3.c M src/drivers/spi/sst.c M src/lib/selfboot.c M src/northbridge/amd/amdmct/mct/mct_d.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/pineview/raminit.c M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/via/vx900/raminit_ddr3.c M src/soc/cavium/common/bootblock.c M src/soc/intel/fsp_broadwell_de/acpi.c M src/southbridge/amd/common/amd_pci_util.c M src/southbridge/intel/i82371eb/fadt.c 13 files changed, 17 insertions(+), 57 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/29917/36 -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 36 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2019