coreboot-gerrit April 2019

coreboot-gerrit@coreboot.org

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1219 discussions

Change in ...coreboot[master]: qcs405:Add SPI_RAM_SIMULATION support for QCS405
by Name of user not set (Code Review) 09 Apr '19

09 Apr '19

nsekar(a)codeaurora.org has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29959 ) Change subject: qcs405:Add SPI_RAM_SIMULATION support for QCS405 ...................................................................... Abandoned This was initially used during the development phase to simulate SPI flash. Not needed now. So abandoning it. -- To view, visit https://review.coreboot.org/c/coreboot/+/29959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I895315a995cbbd5e6a7a305e48476f0d0f583cfe Gerrit-Change-Number: 29959 Gerrit-PatchSet: 12 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: abandon

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Change in ...coreboot[master]: Qcs405: Add SPI chip select assert/de-assert in claim/release bus
by Name of user not set (Code Review) 09 Apr '19

09 Apr '19

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31142 Change subject: Qcs405: Add SPI chip select assert/de-assert in claim/release bus ...................................................................... Qcs405: Add SPI chip select assert/de-assert in claim/release bus Add SPI chip select assert/de-assert in claim/release bus. Configure IO in SPI write function and the keep QUP into run state. Add timeout condition in both SPI write and read functions. Change-Id: Iaeb9046f6c4f89c0c1bfa72374b5134eafd1a9dd Signed-off-by: Prudhvi Yarlagadda <pyarlaga(a)codeaurora.org> Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/include/soc/qup.h M src/soc/qualcomm/qcs405/spi.c 3 files changed, 97 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/31142/1 diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index 41f74be..bccefa7 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -63,6 +63,16 @@ }; struct clock_config spi_cfg[] = { + { + .hz = 1000000, + .hw_ctl = 0x0, + .src = SRC_XO_19_2MHZ, + .div = DIV(48), + //.m = 1, + //.n = 2, + //.d_2 = 4, + }, + { .hz = 19200000, .hw_ctl = 0x0, @@ -210,7 +220,7 @@ REG(GCC_APCS_CLOCK_BRANCH_ENA_VOTE), BLSP1_AHB_CLK_ENA); - clock_configure(blsp1_qup4_spi_clk, spi_cfg, 50000000, + clock_configure(blsp1_qup4_spi_clk, spi_cfg, 1000000, ARRAY_SIZE(spi_cfg)); clock_enable(REG(GCC_BLSP1_QUP4_SPI_APPS_CBCR)); clock_enable_vote(REG(GCC_BLSP1_AHB_CBCR), diff --git a/src/soc/qualcomm/qcs405/include/soc/qup.h b/src/soc/qualcomm/qcs405/include/soc/qup.h index 211b44e..5c1c429 100644 --- a/src/soc/qualcomm/qcs405/include/soc/qup.h +++ b/src/soc/qualcomm/qcs405/include/soc/qup.h @@ -71,6 +71,8 @@ #define OUTPUT_FIFO_FULL (1<<6) #define INPUT_FIFO_NOT_EMPTY (1<<5) #define OUTPUT_FIFO_NOT_EMPTY (1<<4) +#define MAX_OUTPUT_DONE_FLAG (1<<10) +#define MAX_INPUT_DONE_FLAG (1<<11) #define INPUT_SERVICE_FLAG (1<<9) #define OUTPUT_SERVICE_FLAG (1<<8) #define QUP_UNPACK_EN (1<<14) diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c index bd88462..1038881 100644 --- a/src/soc/qualcomm/qcs405/spi.c +++ b/src/soc/qualcomm/qcs405/spi.c @@ -36,6 +36,7 @@ #include <stdlib.h> #include <string.h> #include <spi_flash.h> +#include <timer.h> static const struct blsp_spi spi_reg[] = { /* BLSP0 registers for SPI interface */ @@ -320,47 +321,6 @@ return SUCCESS; } -static int spi_ctrlr_claim_bus(const struct spi_slave *slave) -{ - struct ipq_spi_slave *ds = to_ipq_spi(slave); - unsigned int ret; - - ret = spi_hw_init(ds); - if (ret) - return -EIO; - switch(slave->bus) { - case 5: - - gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - - break; - case 4: - gpio_configure(GPIO(37), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(38), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(117), 2, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(118), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - break; - default: - printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); - break; - } - - - return SUCCESS; -} - -static void spi_ctrlr_release_bus(const struct spi_slave *slave) -{ - struct ipq_spi_slave *ds = to_ipq_spi(slave); - - /* Reset the SPI hardware */ - spi_reset(ds); - ds->initialized = 0; -} - static void write_force_cs(const struct spi_slave *slave, int assert) { struct ipq_spi_slave *ds = to_ipq_spi(slave); @@ -380,6 +340,56 @@ return; } + +static int spi_ctrlr_claim_bus(const struct spi_slave *slave) +{ + struct ipq_spi_slave *ds = to_ipq_spi(slave); + unsigned int ret; + + ret = spi_hw_init(ds); + if (ret) + return -EIO; + switch(slave->bus) { + case 4: + gpio_configure(GPIO(37), 2, + GPIO_PULL_DOWN, GPIO_6MA, GPIO_INPUT); //MISO - IN + gpio_configure(GPIO(38), 2, + GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT); //MOSI - Out + gpio_configure(GPIO(117), 2, + GPIO_NO_PULL, GPIO_6MA, GPIO_OUTPUT); //SCLK - out + gpio_configure(GPIO(118), 2, + GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT); //CS_0 - out + + break; + case 5: + + gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); + gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); + gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); + gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); + + break; + default: + printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); + break; + } + + write_force_cs(slave, 1); + + + return SUCCESS; +} + +static void spi_ctrlr_release_bus(const struct spi_slave *slave) +{ + struct ipq_spi_slave *ds = to_ipq_spi(slave); + + /* Reset the SPI hardware */ + write_force_cs(slave, 0); + spi_reset(ds); + ds->initialized = 0; +} + /* * Function to write data to OUTPUT FIFO */ @@ -465,6 +475,7 @@ unsigned int fifo_count; int ret = SUCCESS; int state_config; + struct stopwatch sw; /* Configure no of bytes to read */ state_config = config_spi_state(ds, QUP_STATE_RESET); @@ -505,6 +516,18 @@ } } + stopwatch_init_msecs_expire(&sw, 10); + + do { + val = read32(ds->regs->qup_operational); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "SPI FIFO read timeout \n"); + ret = -ETIMEDOUT; + goto out; + } + + }while(!(val & MAX_INPUT_DONE_FLAG)); + out: /* * Put the SPI Core back in the Reset State @@ -542,15 +565,18 @@ uint32_t val; unsigned int i; unsigned int write_len = bytes; - unsigned int read_len = 3; //bytes; hack for now + unsigned int read_len = bytes; //hack for now unsigned int fifo_count; int ret = SUCCESS; int state_config; + struct stopwatch sw; state_config = config_spi_state(ds, QUP_STATE_RESET); if (state_config) return state_config; + /* Configure input and output enable */ + enable_io_config(ds, write_len, read_len); /* No of bytes to be written in Output FIFO */ write32(ds->regs->qup_mx_output_count, bytes); write32(ds->regs->qup_mx_input_count, bytes); @@ -558,9 +584,6 @@ if (state_config) return state_config; - /* Configure input and output enable */ - enable_io_config(ds, write_len, read_len); - /* * read_len considered to ensure that we read the dummy data for the * write we performed. This is needed to ensure with WR-RD transaction @@ -620,6 +643,18 @@ } } + stopwatch_init_msecs_expire(&sw, 10); + + do { + val = read32(ds->regs->qup_operational); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "SPI FIFO write timeout \n"); + ret = -ETIMEDOUT; + goto out; + } + + }while(!(val & MAX_OUTPUT_DONE_FLAG)); + out: /* * Put the SPI Core back in the Reset State @@ -639,8 +674,10 @@ length = (bytes < MAX_COUNT_SIZE) ? bytes : MAX_COUNT_SIZE; ret = __blsp_spi_write(ds, cmd_buffer, length); - if (ret != SUCCESS) + if (ret != SUCCESS) { + printk(BIOS_ERR, "SPI:DBG write not success \n"); return ret; + } cmd_buffer += length; bytes -= length; @@ -670,8 +707,6 @@ if (ret != SUCCESS) return ret; - write_force_cs(slave, 1); - if (dout != NULL) { ret = blsp_spi_write(ds, txp, (unsigned int) out_bytes); if (ret != SUCCESS) @@ -685,7 +720,6 @@ } out: - write_force_cs(slave, 0); /* * Put the SPI Core back in the Reset State @@ -750,7 +784,7 @@ .setup = spi_ctrlr_setup, .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, - //.xfer = spi_ctrlr_xfer, + .xfer = spi_ctrlr_xfer, .xfer_vector = xfer_vectors, .max_xfer_size = MAX_PACKET_COUNT, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/31142 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaeb9046f6c4f89c0c1bfa72374b5134eafd1a9dd Gerrit-Change-Number: 31142 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mitral: qcs405: Increased the size of RO_VPD
by Name of user not set (Code Review) 09 Apr '19

09 Apr '19

nsekar(a)codeaurora.org has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30707 ) Change subject: mitral: qcs405: Increased the size of RO_VPD ...................................................................... Abandoned Resolved by CB:29949 -- To view, visit https://review.coreboot.org/c/coreboot/+/30707 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c07db907745f97bd5433d522d2d1ee8c9edd8d7 Gerrit-Change-Number: 30707 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: mistral: qcs405: Updated the layout info as in Gale
by Name of user not set (Code Review) 09 Apr '19

09 Apr '19

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30902 Change subject: mistral: qcs405: Updated the layout info as in Gale ...................................................................... mistral: qcs405: Updated the layout info as in Gale Changed the Mistral's layout as in Gale. Change-Id: I61a82bd8dc6a2f86b72beb8efedaee35897fd66f Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/mainboard/google/mistral/chromeos.fmd 1 file changed, 24 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/30902/1 diff --git a/src/mainboard/google/mistral/chromeos.fmd b/src/mainboard/google/mistral/chromeos.fmd index e8b9978..a9bdd7b 100644 --- a/src/mainboard/google/mistral/chromeos.fmd +++ b/src/mainboard/google/mistral/chromeos.fmd @@ -1,52 +1,33 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2018, The Linux Foundation. All rights reserved. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License version 2 and -## only version 2 as published by the Free Software Foundation. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - FLASH@0x0 0x800000 { - WP_RO@0x0 0x300000 { - RO_SECTION@0x0 0x2FE000 { - BOOTBLOCK@0 248K - COREBOOT(CBFS)@0x3E000 0x1E0000 - FMAP@0x21E000 0x1000 - GBB@0x21F000 0xDEF00 - RO_FRID@0x2FDF00 0x100 + WP_RO@0x0 0x400000 { + RO_SECTION@0x0 0x3e0000 { + BOOTBLOCK@0 128K + COREBOOT(CBFS)@0x20000 0x2e0000 + FMAP@0x300000 0x1000 + GBB@0x301000 0xdef00 + RO_FRID@0x3dff00 0x100 } - RO_VPD@0x2FE000 0x2000 + RO_VPD@0x3e0000 0x20000 } - - RW_NVRAM@0x300000 0x8000 - RW_ELOG@0x308000 0x8000 - RW_VPD@0x310000 0x8000 - RW_CDT@0x318000 0x8000 - - RW_SECTION_A@0x320000 0x268000 { + RW_SECTION_A@0x400000 0x160000 { VBLOCK_A@0x0 0x2000 - FW_MAIN_A(CBFS)@0x2000 0x1E1F00 - RW_FWID_A@0x1E3F00 0x100 - RW_DDR_TRAINING_A@0x1E4000 0x4000 - RW_XBL_BUFFER_A@0x1E8000 0x4000 + FW_MAIN_A(CBFS)@0x2000 0x14df00 + RW_FWID_A@0x14ff00 0x100 + RW_SHARED@0x150000 0x10000 { + SHARED_DATA@0x0 0x10000 + } } - - RW_SHARED@0x588000 0x10000 { - SHARED_DATA@0x0 0x10000 + RW_GPT@0x560000 0x20000 { + RW_GPT_PRIMARY@0x0 0x10000 + RW_GPT_SECONDARY@0x10000 0x10000 } - - RW_SECTION_B@0x598000 0x268000 { + RW_SECTION_B@0x580000 0x160000 { VBLOCK_B@0x0 0x2000 - FW_MAIN_B(CBFS)@0x2000 0x1E1F00 - RW_FWID_B@0x1E3F00 0x100 - RW_DDR_TRAINING_B@0x1E4000 0x4000 - RW_XBL_BUFFER_B@0x1E8000 0x4000 + FW_MAIN_B(CBFS)@0x2000 0x14df00 + RW_FWID_B@0x14ff00 0x100 } + RW_VPD@0x6e0000 0x8000 + RW_ELOG@0x6e8000 0x8000 + RW_NVRAM@0x6f0000 0x10000 + RW_LEGACY(CBFS)@0x700000 0x100000 } -- To view, visit https://review.coreboot.org/c/coreboot/+/30902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I61a82bd8dc6a2f86b72beb8efedaee35897fd66f Gerrit-Change-Number: 30902 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/octopus/variants/meep: Set EN_PP3300_WLAN_L IOStandy to Tx0...
by Kane Chen (Code Review) 09 Apr '19

09 Apr '19

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32248 Change subject: mb/google/octopus/variants/meep: Set EN_PP3300_WLAN_L IOStandy to Tx0RxDCRx0 ...................................................................... mb/google/octopus/variants/meep: Set EN_PP3300_WLAN_L IOStandy to Tx0RxDCRx0 This change is mainly to sync the EN_PP3300_WLAN_L settings with other octopus family project. BUG=b:129377927 Change-Id: I4b497c3db7633354623c94005b3be63151025bc1 Signed-off-by: Kane Chen <kane.chen(a)intel.com> --- M src/mainboard/google/octopus/variants/meep/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/32248/1 diff --git a/src/mainboard/google/octopus/variants/meep/gpio.c b/src/mainboard/google/octopus/variants/meep/gpio.c index 001a488..17157d6 100644 --- a/src/mainboard/google/octopus/variants/meep/gpio.c +++ b/src/mainboard/google/octopus/variants/meep/gpio.c @@ -26,7 +26,7 @@ DISPUPD), /* EN_PP3300_WLAN_L */ - PAD_CFG_GPO(GPIO_178, 0, DEEP), + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), }; const struct pad_config *variant_override_gpio_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/32248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b497c3db7633354623c94005b3be63151025bc1 Gerrit-Change-Number: 32248 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: src: Remove unused variables
by Kyösti Mälkki (Code Review) 09 Apr '19

09 Apr '19

Kyösti Mälkki has removed a vote on this change. Change subject: src: Remove unused variables ...................................................................... Removed Code-Review-2 by Kyösti Mälkki <kyosti.malkki(a)gmail.com> -- To view, visit https://review.coreboot.org/c/coreboot/+/29917 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibdfbf1031130ff861c4313d1271d6ccb68bf8837 Gerrit-Change-Number: 29917 Gerrit-PatchSet: 36 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: deleteVote

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Change in ...coreboot[master]: libpayload: Add UART for qcs405
by Julius Werner (Code Review) 09 Apr '19

09 Apr '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29957 ) Change subject: libpayload: Add UART for qcs405 ...................................................................... Patch Set 20: (8 comments) https://review.coreboot.org/#/c/29957/20/payloads/libpayload/drivers/serial… File payloads/libpayload/drivers/serial/qcs405.c: https://review.coreboot.org/#/c/29957/20/payloads/libpayload/drivers/serial… PS20, Line 286: .uart_dm_base = UART2_DM_BASE, This should be taken from lib_sysinfo.serial->baseaddr rather than hardcoded. (You'll need to implement uart_fill_lb() in coreboot to set that up.) https://review.coreboot.org/#/c/29957/20/payloads/libpayload/drivers/serial… PS20, Line 287: .blsp_uart = BLSP1_UART2, This seems unused? https://review.coreboot.org/#/c/29957/20/payloads/libpayload/drivers/serial… PS20, Line 291: #define read32(addr) readl(addr) These are already defined in <io.h>, don't define them again. https://review.coreboot.org/#/c/29957/20/payloads/libpayload/drivers/serial… PS20, Line 329: * @wait: indicates blocking call or not blocking call This parameter is never set by this driver so you should get rid of it (and associated code). https://review.coreboot.org/#/c/29957/20/payloads/libpayload/drivers/serial… PS20, Line 347: readl readl() is deprecated, use read32() for new code. https://review.coreboot.org/#/c/29957/20/payloads/libpayload/drivers/serial… PS20, Line 373: if (*data == 0) '\0' may be a legal input byte. https://review.coreboot.org/#/c/29957/20/payloads/libpayload/drivers/serial… PS20, Line 544: /* For simplicity sake let's rely on coreboot initalizing the UART. */ You say it, but why aren't you actually doing it? Why do you need that big msm_boot_uart_dm_init() function if coreboot already did that? https://review.coreboot.org/#/c/29957/20/payloads/libpayload/drivers/serial… PS20, Line 556: consout.putchar = serial_putchar; These can be assigned in the struct initializer for consin/consout, they don't need to be here. -- To view, visit https://review.coreboot.org/c/coreboot/+/29957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43164cf9eacc844af1d048f7b6ebbda96fc9d202 Gerrit-Change-Number: 29957 Gerrit-PatchSet: 20 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 09 Apr 2019 01:15:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: TEMP: NOT FOR REVIEW: qcs405: memlayout: Make bootblock 64k aligned
by Julius Werner (Code Review) 08 Apr '19

08 Apr '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29969 ) Change subject: TEMP: NOT FOR REVIEW: qcs405: memlayout: Make bootblock 64k aligned ...................................................................... Patch Set 21: (1 comment) https://review.coreboot.org/#/c/29969/21/src/arch/arm64/armv8/bootblock.S File src/arch/arm64/armv8/bootblock.S: https://review.coreboot.org/#/c/29969/21/src/arch/arm64/armv8/bootblock.S@26 PS21, Line 26: ldr x15, =arm64_init_cpu : blr x15 > what is this change about? See the earlier discussion above... this turns the function call from a relative to an absolute jump, to work around a quirk with the current QC-SEC/bootblock handoff that makes relative jumps not go where expected. I think we should fix the handoff to not be that weird instead, and am still waiting for Sricharan to answer my last comment. -- To view, visit https://review.coreboot.org/c/coreboot/+/29969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1599242bb5158477318867508c72dc14f1244b00 Gerrit-Change-Number: 29969 Gerrit-PatchSet: 21 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Mon, 08 Apr 2019 22:11:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/facebook/watson: Disable turbo
by David Hendricks (Code Review) 08 Apr '19

08 Apr '19

David Hendricks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32222 Change subject: mb/facebook/watson: Disable turbo ...................................................................... mb/facebook/watson: Disable turbo Change-Id: Ief1eaab960c8fdab5bd5041b1a4f0c6ba1dd833f Signed-off-by: David Hendricks <dhendrix(a)fb.com> --- M src/mainboard/facebook/watson/mainboard.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/32222/1 diff --git a/src/mainboard/facebook/watson/mainboard.c b/src/mainboard/facebook/watson/mainboard.c index e6b7850..8b0f129 100644 --- a/src/mainboard/facebook/watson/mainboard.c +++ b/src/mainboard/facebook/watson/mainboard.c @@ -3,6 +3,7 @@ * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2011 Google Inc. + * Copyright (C) 2019-present Facebook Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,6 +15,7 @@ * GNU General Public License for more details. */ +#include <cpu/intel/turbo.h> #include <device/device.h> /* @@ -25,6 +27,12 @@ } +static void mainboard_init(void *chip_info) +{ + disable_turbo(); +} + struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, + .init = mainboard_init, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/32222 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief1eaab960c8fdab5bd5041b1a4f0c6ba1dd833f Gerrit-Change-Number: 32222 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: libpayload/drivers/timer: Use 64 bits to prevent overflow
by Jacob Garber (Code Review) 08 Apr '19

08 Apr '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32223 Change subject: libpayload/drivers/timer: Use 64 bits to prevent overflow ...................................................................... libpayload/drivers/timer: Use 64 bits to prevent overflow Cast cpu_khz to a 64 bit integer to prevent possible integer overflow (the multiplication is currently done using 32 bit math). Similar to 61dac13 (libpayload: timer: cast cpu_khz to make sure 64bit math is used). Found-by: Coverity Scan, CID 1261177 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Change-Id: Iadb0abb7c7cc078f31a6d88d971f5d1b8ac62a9e --- M payloads/libpayload/drivers/timer/img_pistachio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/32223/1 diff --git a/payloads/libpayload/drivers/timer/img_pistachio.c b/payloads/libpayload/drivers/timer/img_pistachio.c index 070998f..d11c3ff 100644 --- a/payloads/libpayload/drivers/timer/img_pistachio.c +++ b/payloads/libpayload/drivers/timer/img_pistachio.c @@ -18,7 +18,7 @@ uint64_t timer_hz(void) { - return lib_sysinfo.cpu_khz * 1000; + return (uint64_t)lib_sysinfo.cpu_khz * 1000; } uint64_t timer_raw_value(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/32223 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iadb0abb7c7cc078f31a6d88d971f5d1b8ac62a9e Gerrit-Change-Number: 32223 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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coreboot-gerrit April 2019