coreboot-gerrit April 2019

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Change in ...coreboot[master]: TEMP: NOT FOR REVIEW: qcs405: Implement bitbang UART for bootblock
by Name of user not set (Code Review) 09 Apr '19

09 Apr '19

nsekar(a)codeaurora.org has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29956 ) Change subject: TEMP: NOT FOR REVIEW: qcs405: Implement bitbang UART for bootblock ...................................................................... Abandoned Intermediate UART driver until the actual UART driver was added. Resolved by CB:29964 -- To view, visit https://review.coreboot.org/c/coreboot/+/29956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib631929f6194d0da8571a930230f0eb460fefaa6 Gerrit-Change-Number: 29956 Gerrit-PatchSet: 15 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: abandon

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Change in ...coreboot[master]: TEMP: NOT FOR REVIEW: libpayload: Fix uart driver for qcs405 support
by Name of user not set (Code Review) 09 Apr '19

09 Apr '19

nsekar(a)codeaurora.org has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29965 ) Change subject: TEMP: NOT FOR REVIEW: libpayload: Fix uart driver for qcs405 support ...................................................................... Abandoned Resolved by CB:29957 -- To view, visit https://review.coreboot.org/c/coreboot/+/29965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied54cf5dd13e9ab752533ad07e9ea906f41060b8 Gerrit-Change-Number: 29965 Gerrit-PatchSet: 15 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: Qcs405: Add SPI chip select assert/de-assert in claim/release bus
by Name of user not set (Code Review) 09 Apr '19

09 Apr '19

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31177 Change subject: Qcs405: Add SPI chip select assert/de-assert in claim/release bus ...................................................................... Qcs405: Add SPI chip select assert/de-assert in claim/release bus Add SPI chip select assert/de-assert in claim/release bus. Configure IO in SPI write function and the keep QUP into run state. Add timeout condition in both SPI write and read functions. Change-Id: Ib8fce5f1890ed3693ee0620cbc0e665d82ce3204 Signed-off-by: Prudhvi Yarlagadda <pyarlaga(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/clock.c M src/soc/qualcomm/qcs405/include/soc/qup.h M src/soc/qualcomm/qcs405/spi.c 3 files changed, 97 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/31177/1 diff --git a/src/soc/qualcomm/qcs405/clock.c b/src/soc/qualcomm/qcs405/clock.c index 41f74be..bccefa7 100644 --- a/src/soc/qualcomm/qcs405/clock.c +++ b/src/soc/qualcomm/qcs405/clock.c @@ -63,6 +63,16 @@ }; struct clock_config spi_cfg[] = { + { + .hz = 1000000, + .hw_ctl = 0x0, + .src = SRC_XO_19_2MHZ, + .div = DIV(48), + //.m = 1, + //.n = 2, + //.d_2 = 4, + }, + { .hz = 19200000, .hw_ctl = 0x0, @@ -210,7 +220,7 @@ REG(GCC_APCS_CLOCK_BRANCH_ENA_VOTE), BLSP1_AHB_CLK_ENA); - clock_configure(blsp1_qup4_spi_clk, spi_cfg, 50000000, + clock_configure(blsp1_qup4_spi_clk, spi_cfg, 1000000, ARRAY_SIZE(spi_cfg)); clock_enable(REG(GCC_BLSP1_QUP4_SPI_APPS_CBCR)); clock_enable_vote(REG(GCC_BLSP1_AHB_CBCR), diff --git a/src/soc/qualcomm/qcs405/include/soc/qup.h b/src/soc/qualcomm/qcs405/include/soc/qup.h index 211b44e..5c1c429 100644 --- a/src/soc/qualcomm/qcs405/include/soc/qup.h +++ b/src/soc/qualcomm/qcs405/include/soc/qup.h @@ -71,6 +71,8 @@ #define OUTPUT_FIFO_FULL (1<<6) #define INPUT_FIFO_NOT_EMPTY (1<<5) #define OUTPUT_FIFO_NOT_EMPTY (1<<4) +#define MAX_OUTPUT_DONE_FLAG (1<<10) +#define MAX_INPUT_DONE_FLAG (1<<11) #define INPUT_SERVICE_FLAG (1<<9) #define OUTPUT_SERVICE_FLAG (1<<8) #define QUP_UNPACK_EN (1<<14) diff --git a/src/soc/qualcomm/qcs405/spi.c b/src/soc/qualcomm/qcs405/spi.c index bd88462..1038881 100644 --- a/src/soc/qualcomm/qcs405/spi.c +++ b/src/soc/qualcomm/qcs405/spi.c @@ -36,6 +36,7 @@ #include <stdlib.h> #include <string.h> #include <spi_flash.h> +#include <timer.h> static const struct blsp_spi spi_reg[] = { /* BLSP0 registers for SPI interface */ @@ -320,47 +321,6 @@ return SUCCESS; } -static int spi_ctrlr_claim_bus(const struct spi_slave *slave) -{ - struct ipq_spi_slave *ds = to_ipq_spi(slave); - unsigned int ret; - - ret = spi_hw_init(ds); - if (ret) - return -EIO; - switch(slave->bus) { - case 5: - - gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - - break; - case 4: - gpio_configure(GPIO(37), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(38), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(117), 2, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); - gpio_configure(GPIO(118), 2, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); - break; - default: - printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); - break; - } - - - return SUCCESS; -} - -static void spi_ctrlr_release_bus(const struct spi_slave *slave) -{ - struct ipq_spi_slave *ds = to_ipq_spi(slave); - - /* Reset the SPI hardware */ - spi_reset(ds); - ds->initialized = 0; -} - static void write_force_cs(const struct spi_slave *slave, int assert) { struct ipq_spi_slave *ds = to_ipq_spi(slave); @@ -380,6 +340,56 @@ return; } + +static int spi_ctrlr_claim_bus(const struct spi_slave *slave) +{ + struct ipq_spi_slave *ds = to_ipq_spi(slave); + unsigned int ret; + + ret = spi_hw_init(ds); + if (ret) + return -EIO; + switch(slave->bus) { + case 4: + gpio_configure(GPIO(37), 2, + GPIO_PULL_DOWN, GPIO_6MA, GPIO_INPUT); //MISO - IN + gpio_configure(GPIO(38), 2, + GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT); //MOSI - Out + gpio_configure(GPIO(117), 2, + GPIO_NO_PULL, GPIO_6MA, GPIO_OUTPUT); //SCLK - out + gpio_configure(GPIO(118), 2, + GPIO_PULL_DOWN, GPIO_6MA, GPIO_OUTPUT); //CS_0 - out + + break; + case 5: + + gpio_configure(GPIO(26), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); + gpio_configure(GPIO(27), 3, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); + gpio_configure(GPIO(28), 4, GPIO_PULL_UP, GPIO_16MA, GPIO_INPUT); + gpio_configure(GPIO(29), 4, GPIO_NO_PULL, GPIO_16MA, GPIO_INPUT); + + break; + default: + printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1, 2, 3, 4, 5) ", slave->bus); + break; + } + + write_force_cs(slave, 1); + + + return SUCCESS; +} + +static void spi_ctrlr_release_bus(const struct spi_slave *slave) +{ + struct ipq_spi_slave *ds = to_ipq_spi(slave); + + /* Reset the SPI hardware */ + write_force_cs(slave, 0); + spi_reset(ds); + ds->initialized = 0; +} + /* * Function to write data to OUTPUT FIFO */ @@ -465,6 +475,7 @@ unsigned int fifo_count; int ret = SUCCESS; int state_config; + struct stopwatch sw; /* Configure no of bytes to read */ state_config = config_spi_state(ds, QUP_STATE_RESET); @@ -505,6 +516,18 @@ } } + stopwatch_init_msecs_expire(&sw, 10); + + do { + val = read32(ds->regs->qup_operational); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "SPI FIFO read timeout \n"); + ret = -ETIMEDOUT; + goto out; + } + + }while(!(val & MAX_INPUT_DONE_FLAG)); + out: /* * Put the SPI Core back in the Reset State @@ -542,15 +565,18 @@ uint32_t val; unsigned int i; unsigned int write_len = bytes; - unsigned int read_len = 3; //bytes; hack for now + unsigned int read_len = bytes; //hack for now unsigned int fifo_count; int ret = SUCCESS; int state_config; + struct stopwatch sw; state_config = config_spi_state(ds, QUP_STATE_RESET); if (state_config) return state_config; + /* Configure input and output enable */ + enable_io_config(ds, write_len, read_len); /* No of bytes to be written in Output FIFO */ write32(ds->regs->qup_mx_output_count, bytes); write32(ds->regs->qup_mx_input_count, bytes); @@ -558,9 +584,6 @@ if (state_config) return state_config; - /* Configure input and output enable */ - enable_io_config(ds, write_len, read_len); - /* * read_len considered to ensure that we read the dummy data for the * write we performed. This is needed to ensure with WR-RD transaction @@ -620,6 +643,18 @@ } } + stopwatch_init_msecs_expire(&sw, 10); + + do { + val = read32(ds->regs->qup_operational); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "SPI FIFO write timeout \n"); + ret = -ETIMEDOUT; + goto out; + } + + }while(!(val & MAX_OUTPUT_DONE_FLAG)); + out: /* * Put the SPI Core back in the Reset State @@ -639,8 +674,10 @@ length = (bytes < MAX_COUNT_SIZE) ? bytes : MAX_COUNT_SIZE; ret = __blsp_spi_write(ds, cmd_buffer, length); - if (ret != SUCCESS) + if (ret != SUCCESS) { + printk(BIOS_ERR, "SPI:DBG write not success \n"); return ret; + } cmd_buffer += length; bytes -= length; @@ -670,8 +707,6 @@ if (ret != SUCCESS) return ret; - write_force_cs(slave, 1); - if (dout != NULL) { ret = blsp_spi_write(ds, txp, (unsigned int) out_bytes); if (ret != SUCCESS) @@ -685,7 +720,6 @@ } out: - write_force_cs(slave, 0); /* * Put the SPI Core back in the Reset State @@ -750,7 +784,7 @@ .setup = spi_ctrlr_setup, .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, - //.xfer = spi_ctrlr_xfer, + .xfer = spi_ctrlr_xfer, .xfer_vector = xfer_vectors, .max_xfer_size = MAX_PACKET_COUNT, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/31177 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8fce5f1890ed3693ee0620cbc0e665d82ce3204 Gerrit-Change-Number: 31177 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

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Change in ...coreboot[master]: TEMP: NOT FOR REVIEW qcs405: Enable bl31
by Name of user not set (Code Review) 09 Apr '19

09 Apr '19

nsekar(a)codeaurora.org has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/31768 ) Change subject: TEMP: NOT FOR REVIEW qcs405: Enable bl31 ...................................................................... Abandoned Resolved by CB:31899 -- To view, visit https://review.coreboot.org/c/coreboot/+/31768 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f7fad22df52d907e9c30c8e59350e34e92a85ec Gerrit-Change-Number: 31768 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: abandon

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Change in ...coreboot[master]: soc/qualcomm/qcs405: Support for new SoC
by Name of user not set (Code Review) 09 Apr '19

09 Apr '19

nsekar(a)codeaurora.org has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/31767 ) Change subject: soc/qualcomm/qcs405: Support for new SoC ...................................................................... Abandoned resolved by CB:29948 -- To view, visit https://review.coreboot.org/c/coreboot/+/31767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e1078b23921f02e505b374ad515ab92260a6dda Gerrit-Change-Number: 31767 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-CC: Sricharan Ramabadhran <srichara(a)qualcomm.corp-partner.google.com> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: qcs405 [temp]: HACK HACK for commit id for VBOOT project
by Name of user not set (Code Review) 09 Apr '19

09 Apr '19

nsekar(a)codeaurora.org has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29974 ) Change subject: qcs405 [temp]: HACK HACK for commit id for VBOOT project ...................................................................... Abandoned Hack patch during development phase. Not needed now -- To view, visit https://review.coreboot.org/c/coreboot/+/29974 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fd040619eb996164e50705fcf16547571e99f99 Gerrit-Change-Number: 29974 Gerrit-PatchSet: 8 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: qcs405 [temp]: REMOVE HACK HACK depthcharge/vboot
by Name of user not set (Code Review) 09 Apr '19

09 Apr '19

nsekar(a)codeaurora.org has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29972 ) Change subject: qcs405 [temp]: REMOVE HACK HACK depthcharge/vboot ...................................................................... Abandoned Hack patch during development phase. Not needed now -- To view, visit https://review.coreboot.org/c/coreboot/+/29972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia520e50d359018ef0a1342d1c98bee8521986139 Gerrit-Change-Number: 29972 Gerrit-PatchSet: 13 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: qcs405: Reduce the reserved memory size
by Name of user not set (Code Review) 09 Apr '19

09 Apr '19

nsekar(a)codeaurora.org has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31176 Change subject: qcs405: Reduce the reserved memory size ...................................................................... qcs405: Reduce the reserved memory size Lets us reserve only for ATF use and give the rest back to Kernel Change-Id: Ibe576b4934e9aa3e5bf1bda71d65c496b42e10f0 Signed-off-by: Nitheesh Sekar <nsekar(a)codeaurora.org> --- M src/soc/qualcomm/qcs405/include/soc/memlayout.ld 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/31176/1 diff --git a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld index 46d4673..ace2e70 100644 --- a/src/soc/qualcomm/qcs405/include/soc/memlayout.ld +++ b/src/soc/qualcomm/qcs405/include/soc/memlayout.ld @@ -56,7 +56,7 @@ DRAM_START(0x80000000) /* Various hardware/software subsystems make use of this area */ - REGION(dram_reserved, 0x85000000, 0x1A800000, 4096) + REGION(dram_reserved, 0x86000000, 0x400000, 4096) POSTRAM_CBFS_CACHE(0x9F800000, 384K) RAMSTAGE(0x9F860000, 128K) } -- To view, visit https://review.coreboot.org/c/coreboot/+/31176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe576b4934e9aa3e5bf1bda71d65c496b42e10f0 Gerrit-Change-Number: 31176 Gerrit-PatchSet: 1 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-MessageType: newchange

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Change in ...coreboot[master]: qcs405: Enable uart_bit_bang
by Name of user not set (Code Review) 09 Apr '19

09 Apr '19

nsekar(a)codeaurora.org has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29961 ) Change subject: qcs405: Enable uart_bit_bang ...................................................................... Abandoned Intermediate UART driver until the actual UART driver was added. Resolved by CB:29964 -- To view, visit https://review.coreboot.org/c/coreboot/+/29961 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I387779a74913ffb58d74d2f2c5d3e22167bbc310 Gerrit-Change-Number: 29961 Gerrit-PatchSet: 7 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: nsekar(a)codeaurora.org Gerrit-MessageType: abandon

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Change in ...coreboot[master]: QCS405: Change DRAM size to 1GB
by Name of user not set (Code Review) 09 Apr '19

09 Apr '19

nsekar(a)codeaurora.org has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29960 ) Change subject: QCS405: Change DRAM size to 1GB ...................................................................... Abandoned resolved by CB:29954 -- To view, visit https://review.coreboot.org/c/coreboot/+/29960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I94f01141d6a537166db3900cf21fc2813cfe96dc Gerrit-Change-Number: 29960 Gerrit-PatchSet: 12 Gerrit-Owner: nsekar(a)codeaurora.org Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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coreboot-gerrit April 2019