coreboot-gerrit April 2019

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Change in ...coreboot[master]: libpayload: Deduplicate strtol and strtoull
by Julius Werner (Code Review) 10 Apr '19

10 Apr '19

Hello Nico Huber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32086 to review the following change. Change subject: libpayload: Deduplicate strtol and strtoull ...................................................................... libpayload: Deduplicate strtol and strtoull Our strtol() and strtoull() function contain almost exactly the same code. This is a) bad in general and b) may cause the code to get out of sync, such as it recently happened with CB:32029. This patch changes strtol() to be based on strtoull() so that the main parsing code exists only once, and also adds a strtoll() to round off the library. Also fix the bounds imposed by strtoul() to be based on the actual length of a 'long', not hardcoded to 32-bits (which is not equivalent on all architectures). Change-Id: I919c65a773cecdb11739c3f22dd0d182ed50c07f Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M payloads/libpayload/include/stdlib.h M payloads/libpayload/libc/string.c 2 files changed, 26 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/32086/1 diff --git a/payloads/libpayload/include/stdlib.h b/payloads/libpayload/include/stdlib.h index aaacc87..d4a7844 100644 --- a/payloads/libpayload/include/stdlib.h +++ b/payloads/libpayload/include/stdlib.h @@ -196,6 +196,7 @@ * @{ */ long int strtol(const char *s, char **nptr, int base); +long long int strtoll(const char *s, char **nptr, int base); unsigned long int strtoul(const char *s, char **nptr, int base); unsigned long long int strtoull(const char *s, char **nptr, int base); long atol(const char *nptr); diff --git a/payloads/libpayload/libc/string.c b/payloads/libpayload/libc/string.c index f563f63..6c257cb 100644 --- a/payloads/libpayload/libc/string.c +++ b/payloads/libpayload/libc/string.c @@ -33,6 +33,7 @@ #include <string.h> #include <ctype.h> #include <inttypes.h> +#include <limits.h> #include <errno.h> /** @@ -419,59 +420,43 @@ * @return A signed integer representation of the string */ -long int strtol(const char *ptr, char **endptr, int base) +long long int strtoll(const char *orig_ptr, char **endptr, int base) { - int ret = 0; - int negative = 1; - - if (endptr != NULL) - *endptr = (char *) ptr; + const char *ptr = orig_ptr; + int is_negative = 0; /* Purge whitespace */ for( ; *ptr && isspace(*ptr); ptr++); if (ptr[0] == '-') { - negative = -1; + is_negative = 1; ptr++; } - if (!*ptr) - return 0; + unsigned long long uval = strtoull(ptr, endptr, base); - /* Determine the base */ + /* If the whole string is unparseable, endptr should point to start. */ + if (endptr && *endptr == ptr) + *endptr = (char *)orig_ptr; - if (base == 0) { - if (ptr[0] == '0' && (ptr[1] == 'x' || ptr[1] == 'X')) - base = 16; - else if (ptr[0] == '0') { - base = 8; - ptr++; - } - else - base = 10; - } + if (uval > (unsigned long long)LLONG_MAX + !!is_negative) + uval = (unsigned long long)LLONG_MAX + !!is_negative; - /* Base 16 allows the 0x on front - so skip over it */ + if (is_negative) + return -uval; + else + return uval; +} - if (base == 16) { - if (ptr[0] == '0' && (ptr[1] == 'x' || ptr[1] == 'X')) - ptr += 2; - } - - /* If the first character isn't valid, then don't - * bother */ - - if (!*ptr || !_valid(*ptr, base)) - return 0; - - for( ; *ptr && _valid(*ptr, base); ptr++) - ret = (ret * base) + _offset(*ptr, base); - - if (endptr != NULL) - *endptr = (char *) ptr; - - return ret * negative; +long int strtol(const char *ptr, char **endptr, int base) +{ + long long int val = strtoll(ptr, endptr, base); + if (val > LONG_MAX) + return LONG_MAX; + if (val < LONG_MIN) + return LONG_MIN; + return val; } long atol(const char *nptr) @@ -534,7 +519,7 @@ unsigned long int strtoul(const char *ptr, char **endptr, int base) { unsigned long long val = strtoull(ptr, endptr, base); - if (val > UINT32_MAX) return UINT32_MAX; + if (val > ULONG_MAX) return ULONG_MAX; return val; } -- To view, visit https://review.coreboot.org/c/coreboot/+/32086 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I919c65a773cecdb11739c3f22dd0d182ed50c07f Gerrit-Change-Number: 32086 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: libpayload: limits.h: Provide reliable definitions for all XXX_MAX/MIN
by Julius Werner (Code Review) 10 Apr '19

10 Apr '19

Hello Nico Huber, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32085 to review the following change. Change subject: libpayload: limits.h: Provide reliable definitions for all XXX_MAX/MIN ...................................................................... libpayload: limits.h: Provide reliable definitions for all XXX_MAX/MIN Our current limits.h only provides (U)INT_MAX constants. This patch adds most others expected by POSIX. Since some of these may be different depending on architecture (e.g. 'long' is 32-bit on x86 and 64-bit on arm64), provide a definition that will automatically figure out the right value for the data model the compiler is using (as long as it's using two's complement for signed integers, which I think we can assume these days). Change-Id: I1124a41279abd4f53d208270e392e590ca8eaada Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M payloads/libpayload/include/limits.h 1 file changed, 15 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/32085/1 diff --git a/payloads/libpayload/include/limits.h b/payloads/libpayload/include/limits.h index 2fecf23..4238e0e 100644 --- a/payloads/libpayload/include/limits.h +++ b/payloads/libpayload/include/limits.h @@ -40,7 +40,20 @@ # endif #endif -#define UINT_MAX (unsigned int)0xffffffff -#define INT_MAX (unsigned int)0x7fffffff +#define USHRT_MAX ((unsigned short int)~0U) +#define SHRT_MIN ((short int)(USHRT_MAX & ~(USHRT_MAX >> 1))) +#define SHRT_MAX ((short int)(USHRT_MAX >> 1)) + +#define UINT_MAX ((unsigned int)~0U) +#define INT_MIN ((int)(UINT_MAX & ~(UINT_MAX >> 1))) +#define INT_MAX ((int)(UINT_MAX >> 1)) + +#define ULONG_MAX ((unsigned long int)~0UL) +#define LONG_MIN ((long int)(ULONG_MAX & ~(ULONG_MAX >> 1))) +#define LONG_MAX ((long int)(ULONG_MAX >> 1)) + +#define ULLONG_MAX ((unsigned long long int)~0UL) +#define LLONG_MIN ((long long int)(ULLONG_MAX & ~(ULLONG_MAX >> 1))) +#define LLONG_MAX ((long long int)(ULLONG_MAX >> 1)) #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/32085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1124a41279abd4f53d208270e392e590ca8eaada Gerrit-Change-Number: 32085 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: libpayload: Fix CONFIG_LP_DEBUG_MALLOC for 64-bit archs
by Patrick Georgi (Code Review) 10 Apr '19

10 Apr '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/14921 ) Change subject: libpayload: Fix CONFIG_LP_DEBUG_MALLOC for 64-bit archs ...................................................................... libpayload: Fix CONFIG_LP_DEBUG_MALLOC for 64-bit archs New compilers are a little more stringent about defining the same prototype more than once, so some of our CONFIG_LP_DEBUG_MALLOC wrappers don't quite work the way they are written anymore. Also, several of the printf()s weren't written 64-bit safe. And let's add some double-evaluation safety while I'm here anyway... and I have no idea why this ever depended on CONFIG_LP_USB, that just seems like a typo. Change-Id: Ib54ebc3cfba99f372690365b78c7ceb372c0bd45 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/14921 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> --- M payloads/libpayload/Kconfig M payloads/libpayload/include/stdlib.h M payloads/libpayload/libc/malloc.c 3 files changed, 91 insertions(+), 102 deletions(-) Approvals: build bot (Jenkins): Verified Hung-Te Lin: Looks good to me, approved diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index fd967c1..5dce89a 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -415,7 +415,6 @@ config DEBUG_MALLOC bool "Debug memory allocator" - depends on USB default n help Select this option if you want to debug the memory allocator. This diff --git a/payloads/libpayload/include/stdlib.h b/payloads/libpayload/include/stdlib.h index aaacc87..3f94d21 100644 --- a/payloads/libpayload/include/stdlib.h +++ b/payloads/libpayload/include/stdlib.h @@ -45,104 +45,6 @@ * @defgroup malloc Memory allocation functions * @{ */ -#if CONFIG(LP_DEBUG_MALLOC) && !defined(IN_MALLOC_C) -#define free(p) \ - ({ \ - extern void print_malloc_map(void); \ - extern void free(void *); \ - printf("free(%p) called from %s:%s:%d...\n", p, __FILE__, __func__, \ - __LINE__);\ - printf("PRE free()\n"); \ - print_malloc_map(); \ - free(p); \ - printf("POST free()\n"); \ - print_malloc_map(); \ - }) -#define malloc(s) \ - ({ \ - extern void print_malloc_map(void); \ - extern void *malloc(size_t); \ - void *ptr; \ - printf("malloc(%u) called from %s:%s:%d...\n", s, __FILE__, __func__, \ - __LINE__);\ - printf("PRE malloc\n"); \ - print_malloc_map(); \ - ptr = malloc(s); \ - printf("POST malloc (ptr = %p)\n", ptr); \ - print_malloc_map(); \ - ptr; \ - }) -#define calloc(n,s) \ - ({ \ - extern void print_malloc_map(void); \ - extern void *calloc(size_t,size_t); \ - void *ptr; \ - printf("calloc(%u, %u) called from %s:%s:%d...\n", n, s, __FILE__, \ - __func__, __LINE__);\ - printf("PRE calloc\n"); \ - print_malloc_map(); \ - ptr = calloc(n,s); \ - printf("POST calloc (ptr = %p)\n", ptr); \ - print_malloc_map(); \ - ptr; \ - }) -#define realloc(p,s) \ - ({ \ - extern void print_malloc_map(void); \ - extern void *realloc(void*,size_t); \ - void *ptr; \ - printf("realloc(%p, %u) called from %s:%s:%d...\n", p, s, __FILE__, \ - __func__, __LINE__);\ - printf("PRE realloc\n"); \ - print_malloc_map(); \ - ptr = realloc(p,s); \ - printf("POST realloc (ptr = %p)\n", ptr); \ - print_malloc_map(); \ - ptr; \ - }) -#define memalign(a,s) \ - ({ \ - extern void print_malloc_map(void); \ - extern void *memalign(size_t, size_t); \ - void *ptr; \ - printf("memalign(%u, %u) called from %s:%s:%d...\n", a, s, __FILE__, \ - __func__, __LINE__);\ - printf("PRE memalign\n"); \ - print_malloc_map(); \ - ptr = memalign(a,s); \ - printf("POST memalign (ptr = %p)\n", ptr); \ - print_malloc_map(); \ - ptr; \ - }) -#define dma_malloc(s) \ - ({ \ - extern void print_malloc_map(void); \ - extern void *dma_malloc(size_t); \ - void *ptr; \ - printf("dma_malloc(%u) called from %s:%s:%d...\n", s, __FILE__, \ - __func__, __LINE__);\ - printf("PRE dma_malloc\n"); \ - print_malloc_map(); \ - ptr = dma_malloc(s); \ - printf("POST dma_malloc (ptr = %p)\n", ptr); \ - print_malloc_map(); \ - ptr; \ - }) -#define dma_memalign(a,s) \ - ({ \ - extern void print_malloc_map(void); \ - extern void *dma_memalign(size_t, size_t); \ - void *ptr; \ - printf("dma_memalign(%u, %u) called from %s:%s:%d...\n", a, s, \ - __FILE__, __func__, __LINE__);\ - printf("PRE dma_memalign\n"); \ - print_malloc_map(); \ - ptr = dma_memalign(a,s); \ - printf("POST dma_memalign (ptr = %p)\n", ptr); \ - print_malloc_map(); \ - ptr; \ - }) -#else void free(void *ptr); void *malloc(size_t size); void *calloc(size_t nmemb, size_t size); @@ -150,7 +52,95 @@ void *memalign(size_t align, size_t size); void *dma_malloc(size_t size); void *dma_memalign(size_t align, size_t size); + +#if CONFIG(LP_DEBUG_MALLOC) && !defined(IN_MALLOC_C) +#include <stdio.h> +void print_malloc_map(void); +#define free(p) ({ \ + void *__p = p; \ + printf("free(%p) called from %s:%s:%d...\n", __p, __FILE__, __func__, \ + __LINE__);\ + printf("PRE free()\n"); \ + print_malloc_map(); \ + free(__p); \ + printf("POST free()\n"); \ + print_malloc_map(); \ +}) +#define malloc(s) ({ \ + size_t __s = s; \ + void *ptr; \ + printf("malloc(%zu) called from %s:%s:%d...\n", __s, __FILE__, \ + __func__, __LINE__);\ + printf("PRE malloc\n"); \ + print_malloc_map(); \ + ptr = malloc(__s); \ + printf("POST malloc (ptr = %p)\n", ptr); \ + print_malloc_map(); \ + ptr; \ +}) +#define calloc(n, s) ({ \ + size_t __n = n, __s = s; \ + void *ptr; \ + printf("calloc(%zu, %zu) called from %s:%s:%d...\n", __n, __s, \ + __FILE__, __func__, __LINE__);\ + printf("PRE calloc\n"); \ + print_malloc_map(); \ + ptr = calloc(__n, __s); \ + printf("POST calloc (ptr = %p)\n", ptr); \ + print_malloc_map(); \ + ptr; \ +}) +#define realloc(p, s) ({ \ + void *__p = p; \ + size_t __s = s; \ + void *ptr; \ + printf("realloc(%p, %zu) called from %s:%s:%d...\n", __p, __s, \ + __FILE__, __func__, __LINE__);\ + printf("PRE realloc\n"); \ + print_malloc_map(); \ + ptr = realloc(__p, __s); \ + printf("POST realloc (ptr = %p)\n", ptr); \ + print_malloc_map(); \ + ptr; \ +}) +#define memalign(a, s) ({ \ + size_t __a = a, __s = s; \ + void *ptr; \ + printf("memalign(%zu, %zu) called from %s:%s:%d...\n", __a, __s, \ + __FILE__, __func__, __LINE__);\ + printf("PRE memalign\n"); \ + print_malloc_map(); \ + ptr = memalign(__a, __s); \ + printf("POST memalign (ptr = %p)\n", ptr); \ + print_malloc_map(); \ + ptr; \ +}) +#define dma_malloc(s) ({ \ + size_t __s = s; \ + void *ptr; \ + printf("dma_malloc(%zu) called from %s:%s:%d...\n", __s, __FILE__, \ + __func__, __LINE__);\ + printf("PRE dma_malloc\n"); \ + print_malloc_map(); \ + ptr = dma_malloc(__s); \ + printf("POST dma_malloc (ptr = %p)\n", ptr); \ + print_malloc_map(); \ + ptr; \ +}) +#define dma_memalign(a, s) ({ \ + size_t __a = a, __s = s; \ + void *ptr; \ + printf("dma_memalign(%zu, %zu) called from %s:%s:%d...\n", __a, __s, \ + __FILE__, __func__, __LINE__);\ + printf("PRE dma_memalign\n"); \ + print_malloc_map(); \ + ptr = dma_memalign(__a, __s); \ + printf("POST dma_memalign (ptr = %p)\n", ptr); \ + print_malloc_map(); \ + ptr; \ +}) #endif + void init_dma_memory(void *start, u32 size); int dma_initialized(void); int dma_coherent(void *ptr); diff --git a/payloads/libpayload/libc/malloc.c b/payloads/libpayload/libc/malloc.c index 957f0e0..5107589 100644 --- a/payloads/libpayload/libc/malloc.c +++ b/payloads/libpayload/libc/malloc.c @@ -480,7 +480,7 @@ if ((reg->alignment == align) && (reg->free >= (size + align - 1)/align)) { #if CONFIG(LP_DEBUG_MALLOC) - printf(" found memalign region. %x free, %x required\n", reg->free, (size + align - 1)/align); + printf(" found memalign region. %u free, %zu required\n", reg->free, (size + align - 1)/align); #endif break; } @@ -563,7 +563,7 @@ /* FIXME: Verify the size of the block. */ - printf("%s %x: %s (%x bytes)\n", type->name, + printf("%s %x: %s (%llx bytes)\n", type->name, (unsigned int)(ptr - type->start), hdr & FLAG_FREE ? "FREE" : "USED", SIZE(hdr)); @@ -575,7 +575,7 @@ if (free_memory && (type->minimal_free > free_memory)) type->minimal_free = free_memory; - printf("%s: Maximum memory consumption: %u bytes\n", type->name, + printf("%s: Maximum memory consumption: %zu bytes\n", type->name, (type->end - type->start) - HDRSIZE - type->minimal_free); if (type != dma) { -- To view, visit https://review.coreboot.org/c/coreboot/+/14921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib54ebc3cfba99f372690365b78c7ceb372c0bd45 Gerrit-Change-Number: 14921 Gerrit-PatchSet: 7 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <f4bug(a)amsat.org> Gerrit-Reviewer: Uwe Hermann <uwe(a)hermann-uwe.de> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in ...coreboot[master]: Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Ch...
by EricR Lai (Code Review) 10 Apr '19

10 Apr '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32264 Change subject: Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I77d4aa39cee875dd1b6ab8ffa89454c2e5c13ab5 ...................................................................... Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: I77d4aa39cee875dd1b6ab8ffa89454c2e5c13ab5 --- M src/mainboard/google/hatch/variants/hatch/overridetree.cb M src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb 2 files changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/32264/1 diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index 28644d1..7d668fe 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -68,6 +68,19 @@ register "stop_off_delay_ms" = "5" device i2c 49 on end end + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "30" + register "generic.reset_off_delay_ms" = "3" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end end # I2C #1 device pci 15.2 on chip drivers/generic/gpio_keys diff --git a/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb b/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb index 9b772c2..caa80a5 100644 --- a/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb @@ -53,6 +53,19 @@ register "stop_off_delay_ms" = "5" device i2c 49 on end end + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" + register "generic.reset_delay_ms" = "30" + register "generic.reset_off_delay_ms" = "3" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end + end end # I2C #1 device pci 15.2 on chip drivers/generic/gpio_keys -- To view, visit https://review.coreboot.org/c/coreboot/+/32264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I77d4aa39cee875dd1b6ab8ffa89454c2e5c13ab5 Gerrit-Change-Number: 32264 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: tint: introduce the new tint build system with checksum verification
by mikeb mikeb (Code Review) 10 Apr '19

10 Apr '19

mikeb mikeb has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23856 ) Change subject: tint: introduce the new tint build system with checksum verification ...................................................................... Patch Set 12: Code-Review+1 > Patch Set 12: > > Luckily ./util/crossgcc/buildgcc script is quite stable - no major changes at its' core functions for at least half year - so the minor maintenance for my tint build system is rarely needed. ;-) I'm rebasing it sometimes to show that I tested it recently and its still working good. This change is important because it adds the checksum verification for tint archive that's downloaded from FSF mirror. I trust FSF, but what if their server is hacked and tint archive replaced with something malicious? If we are the only people who are getting tint from them, such a change - without the checksum verification - could be unnoticed. Or maybe a MitM attack (replace the archive only for one person) -- To view, visit https://review.coreboot.org/c/coreboot/+/23856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d24f222d1b92030b81bba3951e243a2a9f37290 Gerrit-Change-Number: 23856 Gerrit-PatchSet: 12 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Comment-Date: Wed, 10 Apr 2019 08:28:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: tint: introduce the new tint build system with checksum verification
by mikeb mikeb (Code Review) 10 Apr '19

10 Apr '19

mikeb mikeb has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23856 ) Change subject: tint: introduce the new tint build system with checksum verification ...................................................................... Patch Set 12: Luckily ./util/crossgcc/buildgcc script is quite stable - no major changes at its' core functions for at least half year - so the minor maintenance for my tint build system is rarely needed. ;-) I'm rebasing it sometimes to show that I tested it recently and its still working good. -- To view, visit https://review.coreboot.org/c/coreboot/+/23856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d24f222d1b92030b81bba3951e243a2a9f37290 Gerrit-Change-Number: 23856 Gerrit-PatchSet: 12 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Comment-Date: Wed, 10 Apr 2019 08:19:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: libpayload: Fix CONFIG_LP_DEBUG_MALLOC for 64-bit archs
by Hung-Te Lin (Code Review) 10 Apr '19

10 Apr '19

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/14921 ) Change subject: libpayload: Fix CONFIG_LP_DEBUG_MALLOC for 64-bit archs ...................................................................... Patch Set 6: Code-Review+2 Yes I do. Let's get this merged. -- To view, visit https://review.coreboot.org/c/coreboot/+/14921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib54ebc3cfba99f372690365b78c7ceb372c0bd45 Gerrit-Change-Number: 14921 Gerrit-PatchSet: 6 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <f4bug(a)amsat.org> Gerrit-Reviewer: Uwe Hermann <uwe(a)hermann-uwe.de> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 10 Apr 2019 07:25:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/drivers/intel/fsp2_0: Added FSP_S component to VBOOT Stage Verifi...
by Amol N Sukerkar (Code Review) 09 Apr '19

09 Apr '19

Hello Patrick Rudolph, Subrata Banik, Philipp Deppenwiese, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/32155 to look at the new patch set (#2). Change subject: src/drivers/intel/fsp2_0: Added FSP_S component to VBOOT Stage Verification. FSP_S component will be verified in RAMSTAGE. ...................................................................... src/drivers/intel/fsp2_0: Added FSP_S component to VBOOT Stage Verification. FSP_S component will be verified in RAMSTAGE. When VBOOT Stage Verification is enabled, FSP_S component needs to be verified. This logic has been added. TEST=Create a coreboot.rom image by enabling CONFIG_VBOOT and CONFIG_VBOOT_STAGE_VERIFICATION. Verify that the image boots to authenticated payload and graphics is displayed via HDMI and Display Port. Change-Id: Ifefad96b54388143fecb56f0402c3b627ae6350d Signed-off-by: Sukerkar, Amol N <amol.n.sukerkar(a)intel.com> --- M src/drivers/intel/fsp2_0/silicon_init.c 1 file changed, 35 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/32155/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/32155 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifefad96b54388143fecb56f0402c3b627ae6350d Gerrit-Change-Number: 32155 Gerrit-PatchSet: 2 Gerrit-Owner: Amol N Sukerkar <amol.n.sukerkar(a)intel.com> Gerrit-Reviewer: Amol N Sukerkar <amol.n.sukerkar(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: src/lib: Changed the syntax of verify_stage_if_required to accommodat...
by Amol N Sukerkar (Code Review) 09 Apr '19

09 Apr '19

Hello Subrata Banik, Philipp Deppenwiese, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/32154 to look at the new patch set (#2). Change subject: src/lib: Changed the syntax of verify_stage_if_required to accommodate name of the component and added config flags to select them conditionally ...................................................................... src/lib: Changed the syntax of verify_stage_if_required to accommodate name of the component and added config flags to select them conditionally When VBOOT Stage Verification is enabled, the components are verified after they are loaded into DRAM. This requires identifying them by their name so they can be selectively verified as required. TEST=Create a coreboot.rom image by enabling CONFIG_VBOOT and CONFIG_VBOOT_STAGE_VERIFICATION. Verify that the image boots to authenticated payload and graphics is displayed via HDMI and Display Port. Change-Id: I8184a432a32338d1c0aaa362d34de5306ec08eb9 Signed-off-by: Sukerkar, Amol N <amol.n.sukerkar(a)intel.com> --- M src/include/cbfs.h M src/lib/Kconfig M src/lib/cbfs.c M src/lib/selfboot.c 4 files changed, 24 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/32154/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/32154 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8184a432a32338d1c0aaa362d34de5306ec08eb9 Gerrit-Change-Number: 32154 Gerrit-PatchSet: 2 Gerrit-Owner: Amol N Sukerkar <amol.n.sukerkar(a)intel.com> Gerrit-Reviewer: Amol N Sukerkar <amol.n.sukerkar(a)intel.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: [WIP]mainboard/lenovo/t410: Add new port
by Peter Lemenkov (Code Review) 09 Apr '19

09 Apr '19

Peter Lemenkov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/11791 ) Change subject: [WIP]mainboard/lenovo/t410: Add new port ...................................................................... Patch Set 13: > Any new progress on this? Seems like a very interesting port > potential. Please try latest patch. I've just updated it to compile against current master. UNTESTED!!!! BEWARE!!! -- To view, visit https://review.coreboot.org/c/coreboot/+/11791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Gerrit-Change-Number: 11791 Gerrit-PatchSet: 13 Gerrit-Owner: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eloy Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Okashi Odayakana <brianblevins316(a)gmail.com> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Comment-Date: Tue, 09 Apr 2019 18:05:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit April 2019