coreboot-gerrit April 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: mb/ocp/monolake: Add board.fmd
by David Hendricks (Code Review) 10 Apr '19

10 Apr '19

David Hendricks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32260 Change subject: mb/ocp/monolake: Add board.fmd ...................................................................... mb/ocp/monolake: Add board.fmd Change-Id: I6095c3b30990b530c5bc4e2c808879252680e1d7 Signed-off-by: Andrea Barberio <barberio(a)fb.com> Signed-off-by: David Hendricks <dhendrix(a)fb.com> --- A src/mainboard/ocp/monolake/board.fmd 1 file changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/32260/1 diff --git a/src/mainboard/ocp/monolake/board.fmd b/src/mainboard/ocp/monolake/board.fmd new file mode 100644 index 0000000..d0265e4 --- /dev/null +++ b/src/mainboard/ocp/monolake/board.fmd @@ -0,0 +1,22 @@ +FLASH@0xff000000 0x1000000 { + SI_ALL@0x0 0x800000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x7ff000 + } + SI_BIOS@0x800000 0x800000 { + FMAP@0x0 0x1000 + RW_MISC@0x1000 0x9000 { + RW_ELOG@0x0 0x4000 + RW_VPD@0x4000 0x2000 + RW_NVRAM@0x6000 0x2000 + } + UNUSED@0xa000 0x4000 { + # This only exists to satisfy tools that + # specifically look for RO_VPD. + RO_VPD@0x0 0x4000 + } + RW_MRC_CACHE@0xE000 0x10000 + CONSOLE@0x1E000 0x10000 + COREBOOT(CBFS)@0x2E000 0x7d2000 + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32260 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6095c3b30990b530c5bc4e2c808879252680e1d7 Gerrit-Change-Number: 32260 Gerrit-PatchSet: 1 Gerrit-Owner: David Hendricks <david.hendricks(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/sarien/arcada: modify some gpio as NC
by Casper Chang (Code Review) 10 Apr '19

10 Apr '19

Casper Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32259 Change subject: mb/google/sarien/arcada: modify some gpio as NC ...................................................................... mb/google/sarien/arcada: modify some gpio as NC modify following gipo as NC. /* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), /* I2C5_SDA */ PAD_NC(GPP_H10, NONE), /* I2C5_SCL */ PAD_NC(GPP_H11, NONE), BUG=b:129990365 TEST=build image pass Change-Id: Iaf751ec82ff74b2b97a7d8141db59236778712c7 --- M src/mainboard/google/sarien/variants/arcada/gpio.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/32259/1 diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c index 1b06301..9ede492 100644 --- a/src/mainboard/google/sarien/variants/arcada/gpio.c +++ b/src/mainboard/google/sarien/variants/arcada/gpio.c @@ -71,7 +71,7 @@ /* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), /* PRIM_CORE_OPT_DIS (nostuff) */ /* GSPI0_CLK */ PAD_CFG_GPI(GPP_B16, NONE, DEEP), /* ONE_DIMM# */ -/* GSPI0_MISO */ PAD_CFG_GPI(GPP_B17, NONE, DEEP), /* RTC_DET# */ +/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), /* RTC_DET# */ /* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), /* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */ /* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */ @@ -209,8 +209,8 @@ /* I2C3_SCL */ PAD_NC(GPP_H7, NONE), /* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ /* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ -/* I2C5_SDA */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* ISH_I2C2_SDA */ -/* I2C5_SCL */ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* ISH_I2C2_SCL */ +/* I2C5_SDA */ PAD_NC(GPP_H10, NONE), /* ISH_I2C2_SDA */ +/* I2C5_SCL */ PAD_NC(GPP_H11, NONE), /* ISH_I2C2_SCL */ /* M2_SKT2_CFG0 */ PAD_NC(GPP_H12, NONE), /* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE), /* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/32259 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf751ec82ff74b2b97a7d8141db59236778712c7 Gerrit-Change-Number: 32259 Gerrit-PatchSet: 1 Gerrit-Owner: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: [WIP]mainboard/lenovo/t410: Add new port
by Okashi Odayakana (Code Review) 10 Apr '19

10 Apr '19

Okashi Odayakana has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/11791 ) Change subject: [WIP]mainboard/lenovo/t410: Add new port ...................................................................... Patch Set 13: > Patch Set 13: > > > Any new progress on this? Seems like a very interesting port > > potential. > > Please try latest patch. I've just updated it to compile against current master. > > UNTESTED!!!! BEWARE!!! Will try as soon as I get my SPI flasher to work. Christ these SBCs are annoying. -- To view, visit https://review.coreboot.org/c/coreboot/+/11791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Gerrit-Change-Number: 11791 Gerrit-PatchSet: 13 Gerrit-Owner: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eloy Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Okashi Odayakana <brianblevins316(a)gmail.com> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Comment-Date: Wed, 10 Apr 2019 14:05:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: Doc/mb/asrock/h110m: update info about PEG
by Maxim Polyakov (Code Review) 10 Apr '19

10 Apr '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31949 Change subject: Doc/mb/asrock/h110m: update info about PEG ...................................................................... Doc/mb/asrock/h110m: update info about PEG - Now there is no need to additionally configure the FSP before building; - PEG works with high link speed 8 GT/s (Gen 3); - external GPU supported, but dynamic switching between iGPU and PEG is not yet supported. Change-Id: Ie0f9db47c0b88052b090cba139f0ae821758935d Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M Documentation/mainboard/asrock/h110m-dvs.md 1 file changed, 6 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/31949/1 diff --git a/Documentation/mainboard/asrock/h110m-dvs.md b/Documentation/mainboard/asrock/h110m-dvs.md index 7bc38ff..c9be798 100644 --- a/Documentation/mainboard/asrock/h110m-dvs.md +++ b/Documentation/mainboard/asrock/h110m-dvs.md @@ -23,22 +23,10 @@ Please take FSP from the directory `3rdparty/fsp/KabylakeFspBinPkg/` in the coreboot or download the latest version from [github][FSP github]. - -You must use [Intel Binary Configuration Tool] BCT to set the following -parameters in FSP.fd to initialize the PEG x16 port: - -```eval_rst - Peg0Enable = Enable - Peg0MaxLinkSpeed = Gen3 - Peg0MaxLinkWidth = Auto -``` - -BCT creates Fsp_M.fd, Fsp_S.fd and Fsp_T.fd. These files are integrated -into the coreboot image. If PEG port is not used, you can get these files -without BTC: +You must prepare the FSP for integration into the coreboot image: ```bash -# split FSP.fd +# split FSP.fd: Fsp_M.fd and Fsp_S.fd should be used in building the image python 3rdparty/fsp/Tools/SplitFspBin.py split -f 3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd ``` @@ -97,10 +85,9 @@ ## Known issues -- The VGA port doesn't work. - -- PEG x16 port training correctly runs only at link speed of 2.5GT/s(gen1). - It takes more time to research the schematic of this board. +- The VGA port doesn't work. Discrete graphic card is used as primary + device for display output (if CONFIG_ONBOARD_VGA_IS_PRIMARY is not + set). Dynamic switching between iGPU and PEG is not yet supported. - SuperIO GPIO pin is used to reset Realtek chip. However, since the Logical Device 7 (GPIO6, GPIO7, GPIO8) is not initialized, the network @@ -121,7 +108,7 @@ - integrated graphics init with libgfxinit (see [Known issues](#known-issues)) - PCIe x1 -- PEG x16 Gen1 (see [Known issues](#known-issues)) +- PEG x16 Gen3 - SATA - USB - serial port @@ -131,7 +118,6 @@ ## TODO -- PEG x16 Gen3 - NCT6791D GPIOs - onboard network (see [Known issues](#known-issues)) - S3 suspend/resume @@ -156,7 +142,6 @@ [ASRock H110M-DVS]: https://www.asrock.com/mb/Intel/H110M-DVS%20R2.0/ [FSP github]: https://github.com/IntelFsp/FSP -[Intel Binary Configuration Tool]: https://github.com/IntelFsp/BCT [MX25L6473E]: http://www.macronix.com/Lists/Datasheet/Attachments/7380/MX25L6473E,%203V,%… [flashrom]: https://flashrom.org/Flashrom [H110M-DVS manual]: http://asrock.pc.cdn.bitgravity.com/Manual/H110M-DVS%20R2.0.pdf -- To view, visit https://review.coreboot.org/c/coreboot/+/31949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0f9db47c0b88052b090cba139f0ae821758935d Gerrit-Change-Number: 31949 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/intel/fsp1_1: Configure UART after memory init
by Patrick Rudolph (Code Review) 10 Apr '19

10 Apr '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28464 ) Change subject: drivers/intel/fsp1_1: Configure UART after memory init ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/28464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb6c9e4153b3de58791b211c7f4241be3bceae9d Gerrit-Change-Number: 28464 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Wed, 10 Apr 2019 13:47:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/soc/intel/braswell: Remove disabled LPE ACPI code
by Frans Hendriks (Code Review) 10 Apr '19

10 Apr '19

Hello Patrick Rudolph, Piotr Król, build bot (Jenkins), Hannah Williams, Michał Żygowski, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/29414 to look at the new patch set (#7). Change subject: src/soc/intel/braswell: Remove disabled LPE ACPI code ...................................................................... src/soc/intel/braswell: Remove disabled LPE ACPI code The ACPI code for LPE device was included regardless of the availability of the LPE controller. Move the LPE ACPI code to separate SSDT and hide it when LPE is disabled. BUG=N/A TEST=Intel CherryHill CRB Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/mainboard/google/cyan/Makefile.inc M src/mainboard/google/cyan/acpi/codec_maxim.asl M src/mainboard/google/cyan/acpi/codec_realtek.asl A src/mainboard/google/cyan/acpi/jack_board.asl A src/mainboard/google/cyan/acpi/jack_detect.asl A src/mainboard/google/cyan/ssdtlpe.asl A src/mainboard/google/cyan/variants/banon/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/celes/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/cyan/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/edgar/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/kefka/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/reks/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/relm/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/setzer/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/terra/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/ultima/include/variant/acpi/lpe.asl A src/mainboard/google/cyan/variants/wizpig/include/variant/acpi/lpe.asl M src/mainboard/intel/strago/Makefile.inc M src/mainboard/intel/strago/acpi/mainboard.asl A src/mainboard/intel/strago/ssdtlpe.asl M src/soc/intel/braswell/acpi/southcluster.asl M src/soc/intel/braswell/include/soc/acpi.h M src/soc/intel/braswell/lpe.c 23 files changed, 392 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/29414/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/29414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73 Gerrit-Change-Number: 29414 Gerrit-PatchSet: 7 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: drivers/intel/fsp1_1: Configure UART after memory init
by Frans Hendriks (Code Review) 10 Apr '19

10 Apr '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28464 ) Change subject: drivers/intel/fsp1_1: Configure UART after memory init ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/28464/2/src/drivers/intel/fsp1_1/raminit.c File src/drivers/intel/fsp1_1/raminit.c: https://review.coreboot.org/#/c/28464/2/src/drivers/intel/fsp1_1/raminit.c@… PS2, Line 327: void) > move void to the previous line Done -- To view, visit https://review.coreboot.org/c/coreboot/+/28464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb6c9e4153b3de58791b211c7f4241be3bceae9d Gerrit-Change-Number: 28464 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Wed, 10 Apr 2019 13:29:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: comment

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Change in ...coreboot[master]: soc/skl: Use devtree options to set primary GPU
by Maxim Polyakov (Code Review) 10 Apr '19

10 Apr '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32044 Change subject: soc/skl: Use devtree options to set primary GPU ...................................................................... soc/skl: Use devtree options to set primary GPU List of options: - InternalGfx, - PrimaryDisplay, - SkipExtGfxScan. Change-Id: Ie3f9362676105e41c69139a094dbb9e8b865689f Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/skylake/romstage/romstage_fsp20.c 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/32044/1 diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index 43ba9c9..f38a775 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -274,6 +274,16 @@ /* Enable SMBus controller based on config */ m_cfg->SmbusEnable = config->SmbusEnable; + /* Set primary graphic device */ + if (CONFIG(ONBOARD_VGA_IS_PRIMARY)) { + m_cfg->PrimaryDisplay = 0; + m_cfg->InternalGfx = 1; + } else { + m_cfg->PrimaryDisplay = config->PrimaryDisplay; + m_cfg->InternalGfx = config->InternalGfx; + } + m_t_cfg->SkipExtGfxScan = config->SkipExtGfxScan; + mainboard_memory_init_params(mupd); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32044 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3f9362676105e41c69139a094dbb9e8b865689f Gerrit-Change-Number: 32044 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: tint: introduce the new tint build system with checksum verification
by mikeb mikeb (Code Review) 10 Apr '19

10 Apr '19

mikeb mikeb has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23856 ) Change subject: tint: introduce the new tint build system with checksum verification ...................................................................... Patch Set 12: -Code-Review Thank you, I will update my commit message a bit later, and already removed +1 (which I initially added only to display my confidence in this commit, since this +1 stands for "Looks good to me, but someone else must approve", but now I understand this is not needed) > 2. Why not just extend the target below with the checksum verification? > > ``` > download: > test -d tint || { wget $(project_url); \ > tar -xvf $(archive_name); \ > rm $(archive_name); \ > mv tint-0.04+nmu1 tint; } > ``` buildgcc script has a lot of useful functions that I wanted to borrow, for example: # Find all the required tools: TAR=$(searchtool tar) || exit $? PATCH=$(searchtool patch) || exit $? MAKE=$(searchtool make) || exit $? SHA1SUM=$(searchtool sha1sum) #SHA512SUM=$(searchtool sha512sum) #MD5SUM=$(searchtool md5sum) CHECKSUM=$SHA1SUM LBZIP2=$(searchtool lbzip2 "" nofail) PIGZ=$(searchtool pigz "" nofail) Here is how the generated tint .sh looks like - https://pastebin.com/jY8A5juD I didn't want to simply copy these functions to avoid the need of keeping this copy up-to-date (or it becoming outdated). My "tint build system" will do it automatically by always generating this tint .sh script by itself, using the parts of fresh buildgcc script from a coreboot tree. -- To view, visit https://review.coreboot.org/c/coreboot/+/23856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d24f222d1b92030b81bba3951e243a2a9f37290 Gerrit-Change-Number: 23856 Gerrit-PatchSet: 12 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Comment-Date: Wed, 10 Apr 2019 12:42:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: tint: introduce the new tint build system with checksum verification
by Paul Menzel (Code Review) 10 Apr '19

10 Apr '19

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23856 ) Change subject: tint: introduce the new tint build system with checksum verification ...................................................................... Patch Set 12: 1. Please describe the deficiencies of the current system in the commit message. 2. Why not just extend the target below with the checksum verification? ``` download: test -d tint || { wget $(project_url); \ tar -xvf $(archive_name); \ rm $(archive_name); \ mv tint-0.04+nmu1 tint; } ``` 3. Please do not score your own change-sets. -- To view, visit https://review.coreboot.org/c/coreboot/+/23856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d24f222d1b92030b81bba3951e243a2a9f37290 Gerrit-Change-Number: 23856 Gerrit-PatchSet: 12 Gerrit-Owner: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mikeb mikeb <mikebdp2(a)gmail.com> Gerrit-Comment-Date: Wed, 10 Apr 2019 11:56:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit April 2019