coreboot-gerrit April 2019

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Change in ...coreboot[master]: drivers/spi: Move M25Pxx commands to spi_winbond.h
by Frans Hendriks (Code Review) 11 Apr '19

11 Apr '19

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31710 Change subject: drivers/spi: Move M25Pxx commands to spi_winbond.h ...................................................................... drivers/spi: Move M25Pxx commands to spi_winbond.h Move Wnbond M25PXX command values to spi_winbond.h Now the commands value can be used for programming SPI contoller of Intel Braswell, by using including file. Update winbond.c file with coreboot header. BUG=N/A TEST=Facebook FBG-1701 with flashrom Change-Id: I9c17c4ed7004209bd3c619d47a7474b0b7e17495 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- A src/drivers/spi/spi_winbond.h M src/drivers/spi/winbond.c 2 files changed, 49 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/31710/1 diff --git a/src/drivers/spi/spi_winbond.h b/src/drivers/spi/spi_winbond.h new file mode 100644 index 0000000..e21571c --- /dev/null +++ b/src/drivers/spi/spi_winbond.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2008, Network Appliance Inc. + * Author: Jason McMullan <mcmullan <at> netapp.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Winbond specific function */ +/* M25Pxx-specific commands */ +#define CMD_W25_WREN 0x06 /* Write Enable */ +#define CMD_W25_WRDI 0x04 /* Write Disable */ +#define CMD_W25_RDSR 0x05 /* Read Status Register */ +#define CMD_W25_WRSR 0x01 /* Write Status Register */ +#define CMD_W25_RDSR2 0x35 /* Read Status2 Register */ +#define CMD_W25_WRSR2 0x31 /* Write Status2 Register */ +#define CMD_W25_READ 0x03 /* Read Data Bytes */ +#define CMD_W25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ +#define CMD_W25_PP 0x02 /* Page Program */ +#define CMD_W25_SE 0x20 /* Sector (4K) Erase */ +#define CMD_W25_RDID 0x9f /* Read ID */ +#define CMD_W25_BE 0xd8 /* Block (64K) Erase */ +#define CMD_W25_CE 0xc7 /* Chip Erase */ +#define CMD_W25_DP 0xb9 /* Deep Power-down */ +#define CMD_W25_RES 0xab /* Release from DP and Read Signature */ +#define CMD_VOLATILE_SREG_WREN 0x50 /* Write Enable for Volatile SREG */ + +/* tw: Maximum time to write a flash cell in milliseconds */ +#define WINBOND_FLASH_TIMEOUT 30 diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index 8bf8fcd..7276ec1 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -1,7 +1,16 @@ /* * Copyright 2008, Network Appliance Inc. - * Author: Jason McMullan <mcmullan <at> netapp.com> - * Licensed under the GPL-2 or later. + * Jason McMullan <mcmullan(a)netapp.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. */ #include <console/console.h> @@ -14,26 +23,7 @@ #include <lib.h> #include "spi_flash_internal.h" - -/* M25Pxx-specific commands */ -#define CMD_W25_WREN 0x06 /* Write Enable */ -#define CMD_W25_WRDI 0x04 /* Write Disable */ -#define CMD_W25_RDSR 0x05 /* Read Status Register */ -#define CMD_W25_WRSR 0x01 /* Write Status Register */ -#define CMD_W25_RDSR2 0x35 /* Read Status2 Register */ -#define CMD_W25_WRSR2 0x31 /* Write Status2 Register */ -#define CMD_W25_READ 0x03 /* Read Data Bytes */ -#define CMD_W25_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ -#define CMD_W25_PP 0x02 /* Page Program */ -#define CMD_W25_SE 0x20 /* Sector (4K) Erase */ -#define CMD_W25_BE 0xd8 /* Block (64K) Erase */ -#define CMD_W25_CE 0xc7 /* Chip Erase */ -#define CMD_W25_DP 0xb9 /* Deep Power-down */ -#define CMD_W25_RES 0xab /* Release from DP, and Read Signature */ -#define CMD_VOLATILE_SREG_WREN 0x50 /* Write Enable for Volatile SREG */ - -/* tw: Maximum time to write a flash cell in milliseconds */ -#define WINBOND_FLASH_TIMEOUT 30 +#include "spi_winbond.h" struct winbond_spi_flash_params { uint16_t id; -- To view, visit https://review.coreboot.org/c/coreboot/+/31710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c17c4ed7004209bd3c619d47a7474b0b7e17495 Gerrit-Change-Number: 31710 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/intel/fsp1_1: Configure UART after memory init
by Patrick Georgi (Code Review) 11 Apr '19

11 Apr '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28464 ) Change subject: drivers/intel/fsp1_1: Configure UART after memory init ...................................................................... Patch Set 4: makes sense, yes -- To view, visit https://review.coreboot.org/c/coreboot/+/28464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb6c9e4153b3de58791b211c7f4241be3bceae9d Gerrit-Change-Number: 28464 Gerrit-PatchSet: 4 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Thu, 11 Apr 2019 11:58:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: drivers/intel/fsp1_1: Configure UART after memory init
by Patrick Georgi (Code Review) 11 Apr '19

11 Apr '19

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/28464 ) Change subject: drivers/intel/fsp1_1: Configure UART after memory init ...................................................................... drivers/intel/fsp1_1: Configure UART after memory init FSP code will default enable the onboard serial port. When external serial port is used, this onboard port needs to be disabled. Add function mainboard_after_memory_init() function to perform required actions to re-enabled output to external serial port. BUG=N/A TEST=LPC Post card on Intel Cherry Hill Change-Id: Ibb6c9e4153b3de58791b211c7f4241be3bceae9d Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/28464 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/drivers/intel/fsp1_1/include/fsp/romstage.h M src/drivers/intel/fsp1_1/raminit.c 2 files changed, 9 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/drivers/intel/fsp1_1/include/fsp/romstage.h b/src/drivers/intel/fsp1_1/include/fsp/romstage.h index e266bee..d608484 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/romstage.h +++ b/src/drivers/intel/fsp1_1/include/fsp/romstage.h @@ -3,6 +3,7 @@ * * Copyright (C) 2014 Google Inc. * Copyright (C) 2015-2016 Intel Corporation + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -91,5 +92,6 @@ /* Update the SOC specific memory config param for mma. */ void soc_update_memory_params_for_mma(MEMORY_INIT_UPD *memory_cfg, struct mma_config_param *mma_cfg); +void mainboard_after_memory_init(void); #endif /* _COMMON_ROMSTAGE_H_ */ diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 2dd5c77..8405c94 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -125,6 +125,7 @@ timestamp_add_now(TS_FSP_MEMORY_INIT_START); post_code(POST_FSP_MEMORY_INIT); status = fsp_memory_init(&fsp_memory_init_params); + mainboard_after_memory_init(); post_code(0x37); timestamp_add_now(TS_FSP_MEMORY_INIT_END); @@ -322,3 +323,9 @@ { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } + +/* Initialize the SoC after MemoryInit */ +__weak void mainboard_after_memory_init(void) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/28464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb6c9e4153b3de58791b211c7f4241be3bceae9d Gerrit-Change-Number: 28464 Gerrit-PatchSet: 4 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: merged

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Change in ...coreboot[master]: drivers/intel/fsp1_1: Configure UART after memory init
by Frans Hendriks (Code Review) 11 Apr '19

11 Apr '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28464 ) Change subject: drivers/intel/fsp1_1: Configure UART after memory init ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/28464/3/src/drivers/intel/fsp1_1/raminit.c File src/drivers/intel/fsp1_1/raminit.c: https://review.coreboot.org/#/c/28464/3/src/drivers/intel/fsp1_1/raminit.c@… PS3, Line 128: mainboard_after_memory_init > so you call the function and add a weak stub below. […] This function is used with update of Facebook FBG-1701 ( https://review.coreboot.org/c/coreboot/+/30414) Note: At the moment I created this patch, I was not aware that you can rebase a patch. The 30414 patch requires the function prototype of this patch. To have the 30414 patch build, I removed the call of mainboard_after_memory_init(). My plan is to wait till this patch in merged before updating the other patch. Does this make sense? -- To view, visit https://review.coreboot.org/c/coreboot/+/28464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb6c9e4153b3de58791b211c7f4241be3bceae9d Gerrit-Change-Number: 28464 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Thu, 11 Apr 2019 11:54:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: comment

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Change in ...coreboot[master]: src/mainboard/portwell/m107: Do initial mainboard commit
by Michał Żygowski (Code Review) 11 Apr '19

11 Apr '19

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29470 ) Change subject: src/mainboard/portwell/m107: Do initial mainboard commit ...................................................................... Patch Set 8: (23 comments) https://review.coreboot.org/#/c/29470/8/Documentation/mainboard/portwell/pq… File Documentation/mainboard/portwell/pq7-m107.md: https://review.coreboot.org/#/c/29470/8/Documentation/mainboard/portwell/pq… PS8, Line 5: ## Required blobs How about microcode state? Does the board run with microcode generated from tree? https://review.coreboot.org/#/c/29470/8/Documentation/mainboard/portwell/pq… PS8, Line 11: You may also consider committing a miniconfig to the configs/ directory. https://review.coreboot.org/#/c/29470/8/Documentation/mainboard/portwell/pq… PS8, Line 39: The main SPI flash can be accessed using [flashrom]. Please clean up the obsolete whitespaces at the end of lines. https://review.coreboot.org/#/c/29470/8/Documentation/mainboard/portwell/pq… PS8, Line 43: The flash chip is a 64 MiB socketed DIP-8 chip. Specifically, it's a W25Q64FW is a 64 Megabit flash = 8MiB. Please correct. https://review.coreboot.org/#/c/29470/8/Documentation/mainboard/portwell/pq… PS8, Line 56: - flashing coreboot How did You verify Your patch then if not even tested flashing coreboot? https://review.coreboot.org/#/c/29470/8/Documentation/mainboard/portwell/pq… PS8, Line 59: - Full Embedded controller support Embedded Controller https://review.coreboot.org/#/c/29470/8/src/mainboard/portwell/m107/Kconfig File src/mainboard/portwell/m107/Kconfig: https://review.coreboot.org/#/c/29470/8/src/mainboard/portwell/m107/Kconfig… PS8, Line 55: config ROM_SIZE Already set to 8MiB in the board specific options. Any reasoning for duplicating the setting? https://review.coreboot.org/#/c/29470/8/src/mainboard/portwell/m107/Kconfig… PS8, Line 64: config SPI_FLASH_INCLUDE_ALL_DRIVERS Would be great to have all these optimizations in a miniconfig file. https://review.coreboot.org/#/c/29470/8/src/mainboard/portwell/m107/Makefil… File src/mainboard/portwell/m107/Makefile.inc: https://review.coreboot.org/#/c/29470/8/src/mainboard/portwell/m107/Makefil… PS8, Line 26: ## Please select GENERIC_SPD_BIN option in the board specific options and define SPD_SOURCES variable with the name of SPD file without spd.hex extension. And also get rid of CONFIG_MAINBOARD_SPD0_FILE_NAME in Kconfig file then. It will do the same magic as You have written here. https://review.coreboot.org/#/c/29470/8/src/mainboard/portwell/m107/acpi/dp… File src/mainboard/portwell/m107/acpi/dptf.asl: https://review.coreboot.org/#/c/29470/8/src/mainboard/portwell/m107/acpi/dp… PS8, Line 1: /* Is this ASL file included anywhere? If not, what is the reasoning of committing the file? https://review.coreboot.org/#/c/29470/8/src/mainboard/portwell/m107/acpi/su… File src/mainboard/portwell/m107/acpi/superio.asl: https://review.coreboot.org/#/c/29470/8/src/mainboard/portwell/m107/acpi/su… PS8, Line 21: Device (COM1) { Why it is indented? https://review.coreboot.org/#/c/29470/8/src/mainboard/portwell/m107/board_i… File src/mainboard/portwell/m107/board_info.txt: https://review.coreboot.org/#/c/29470/8/src/mainboard/portwell/m107/board_i… PS8, Line 3: Category: misc Isn't it SBC? https://review.coreboot.org/#/c/29470/8/src/mainboard/portwell/m107/devicet… File src/mainboard/portwell/m107/devicetree.cb: https://review.coreboot.org/#/c/29470/8/src/mainboard/portwell/m107/devicet… PS8, Line 27: register "PcdEnableLpe" = "1" LPE is enabled here, but not described in domain 0. What is the intention of setting it to enabled? https://review.coreboot.org/#/c/29470/8/src/mainboard/portwell/m107/devicet… PS8, Line 43: register "PcdEnableSata" = "0" # Disable SATA The product specification on Portwell site says there are 2x SATA ports. Does carrier board not have the SATA ports? https://review.coreboot.org/#/c/29470/8/src/mainboard/portwell/m107/devicet… PS8, Line 75: register "DptfDisable" = "1" Here DPTF is disabled so there is less sense to have the DPTF ASL code in the mainboard tree. https://review.coreboot.org/#/c/29470/8/src/mainboard/portwell/m107/devicet… PS8, Line 99: device pci 0b.0 on end # 8086 22DC - PUNIT/DPTF Now the DPTF is on? I am lost. What is Your intention? Please elaborate. https://review.coreboot.org/#/c/29470/8/src/mainboard/portwell/m107/devicet… PS8, Line 102: device pci 14.0 on end # 8086 22b5 - USB XHCI - Only 1 USB controller at a time Maybe consider declaring SATA controller as disabled here explicitly. https://review.coreboot.org/#/c/29470/8/src/mainboard/portwell/m107/dsdt.asl File src/mainboard/portwell/m107/dsdt.asl: https://review.coreboot.org/#/c/29470/8/src/mainboard/portwell/m107/dsdt.as… PS8, Line 36: #include <acpi/cpu.asl> Intel board should have unified CPU ASL code as introduced by the patch https://review.coreboot.org/c/coreboot/+/29894: <cpu/intel/common/acpi/cpu.asl> https://review.coreboot.org/#/c/29470/8/src/mainboard/portwell/m107/fadt.c File src/mainboard/portwell/m107/fadt.c: https://review.coreboot.org/#/c/29470/8/src/mainboard/portwell/m107/fadt.c@… PS8, Line 36: fadt->model = 1; model field is no longer used AFAIK https://review.coreboot.org/#/c/29470/8/src/mainboard/portwell/m107/gpio.c File src/mainboard/portwell/m107/gpio.c: https://review.coreboot.org/#/c/29470/8/src/mainboard/portwell/m107/gpio.c@… PS8, Line 18: #include "irqroute.h" Is this include needed? https://review.coreboot.org/#/c/29470/8/src/mainboard/portwell/m107/gpio.c@… PS8, Line 258: Empty line, please remove https://review.coreboot.org/#/c/29470/8/src/mainboard/portwell/m107/romstag… File src/mainboard/portwell/m107/romstage.c: https://review.coreboot.org/#/c/29470/8/src/mainboard/portwell/m107/romstag… PS8, Line 33: ps->spd_data_ch0 = cbfs_boot_map_with_leak(buf, CBFS_TYPE_SPD, NULL); With GENERIC_SPD_BIN option the function will be: cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, NULL); https://review.coreboot.org/#/c/29470/8/src/mainboard/portwell/m107/smihand… File src/mainboard/portwell/m107/smihandler.c: https://review.coreboot.org/#/c/29470/8/src/mainboard/portwell/m107/smihand… PS8, Line 61: case ACPI_S3: The board does not seem to support S3 sleep state, only S4. Why this case exists then? -- To view, visit https://review.coreboot.org/c/coreboot/+/29470 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d3173fdcf881f894a75cd9798ba173b425d4e62 Gerrit-Change-Number: 29470 Gerrit-PatchSet: 8 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Comment-Date: Thu, 11 Apr 2019 11:44:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/asrock/h110m: Add virtual LDN for SurerIO to DT
by Maxim Polyakov (Code Review) 11 Apr '19

11 Apr '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32267 Change subject: mb/asrock/h110m: Add virtual LDN for SurerIO to DT ...................................................................... mb/asrock/h110m: Add virtual LDN for SurerIO to DT Adds virtual logical devices numbers for the Nuvoton (NCT6791D) SuperIO to the devicetree. Change-Id: I7df1633951c30fef14c62c89aaedebd3044b312f Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/mainboard/asrock/h110m/devicetree.cb 1 file changed, 19 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/32267/1 diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index e13076e..158801f 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -344,11 +344,18 @@ irq 0x72 = 12 # Mouse end device pnp 2e.6 off end # CIR - device pnp 2e.7 off end # GPIO6..8 - # WDT1, WDT_MEM, GPIO 0, GPIO 1 - device pnp 2e.8 off end - # GPIO 2, GPIO 3, GPIO 4, GPIO 5 - device pnp 2e.9 off end + device pnp 2e.7 off end # GPIO6 + device pnp 2e.107 off end # GPIO7 + device pnp 2e.207 off end # GPIO8 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO0 + device pnp 2e.308 off end # GPIO base + device pnp 2e.408 off end # WDTMEM + device pnp 2e.708 off end # GPIO1 + device pnp 2e.9 off end # GPIO2 + device pnp 2e.109 off end # GPIO3 + device pnp 2e.209 off end # GPIO4 + device pnp 2e.309 off end # GPIO5 device pnp 2e.a off end # ACPI device pnp 2e.b on # HWM, LED io 0x60 = 0x0290 @@ -359,7 +366,13 @@ device pnp 2e.e off end # CIR wake-up device pnp 2e.f off end # GPIO PP/OD device pnp 2e.14 off end # SVID, Port 80 UART - device pnp 2e.16 off end # Deep sleep + device pnp 2e.16 off end # DS5 + device pnp 2e.116 off end # DS3 + device pnp 2e.316 off end # PCHDSW + device pnp 2e.416 off end # DSWWOPT + device pnp 2e.516 off end # DS3OPT + device pnp 2e.616 off end # DSDSS + device pnp 2e.716 off end # DSPU end # superio/nuvoton/nct6791d chip drivers/pc80/tpm device pnp 4e.0 on end # TPM module -- To view, visit https://review.coreboot.org/c/coreboot/+/32267 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7df1633951c30fef14c62c89aaedebd3044b312f Gerrit-Change-Number: 32267 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: google/kukui: Add variant 'Krane'
by Hung-Te Lin (Code Review) 11 Apr '19

11 Apr '19

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32261 Change subject: google/kukui: Add variant 'Krane' ...................................................................... google/kukui: Add variant 'Krane' Add the new configuration 'Krane' that will need at least its own EC. There's currently no difference in Coreboot side, simply a symlink. BUG=b:130011505 TEST=make menuconfig; make -j # select board=Krane BRANCH=None Change-Id: Ibb2ec42b08f9a51b22c22f3fe99b203f5eb31627 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- M src/mainboard/google/kukui/Kconfig M src/mainboard/google/kukui/Kconfig.name 2 files changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/32261/1 diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig index 9f477e5..6831d1e 100644 --- a/src/mainboard/google/kukui/Kconfig +++ b/src/mainboard/google/kukui/Kconfig @@ -45,6 +45,7 @@ config MAINBOARD_PART_NUMBER string default "Kukui" if BOARD_GOOGLE_KUKUI + default "Krane" if BOARD_GOOGLE_KRANE default "Flapjack" if BOARD_GOOGLE_FLAPJACK config DRIVER_TPM_SPI_BUS @@ -63,6 +64,7 @@ string depends on CHROMEOS default "KUKUI TEST 9847" if BOARD_GOOGLE_KUKUI + default "KRANE TEST 5417" if BOARD_GOOGLE_KRANE default "FLAPJACK TEST 4147" if BOARD_GOOGLE_FLAPJACK endif diff --git a/src/mainboard/google/kukui/Kconfig.name b/src/mainboard/google/kukui/Kconfig.name index 6c84e26..348be66 100644 --- a/src/mainboard/google/kukui/Kconfig.name +++ b/src/mainboard/google/kukui/Kconfig.name @@ -4,6 +4,10 @@ bool "-> Kukui" select BOARD_GOOGLE_KUKUI_COMMON +config BOARD_GOOGLE_KRANE + bool "-> Krane" + select BOARD_GOOGLE_KUKUI_COMMON + config BOARD_GOOGLE_FLAPJACK bool "-> Flapjack" select BOARD_GOOGLE_KUKUI_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/32261 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb2ec42b08f9a51b22c22f3fe99b203f5eb31627 Gerrit-Change-Number: 32261 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/i945: Use macro instead of magic number
by HAOUAS Elyes (Code Review) 11 Apr '19

11 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/30993 Change subject: nb/intel/i945: Use macro instead of magic number ...................................................................... nb/intel/i945: Use macro instead of magic number Aslo add comments on Read/Write-Once bits. ULBA register is 64bits, so maybe there is a typo on RCBA(0x114) and it should be 0x11b insted. Change-Id: I3f2199d6da22ce9995496c2a81363710edde81f3 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M 3rdparty/blobs M src/northbridge/intel/i945/early_init.c 2 files changed, 8 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/30993/1 diff --git a/3rdparty/blobs b/3rdparty/blobs index 16058e5..998982d 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 16058e552279b4884b1f671e7a78752d28abd1cc +Subproject commit 998982d714a08481bb4944f456929be06b5e696f diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 6bfa1c7..70b8152 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -883,10 +883,13 @@ static void ich7_setup_root_complex_topology(void) { - RCBA32(0x104) = 0x00000802; - RCBA32(0x110) = 0x00000001; - RCBA32(0x114) = 0x00000000; - RCBA32(0x118) = 0x00000000; + /* FIXME: ESD [23:16] is R/WO */ + RCBA32(ESD) = 0x00000802; + /* FIXME: ULD [31:16] is R/WO */ + RCBA32(ULD) = 0x00000001; + /* FIXME: ULBA [63:0] is R/WO */ + RCBA32(0x114) = 0x00000000; // RCBA32(0x11b) ? + RCBA32(ULBA) = 0x00000000; } static void ich7_setup_pci_express(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/30993 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f2199d6da22ce9995496c2a81363710edde81f3 Gerrit-Change-Number: 30993 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/intel/fsp1_1: Configure UART after memory init
by Patrick Georgi (Code Review) 11 Apr '19

11 Apr '19

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/28464 ) Change subject: drivers/intel/fsp1_1: Configure UART after memory init ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/28464/3/src/drivers/intel/fsp1_1/raminit.c File src/drivers/intel/fsp1_1/raminit.c: https://review.coreboot.org/#/c/28464/3/src/drivers/intel/fsp1_1/raminit.c@… PS3, Line 128: mainboard_after_memory_init so you call the function and add a weak stub below. but where's the override that actually does something with this? -- To view, visit https://review.coreboot.org/c/coreboot/+/28464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb6c9e4153b3de58791b211c7f4241be3bceae9d Gerrit-Change-Number: 28464 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Thu, 11 Apr 2019 11:30:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/google/sarien: resvered gpio pins for D3 cold control
by EricR Lai (Code Review) 11 Apr '19

11 Apr '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32242 Change subject: mb/google/sarien: resvered gpio pins for D3 cold control ...................................................................... mb/google/sarien: resvered gpio pins for D3 cold control Base on HW change, resvered gpio pins for D3 cold control. A13,A15 for Card reader H13 for M.2 SSD BUG=b:123263562 TEST=N/A Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ib4245be8d77c015e56df7b1d53ef82722c51d656 --- M src/mainboard/google/sarien/variants/sarien/gpio.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32242/1 diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c index ff311b1..91934b1 100644 --- a/src/mainboard/google/sarien/variants/sarien/gpio.c +++ b/src/mainboard/google/sarien/variants/sarien/gpio.c @@ -31,9 +31,9 @@ /* CLKOUT_LPC1 */ PAD_NC(GPP_A10, NONE), /* PME# */ PAD_NC(GPP_A11, NONE), /* BM_BUSY# */ PAD_NC(GPP_A12, NONE), -/* SUSWARN# */ PAD_NC(GPP_A13, NONE), +/* SUSWARN# */ PAD_CFG_GPO(GPP_A13, 1, DEEP), /* Card reader D3 cold */ /* ESPI_RESET# */ -/* SUSACK# */ PAD_NC(GPP_A15, NONE), +/* SUSACK# */ PAD_CFG_GPO(GPP_A15, 1, DEEP), /* Card reader D3 cold */ /* SD_1P8_SEL */ PAD_NC(GPP_A16, NONE), /* SD_PWR_EN# */ PAD_NC(GPP_A17, NONE), /* ISH_GP0 */ PAD_NC(GPP_A18, NONE), @@ -198,7 +198,7 @@ /* I2C5_SDA */ PAD_NC(GPP_H10, NONE), /* I2C5_SCL */ PAD_NC(GPP_H11, NONE), /* M2_SKT2_CFG0 */ PAD_NC(GPP_H12, NONE), -/* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE), +/* M2_SKT2_CFG1 */ PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */ /* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), /* M2_SKT2_CFG3 */ PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */ /* DDPF_CTRLCLK */ PAD_NC(GPP_H16, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/32242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib4245be8d77c015e56df7b1d53ef82722c51d656 Gerrit-Change-Number: 32242 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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