coreboot-gerrit April 2019

coreboot-gerrit@coreboot.org

1 participants
1219 discussions

Change in ...coreboot[master]: kconfig_lint: Make uses of CONFIG() on an unknown option an error
by Julius Werner (Code Review) 11 Apr '19

11 Apr '19

Hello Nico Huber, Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32257 to review the following change. Change subject: kconfig_lint: Make uses of CONFIG() on an unknown option an error ...................................................................... kconfig_lint: Make uses of CONFIG() on an unknown option an error This check had very few false positives which were all easily resolved, and it's unlikely that further false positives will become problematic in the future. On the other hand, it does detect a very severe bug (when you think you're using a Kconfig but you aren't due to a typo), so since warnings are currently not very visible, let's turn this into an error because the pros clearly outweigh the cons for that. Change-Id: I897b5e13d3242fb77b69f0bd3585baa7476aa726 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- M util/lint/kconfig_lint 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/32257/1 diff --git a/util/lint/kconfig_lint b/util/lint/kconfig_lint index 6cf05a4..308c423 100755 --- a/util/lint/kconfig_lint +++ b/util/lint/kconfig_lint @@ -47,7 +47,7 @@ my $exclude_dirs_and_files = '^build/\|^coreboot-builds/\|^configs/\|^util/\|^\.git/\|^payloads\|^Documentation\|^3rdparty' . '\|' . # directories to exclude when searching for used symbols - '\.config\|\.txt$\|\.tex$\|\.tags'; #files to exclude when looking for symbols + '\.config\|\.txt$\|\.tex$\|\.tags\|/kconfig.h'; #files to exclude when looking for symbols my $payload_files_to_check='payloads/Makefile.inc payloads/external/Makefile.inc'; my $config_file = ""; # name of config file to load symbol values from. my @wholeconfig; # document the entire kconfig structure @@ -333,7 +333,7 @@ } } else { - show_warning("CONFIG() used on unknown value ($symbol) at $file:$lineno."); + show_error("CONFIG() used on unknown value ($symbol) at $file:$lineno."); } } } elsif ( $line =~ /^([^:]+):(\d+):(.+IS_ENABLED.*)/ ) { -- To view, visit https://review.coreboot.org/c/coreboot/+/32257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I897b5e13d3242fb77b69f0bd3585baa7476aa726 Gerrit-Change-Number: 32257 Gerrit-PatchSet: 1 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 4

Change in ...coreboot[master]: nb/amd/amdfam10/util.c: Use "CONFIG" only when appropriate
by HAOUAS Elyes (Code Review) 11 Apr '19

11 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31848 Change subject: nb/amd/amdfam10/util.c: Use "CONFIG" only when appropriate ...................................................................... nb/amd/amdfam10/util.c: Use "CONFIG" only when appropriate Change-Id: Idcdbbfa883c906db1ebb8d9bc7c9e277e7c0c949 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/amd/amdfam10/util.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/31848/1 diff --git a/src/northbridge/amd/amdfam10/util.c b/src/northbridge/amd/amdfam10/util.c index 41f4deb..9941aec 100644 --- a/src/northbridge/amd/amdfam10/util.c +++ b/src/northbridge/amd/amdfam10/util.c @@ -135,7 +135,7 @@ static void showconfig(int level, u8 which, u32 reg) { /* Don't use r_node() and r_link() here. */ - printk(level, "CONFIG(%02x)%02x-%02x ->(%d,%d),%s %s (%s numbers)\n", + printk(level, "Config(%02x)%02x-%02x ->(%d,%d),%s %s (%s numbers)\n", which, BITS(reg, 16, 0xff), BITS(reg, 24, 0xff), BITS(reg, 4, 0x7), BITS(reg, 8, 0x3), re(reg), we(reg), -- To view, visit https://review.coreboot.org/c/coreboot/+/31848 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idcdbbfa883c906db1ebb8d9bc7c9e277e7c0c949 Gerrit-Change-Number: 31848 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: Documentation: Convert lenovo codenames to markdown
by Patrick Rudolph (Code Review) 11 Apr '19

11 Apr '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32250 Change subject: Documentation: Convert lenovo codenames to markdown ...................................................................... Documentation: Convert lenovo codenames to markdown Change-Id: I7fd61bd7a4e8818901520311332ae4027e7a7d02 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/mainboard/index.md A Documentation/mainboard/lenovo/codenames.md D Documentation/thinkpad/codenames.csv 3 files changed, 67 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/32250/1 diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index d94c23e..7eaf425 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -51,6 +51,7 @@ ## Lenovo +- [Mainboard codenames](lenovo/codenames.md) - [Hardware Maintenance Manual of ThinkPads](lenovo/thinkpad_hmm.md) - [T4xx common](lenovo/t4xx_series.md) - [X2xx common](lenovo/x2xx_series.md) diff --git a/Documentation/mainboard/lenovo/codenames.md b/Documentation/mainboard/lenovo/codenames.md new file mode 100644 index 0000000..9f54633 --- /dev/null +++ b/Documentation/mainboard/lenovo/codenames.md @@ -0,0 +1,66 @@ +# Lenovo mainboard codenames + + +```eval_rst ++----------------+----------------------------+ +| Marketing name | Development codename | ++================+============================+ +| T60 | magi-5 / magi-7 / austin-3 | ++----------------+----------------------------+ +| T400 | malibu-3 | ++----------------+----------------------------+ +| T400s | shinai | ++----------------+----------------------------+ +| T410 | nozomi-1 | ++----------------+----------------------------+ +| T410s | shinai-2 | ++----------------+----------------------------+ +| T420 | nozomi-3 | ++----------------+----------------------------+ +| T420s | shinai-3 | ++----------------+----------------------------+ +| T430 | nozomi-4 | ++----------------+----------------------------+ +| T430s | lsn-4 | ++----------------+----------------------------+ +| T500 | coronado-5 | ++----------------+----------------------------+ +| T510 | kendo-1 | ++----------------+----------------------------+ +| T520 | kendo-3 | ++----------------+----------------------------+ +| T530 | kendo-4 | ++----------------+----------------------------+ +| W500 | coronada-5 | ++----------------+----------------------------+ +| W510 | kendo-1 workstation | ++----------------+----------------------------+ +| W520 | kendo-3 workstation | ++----------------+----------------------------+ +| W530 | kendo-4 workstation | ++----------------+----------------------------+ +| W700 | n-note | ++----------------+----------------------------+ +| X1 Carbon Gen1 | genesis-1 | ++----------------+----------------------------+ +| X60 | ks note | ++----------------+----------------------------+ +| X61 | ks note-3 | ++----------------+----------------------------+ +| X200 | mocha-1 | ++----------------+----------------------------+ +| X201 | mocha-3 | ++----------------+----------------------------+ +| X220 | dasher-1 | ++----------------+----------------------------+ +| X230 | dasher-2 | ++----------------+----------------------------+ +| X230s | rogue-1 | ++----------------+----------------------------+ +| X240 | rogue-2 | ++----------------+----------------------------+ +| X300 | kodachi | ++----------------+----------------------------+ +| X301 | kodachi-2 | ++----------------+----------------------------+ +``` diff --git a/Documentation/thinkpad/codenames.csv b/Documentation/thinkpad/codenames.csv deleted file mode 100644 index ad77059..0000000 --- a/Documentation/thinkpad/codenames.csv +++ /dev/null @@ -1,29 +0,0 @@ -t60,magi-5|magi-7|austin-3 -t400,malibu-3 -t400s,shinai -t410,nozomi-1 -t410s,shinai-2 -t420,nozomi-3 -t420s,shinai-3 -t430,nozomi-4 -t430s,lsn-4 -t500,coronado-5 -t510,kendo-1 -t520,kendo-3 -t530,kendo-4 -w500,coronado-5 -w510,kendo-1 workstation -w520,kendo-3 workstation -w530,kendo-4 workstation -w700,n-note -x1_carbon_gen1,genesis-1 -x60,ks note -x61,ks note-3 -x200,mocha-1 -x201,mocha-3 -x220,dasher-1 -x230,dasher-2 -x230s,rogue-1 -x240,rogue-2 -x300,kodachi -x301,kodachi-2 -- To view, visit https://review.coreboot.org/c/coreboot/+/32250 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7fd61bd7a4e8818901520311332ae4027e7a7d02 Gerrit-Change-Number: 32250 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 7

Change in ...coreboot[master]: Documentation: Allow the use of CSV
by Patrick Rudolph (Code Review) 11 Apr '19

11 Apr '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32251 Change subject: Documentation: Allow the use of CSV ...................................................................... Documentation: Allow the use of CSV Allow the use of CSV files if properly referenced from markdown. Sphinx will parse the file and create a human readable table, allowing easy integration of autogenerated files. Change-Id: I6fa13acf67ff1c6c9e3985054405c5446808da03 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/getting_started/writing_documentation.md 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/32251/1 diff --git a/Documentation/getting_started/writing_documentation.md b/Documentation/getting_started/writing_documentation.md index 0ba17e3..ac425ef 100644 --- a/Documentation/getting_started/writing_documentation.md +++ b/Documentation/getting_started/writing_documentation.md @@ -100,6 +100,20 @@ you'll see the following warning: **WARNING: document isn't included in any toctree** +## CSV + +You can import CSV files and let sphinx automatically convert them to human +readable tables, using the following reStructuredText snipped: + + ```eval_rst + .. csv-table:: + :header: "Key", "Value" + :file: keyvalues.csv + ``` + +Of course this can only be done from a markdown file that is included in the +TOC tree. + [coreboot]: https://coreboot.org [Documentation]: https://review.coreboot.org/cgit/coreboot.git/tree/Documentation [shpinx-autobuild]: https://github.com/GaretJax/sphinx-autobuild -- To view, visit https://review.coreboot.org/c/coreboot/+/32251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6fa13acf67ff1c6c9e3985054405c5446808da03 Gerrit-Change-Number: 32251 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

3 2

Change in ...coreboot[master]: Documentation: Add coreboot architecture
by Patrick Rudolph (Code Review) 11 Apr '19

11 Apr '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32123 Change subject: Documentation: Add coreboot architecture ...................................................................... Documentation: Add coreboot architecture Describe the coreboot stages, given a short introduction what is done and add a chart for coreboot's vs EDK II bootflow. TODO: Describe stages and payloads in detail Change-Id: I98cb61b1d0d29ac9d03f5ef3644d51a8e14bad74 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- A Documentation/getting_started/architecture.md A Documentation/getting_started/comparision_coreboot_uefi.svg M Documentation/getting_started/index.md 3 files changed, 287 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/32123/1 diff --git a/Documentation/getting_started/architecture.md b/Documentation/getting_started/architecture.md new file mode 100644 index 0000000..f8f8b3d --- /dev/null +++ b/Documentation/getting_started/architecture.md @@ -0,0 +1,110 @@ +# coreboot architecture + +## Overwiew +![][architecture] + +[architecture]: comparision_coreboot_uefi.svg + +## Stages +The stages are compiled as seperate binaries and are inserted into the CBFS with +custom compression. The bootblock usually doesn't have compression, while the +ramstage and payload are compressed with LZMA. + +Each stage loads the next stage at given address (possibly decompressing it). + +Some stages are relocatable and can be placed anywhere in DRAM. Those stages are +usually cached in CBMEM for faster loading times on ACPI S3 resume. + +## bootblock +The bootblock is the first stage executed after CPU reset. It is written in +assembly language and its main task is to setup everything for a C-environment: + +Common tasks: + +* Cache-As-RAM for heap and stack +* Set stack pointer +* Clear memory for BSS +* Decompress and load the next stage + +On x86 platforms that includes: + +* Microcode updates +* Timer init +* Switching from 16-bit real-mode to 32-bit protected mode + +The bootblock loads the romstage or the verstage if verified boot is enabled. + +### Cache-As-Ram +The *Cache-As-Ram*, also called Non-Eviction mode, or *CAR* allows to use the +CPU cache like regular SRAM. This is particullary usefull for high level +languages like `C`, which need RAM for heap and stack. + +The CAR needs to be actived using vendor specific CPU instructions. + +The following stages run when Cache-As-Ram is active: +* bootblock +* romstage +* verstage +* postcar + +## verstage +The verstage is where the root-of-trust starts. It's assumed that +it cannot be overwritten in-field (together with the public key) and +that starts at the very beginning of the boot process. +The verstage installs a hook to verify a file before it's loaded from +CBFS or a partition before it's accessed. + +The verified boot mechanism allows trusted in-field firmware updates +combined with a fail-safe recovery mode. + +## romstage +The romstage initialized the DRAM and prepares everything for device init. + +Common tasks: + +* DRAM init +* Early device init + +## postcar +To leave the CAR setup and run code from regular DRAM the postcar-stage tears +down CAR and loads the ramstage. Compared to other stages it's minimal in size. + +## ramstage + +The ramstage does the main device init: + +* PCI device init +* On-chip device init +* TPM init +* Graphics init (optional) +* CPU init (like set up SMM) + +After initialization tables are written to inform the payload about the current +hardware existance and state. That includes: + +* ACPI tables (x86 specific) +* SMBIOS tables (x86 specific) +* coreboot tables +* devicetree updates (ARM specific) + +It also does hardware and firmware lockdown: +* Write-protection of boot media +* Lock security related registers +* Lock SMM mode (x86 specific) + +## payload +The payload is the software that is run after coreboot is done. It resides in +the CBFS and there's no possibility to choose it at runtime. +Some payloads, like *SeaBios*, offer to load `secondary payloads` at runtime. + +Supported payloads are: + +* [SeaBIOS](https://www.seabios.org/SeaBIOS) +* [Tianocore](https://www.tianocore.org/) +* [GRUB](https://www.gnu.org/software/grub/) +* [Depthcharge](https://chromium.googlesource.com/chromiumos/platform/depthcha… +* ELF binaries +* [UBoot](https://www.denx.de/wiki/U-Boot) +* [Linux kernel](https://www.kernel.org/) +* [LinuxBoot](https://www.linuxboot.org/) + diff --git a/Documentation/getting_started/comparision_coreboot_uefi.svg b/Documentation/getting_started/comparision_coreboot_uefi.svg new file mode 100644 index 0000000..3ea2fa6 --- /dev/null +++ b/Documentation/getting_started/comparision_coreboot_uefi.svg @@ -0,0 +1,176 @@ +<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.0//EN" "http://www.w3.org/TR/2001/PR-SVG-20010719/DTD/svg10.dtd"> +<svg width="55cm" height="28cm" viewBox="62 37 1088 559" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink"> + <g> + <rect style="fill: #ffffff" x="63.296" y="74.0258" width="1085.8" height="520.893"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #ffffff" x="63.296" y="74.0258" width="1085.8" height="520.893"/> + </g> + <line style="fill: none; fill-opacity:0; stroke-width: 4; stroke: #000000" x1="242.613" y1="107.463" x2="242.698" y2="492.591"/> + <g> + <line style="fill: none; fill-opacity:0; stroke-width: 4; stroke: #000000" x1="234.964" y1="477.053" x2="1135.15" y2="478.109"/> + <polyline style="fill: none; fill-opacity:0; stroke-width: 4; stroke: #000000" points="1124.61,485.597 1139.62,478.114 1124.63,470.597 "/> + </g> + <text font-size="22.5778" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="482.342" y="58.1574"> + <tspan x="482.342" y="58.1574">Platform Initialization Firmware Phases</tspan> + </text> + <text font-size="16.9333" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="98.4514" y="435.714"> + <tspan x="98.4514" y="435.714">EDK II - stages</tspan> + </text> + <text font-size="12.8" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="1073.49" y="499.998"> + <tspan x="1073.49" y="499.998">time</tspan> + </text> + <text font-size="16.9333" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="82.8266" y="330.476"> + <tspan x="82.8266" y="330.476">coreboot - stages</tspan> + </text> + <g> + <rect style="fill: #faff94" x="250.501" y="404.247" width="130.432" height="69.1471"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" x="250.501" y="404.247" width="130.432" height="69.1471"/> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="315.718" y="434.72"> + <tspan x="315.718" y="434.72">Security</tspan> + <tspan x="315.718" y="450.72">(SEC)</tspan> + </text> + </g> + <g> + <rect style="fill: #faff94" x="383.033" y="404.781" width="282.702" height="69"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" x="383.033" y="404.781" width="282.702" height="69"/> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="524.384" y="427.181"> + <tspan x="524.384" y="427.181">Pre-EFI</tspan> + <tspan x="524.384" y="443.181">Initialization Environment</tspan> + <tspan x="524.384" y="459.181">(PEI)</tspan> + </text> + </g> + <g> + <rect style="fill: #faff94" x="668.027" y="405.317" width="269.244" height="69"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" x="668.027" y="405.317" width="269.244" height="69"/> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="802.649" y="427.717"> + <tspan x="802.649" y="427.717">Driver Execution</tspan> + <tspan x="802.649" y="443.717">Environment</tspan> + <tspan x="802.649" y="459.717">(DXE)</tspan> + </text> + </g> + <g> + <rect style="fill: #faff94" x="939.541" y="405.727" width="178.75" height="69"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" x="939.541" y="405.727" width="178.75" height="69"/> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="1028.92" y="436.127"> + <tspan x="1028.92" y="436.127">Boot Device Selection</tspan> + <tspan x="1028.92" y="452.127">(BDS)</tspan> + </text> + </g> + <g> + <rect style="fill: #90c9ff" x="254.747" y="291.309" width="125.314" height="69.1471"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" x="254.747" y="291.309" width="125.314" height="69.1471"/> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="317.404" y="329.782"> + <tspan x="317.404" y="329.782">bootblock</tspan> + </text> + </g> + <g> + <rect style="fill: #90c9ff" x="476.354" y="290.735" width="89.65" height="69.1471"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" x="476.354" y="290.735" width="89.65" height="69.1471"/> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="521.179" y="329.209"> + <tspan x="521.179" y="329.209">romstage</tspan> + </text> + </g> + <g> + <rect style="fill: #90c9ff" x="382.317" y="291.011" width="92.1" height="69.1471"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" x="382.317" y="291.011" width="92.1" height="69.1471"/> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="428.367" y="321.485"> + <tspan x="428.367" y="321.485">verstage</tspan> + <tspan x="428.367" y="337.485">(optional)</tspan> + </text> + </g> + <g> + <rect style="fill: #90c9ff" x="567.853" y="290.99" width="98.5152" height="69.1471"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" x="567.853" y="290.99" width="98.5152" height="69.1471"/> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="617.11" y="321.464"> + <tspan x="617.11" y="321.464">postcar</tspan> + <tspan x="617.11" y="337.464">(x86 only)</tspan> + </text> + </g> + <g> + <rect style="fill: #90c9ff" x="667.529" y="281.527" width="168.747" height="37"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" x="667.529" y="281.527" width="168.747" height="37"/> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="751.903" y="303.927"> + <tspan x="751.903" y="303.927">ramstage</tspan> + </text> + </g> + <g> + <rect style="fill: #90c9ff" x="667.84" y="321.487" width="167.519" height="53"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" x="667.84" y="321.487" width="167.519" height="53"/> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="751.6" y="343.887"> + <tspan x="751.6" y="343.887">SMM</tspan> + <tspan x="751.6" y="359.887">(x86 only)</tspan> + </text> + </g> + <g> + <rect style="fill: #90c9ff" x="941.841" y="283.151" width="171.98" height="69.1471"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" x="941.841" y="283.151" width="171.98" height="69.1471"/> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="1027.83" y="321.624"> + <tspan x="1027.83" y="321.624">payload</tspan> + </text> + </g> + <g> + <rect style="fill: #d8e5e5" x="253.112" y="209.178" width="82.7" height="27"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" x="253.112" y="209.178" width="82.7" height="27"/> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="294.462" y="226.578"> + <tspan x="294.462" y="226.578">Assembly</tspan> + </text> + </g> + <g> + <rect style="fill: #00c800" x="318.155" y="129.267" width="283.43" height="27"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" x="318.155" y="129.267" width="283.43" height="27"/> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="459.87" y="146.667"> + <tspan x="459.87" y="146.667">Cache-As-RAM</tspan> + </text> + </g> + <g> + <rect style="fill: #ff8484" x="506.676" y="159.67" width="599.421" height="27"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" x="506.676" y="159.67" width="599.421" height="27"/> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="806.387" y="177.07"> + <tspan x="806.387" y="177.07">DRAM</tspan> + </text> + </g> + <line style="fill: none; fill-opacity:0; stroke-width: 1; stroke-dasharray: 4; stroke: #000000" x1="175.046" y1="392.926" x2="1113.82" y2="391.893"/> + <text font-size="12.7998" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="387.045" y="241.637"> + <tspan x="387.045" y="241.637"></tspan> + </text> + <g> + <rect style="fill: #ffffff" x="337.438" y="209.383" width="618.831" height="27"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" x="337.438" y="209.383" width="618.831" height="27"/> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="646.853" y="226.783"> + <tspan x="646.853" y="226.783">C</tspan> + </text> + </g> + <g> + <rect style="fill: #f6c7c7" x="667.35" y="238.912" width="170.3" height="27"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" x="667.35" y="238.912" width="170.3" height="27"/> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="752.5" y="256.312"> + <tspan x="752.5" y="256.312">ADA SPARK (x86 only)</tspan> + </text> + </g> + <text font-size="16.9333" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="84.2481" y="233.28"> + <tspan x="84.2481" y="233.28">coreboot</tspan> + <tspan x="84.2481" y="254.446">source languages</tspan> + </text> + <text font-size="16.9333" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="86.5008" y="153.786"> + <tspan x="86.5008" y="153.786">code/heap</tspan> + <tspan x="86.5008" y="174.953">memory location </tspan> + </text> + <line style="fill: none; fill-opacity:0; stroke-width: 1; stroke-dasharray: 4; stroke: #000000" x1="175.483" y1="273.35" x2="1109.07" y2="273.582"/> + <line style="fill: none; fill-opacity:0; stroke-width: 1; stroke-dasharray: 4; stroke: #000000" x1="176.24" y1="192.463" x2="1109.66" y2="192.132"/> + <g> + <rect style="fill: #90c9ff" x="838.583" y="281.963" width="100.3" height="53"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" x="838.583" y="281.963" width="100.3" height="53"/> + <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="888.733" y="304.363"> + <tspan x="888.733" y="304.363">BL31</tspan> + <tspan x="888.733" y="320.363">(ARM only)</tspan> + </text> + </g> + <text font-size="12.7998" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:normal" x="209.772" y="508.772"> + <tspan x="209.772" y="508.772">Power on</tspan> + </text> + <g> + <rect style="fill: #ffffff" x="941.939" y="210.26" width="22.4641" height="25.1384"/> + <rect style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #ffffff" x="941.939" y="210.26" width="22.4641" height="25.1384"/> + </g> + <path style="fill: none; fill-opacity:0; stroke-width: 1; stroke: #000000" d="M 955.029 209.941 C 967.678,210.1 946.349,230.772 955.598,237.021"/> +</svg> diff --git a/Documentation/getting_started/index.md b/Documentation/getting_started/index.md index 8f2a58e..52d873e 100644 --- a/Documentation/getting_started/index.md +++ b/Documentation/getting_started/index.md @@ -1,5 +1,6 @@ # Getting Started +* [coreboot architecture](architecture.md) * [Build System](build_system.md) * [Submodules](submodules.md) * [Kconfig](kconfig.md) -- To view, visit https://review.coreboot.org/c/coreboot/+/32123 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I98cb61b1d0d29ac9d03f5ef3644d51a8e14bad74 Gerrit-Change-Number: 32123 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

5 12

Change in ...coreboot[master]: mediatek/mt8183: Deselect BOOTBLOCK_CONSOLE
by Hung-Te Lin (Code Review) 11 Apr '19

11 Apr '19

Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30127 ) Change subject: mediatek/mt8183: Deselect BOOTBLOCK_CONSOLE ...................................................................... Patch Set 3: -Code-Review I think we should abandon this. Instead this can be done in chromium os overlay config, since that's why/where we need to have larger size (due to selected EC). -- To view, visit https://review.coreboot.org/c/coreboot/+/30127 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84909fc8dbba972c8293070fcf71391cd9ae0151 Gerrit-Change-Number: 30127 Gerrit-PatchSet: 3 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: You-Cheng Syu <youcheng(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 11 Apr 2019 08:40:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: mb/google/hatch: Add overridetree to hatch variant
by Shelley Chen (Code Review) 11 Apr '19

11 Apr '19

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32003 Change subject: mb/google/hatch: Add overridetree to hatch variant ...................................................................... mb/google/hatch: Add overridetree to hatch variant Mimic the serialio settings from cml_u variant of coffeelake rvp BUG=b:128347800 BRANCH=None TEST=abuild Change-Id: I6a9ec778d74cd48a2e1c79f8e669a9a6a6a9477d Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/hatch/Kconfig A src/mainboard/google/hatch/variants/hatch/overridetree.cb 2 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/32003/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 629b125..d88c795 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -38,6 +38,10 @@ string default "variants/baseboard/devicetree.cb" +config OVERRIDE_DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" if !BOARD_GOOGLE_HATCH_WHL + config DIMM_MAX int default 2 diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb new file mode 100644 index 0000000..62da635 --- /dev/null +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -0,0 +1,18 @@ +chip soc/intel/cannonlake + + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + [PchSerialIoIndexSPI0] = PchSerialIoPci, + [PchSerialIoIndexSPI1] = PchSerialIoPci, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoSkipInit, + }" + +end \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/32003 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6a9ec778d74cd48a2e1c79f8e669a9a6a6a9477d Gerrit-Change-Number: 32003 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

4 9

Change in ...coreboot[master]: sdm845: Add SPI QUP driver
by Julius Werner (Code Review) 11 Apr '19

11 Apr '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27483 ) Change subject: sdm845: Add SPI QUP driver ...................................................................... Patch Set 46: (1 comment) https://review.coreboot.org/#/c/27483/46/src/soc/qualcomm/sdm845/include/so… File src/soc/qualcomm/sdm845/include/soc/qcom_qup_se.h: https://review.coreboot.org/#/c/27483/46/src/soc/qualcomm/sdm845/include/so… PS46, Line 203: union proto_rx_trans_len { > I am not sure whether I get your suggestion correctly. […] Okay, I think I didn't read this closely enough last time... if it's TX for UART but RX for I2C and SPI, I agree a union is nice to make it more clear. -- To view, visit https://review.coreboot.org/c/coreboot/+/27483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35061727d5ccc550eaeb06caef4524bc4cf25b54 Gerrit-Change-Number: 27483 Gerrit-PatchSet: 46 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mukesh Savaliya <msavaliy(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: T Michael Turney <mturney(a)codeaurora.org> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Vin Kamath <vink(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Thu, 11 Apr 2019 00:57:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: sdm845: Port I2C driver
by Julius Werner (Code Review) 11 Apr '19

11 Apr '19

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29104 ) Change subject: sdm845: Port I2C driver ...................................................................... Patch Set 26: (2 comments) https://review.coreboot.org/#/c/29104/24/src/mainboard/google/cheza/mainboa… File src/mainboard/google/cheza/mainboard.c: https://review.coreboot.org/#/c/29104/24/src/mainboard/google/cheza/mainboa… PS24, Line 42: i2c_init(12, 400 * KHz, 1); > As per a discussion with clock team they need this enum(QUP_WRAP1_S4...) for their functionality. […] Okay, but why don't they just #include qcom_qup_se.h in clock.c and then use the enum from there? We should only need to have a single enum definition for the available QUPs and all code that cares about it can share that. I think qcom_qup_se.h would be the more natural place for that. https://review.coreboot.org/#/c/29104/24/src/soc/qualcomm/sdm845/i2c.c File src/soc/qualcomm/sdm845/i2c.c: https://review.coreboot.org/#/c/29104/24/src/soc/qualcomm/sdm845/i2c.c@101 PS24, Line 101: BITS_PER_WORD >> 4 > geni_byte_granularity is used to configure the number of protocol words in each FIFO entry. […] Okay. I think it's fine to hardcode a single BITS_PER_WORD and the PACK_VECTORs for that (just maybe add a comment where it is defined to clarify that the two depend on each other). However, since you're writing it programmatically here anyway, can you please write it as (log2(BITS_PER_WORD) - 3)? That should come out to the same numbers for 16 and 32 but represents it more correctly (e.g. it will also yield the right value for 8). -- To view, visit https://review.coreboot.org/c/coreboot/+/29104 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb76564d8a11427423dd14d8ba7c8c7d500ef346 Gerrit-Change-Number: 29104 Gerrit-PatchSet: 26 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: T Michael Turney <mturney(a)codeaurora.org> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 11 Apr 2019 00:54:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Akash Asthana <akashast(a)qualcomm.corp-partner.google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: mb/GA-Z170N-WIFI: Add mainboard
by Marius Genheimer (Code Review) 10 Apr '19

10 Apr '19

Marius Genheimer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32274 Change subject: mb/GA-Z170N-WIFI: Add mainboard ...................................................................... mb/GA-Z170N-WIFI: Add mainboard Change-Id: I0ac13e8f5ac800d1c7c21b3eab15392b9eae22fc Signed-off-by: Marius Genheimer <mail(a)f0wl.cc> --- A src/mainboard/gigabyte/ga-z170n-wifi/Kconfig A src/mainboard/gigabyte/ga-z170n-wifi/Kconfig.name A src/mainboard/gigabyte/ga-z170n-wifi/Makefile.inc A src/mainboard/gigabyte/ga-z170n-wifi/board_info.txt A src/mainboard/gigabyte/ga-z170n-wifi/data.vbt A src/mainboard/gigabyte/ga-z170n-wifi/devicetree.cb A src/mainboard/gigabyte/ga-z170n-wifi/pei_data.c 7 files changed, 152 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/32274/1 diff --git a/src/mainboard/gigabyte/ga-z170n-wifi/Kconfig b/src/mainboard/gigabyte/ga-z170n-wifi/Kconfig new file mode 100644 index 0000000..fb21b5e --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170n-wifi/Kconfig @@ -0,0 +1,42 @@ +if BOARD_GIGABYTE_Z170N_WIFI + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select USE_BLOBS + select ADD_FSP_BINARIES + select FSP_USE_REPO + select INTEL_GMA_ADD_VBT + select CONSOLE_POST + select ONBOARD_VGA_IS_PRIMARY + select HAVE_ACPI_TABLES + select SKYLAKE_SOC_PCH_H + select SOC_INTEL_SKYLAKE + select MAINBOARD_USES_FSP2_0 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAINBOARD_DIR + string + default "gigabyte/ga-z170n-wifi" + +config MAINBOARD_PART_NUMBER + string + default "Z170N-WIFI" + +config MAINBOARD_FAMILY + string + default "Gigabyte_Z170" + +config MAX_CPUS + int + default 8 + +config DIMM_SPD_SIZE + int + default 512 #DDR4 + +endif diff --git a/src/mainboard/gigabyte/ga-z170n-wifi/Kconfig.name b/src/mainboard/gigabyte/ga-z170n-wifi/Kconfig.name new file mode 100644 index 0000000..dbabce7 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170n-wifi/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GIGABYTE_Z170N_WIFI + bool "GA-Z170N-WIFI" diff --git a/src/mainboard/gigabyte/ga-z170n-wifi/Makefile.inc b/src/mainboard/gigabyte/ga-z170n-wifi/Makefile.inc new file mode 100644 index 0000000..63889af --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170n-wifi/Makefile.inc @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2013 Google Inc. +## Copyright (C) 2016 Intel Corporation. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +subdirs-y += spd + +bootblock-y += bootblock.c +romstage-y += pei_data.c + +ramstage-y += ramstage.c diff --git a/src/mainboard/gigabyte/ga-z170n-wifi/board_info.txt b/src/mainboard/gigabyte/ga-z170n-wifi/board_info.txt new file mode 100644 index 0000000..d3295d9 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170n-wifi/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Saddle Brook Skylake Reference Board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/gigabyte/ga-z170n-wifi/data.vbt b/src/mainboard/gigabyte/ga-z170n-wifi/data.vbt new file mode 100644 index 0000000..45e381c --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170n-wifi/data.vbt Binary files differ diff --git a/src/mainboard/gigabyte/ga-z170n-wifi/devicetree.cb b/src/mainboard/gigabyte/ga-z170n-wifi/devicetree.cb new file mode 100644 index 0000000..717c994 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170n-wifi/devicetree.cb @@ -0,0 +1,53 @@ +chip soc/intel/skylake + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # Thermal Subsystem + device pci 15.0 on end # I2C #0 + device pci 15.1 on end # I2C #1 + device pci 15.2 on end # I2C #2 + device pci 15.3 on end # I2C #3 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off end # Management Engine Interface 3 + device pci 17.0 on end # SATA + device pci 19.0 on end # UART #2 + device pci 19.1 on end # I2C #5 + device pci 19.2 on end # I2C #4 + device pci 1c.0 on end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 off end # PCI Express Port 8 + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 off end # PCI Express Port 10 + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1e.0 on end # UART #0 + device pci 1e.1 on end # UART #1 + device pci 1e.2 on end # GSPI #0 + device pci 1e.3 on end # GSPI #1 + device pci 1e.4 off end # eMMC + device pci 1e.5 off end # SDIO + device pci 1e.6 off end # SDCard + device pci 1f.0 on + end # LPC Interface + device pci 1f.1 on end # P2SB + device pci 1f.2 on end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 on end # GbE + end +end diff --git a/src/mainboard/gigabyte/ga-z170n-wifi/pei_data.c b/src/mainboard/gigabyte/ga-z170n-wifi/pei_data.c new file mode 100644 index 0000000..ac4ce95 --- /dev/null +++ b/src/mainboard/gigabyte/ga-z170n-wifi/pei_data.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> +#include "spd/spd.h" + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + mainboard_fill_dq_map_data(&pei_data->dq_map); + mainboard_fill_dqs_map_data(&pei_data->dqs_map); + mainboard_fill_rcomp_res_data(&pei_data->RcompResistor); + mainboard_fill_rcomp_strength_data(&pei_data->RcompTarget); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ac13e8f5ac800d1c7c21b3eab15392b9eae22fc Gerrit-Change-Number: 32274 Gerrit-PatchSet: 1 Gerrit-Owner: Marius Genheimer Gerrit-MessageType: newchange

1 2

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2019