coreboot-gerrit April 2019

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Change in ...coreboot[master]: [WIP]mainboard/lenovo/t410: Add new port
by build bot (Jenkins) (Code Review) 09 Apr '19

09 Apr '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/11791 ) Change subject: [WIP]mainboard/lenovo/t410: Add new port ...................................................................... Patch Set 13: (10 comments) https://review.coreboot.org/#/c/11791/13/src/mainboard/lenovo/t410/romstage… File src/mainboard/lenovo/t410/romstage.c: https://review.coreboot.org/#/c/11791/13/src/mainboard/lenovo/t410/romstage… PS13, Line 65: (pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1); line over 80 characters https://review.coreboot.org/#/c/11791/13/src/mainboard/lenovo/t410/romstage… PS13, Line 141: unsigned i; Prefer 'unsigned int' to bare use of 'unsigned' https://review.coreboot.org/#/c/11791/13/src/mainboard/lenovo/t410/romstage… PS13, Line 271: pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) | 2); line over 80 characters https://review.coreboot.org/#/c/11791/13/src/mainboard/lenovo/t410/smihandl… File src/mainboard/lenovo/t410/smihandler.c: https://review.coreboot.org/#/c/11791/13/src/mainboard/lenovo/t410/smihandl… PS13, Line 52: switch (smif) { switch and case should be at the same indent https://review.coreboot.org/#/c/11791/13/src/mainboard/lenovo/t410/smihandl… PS13, Line 55: udelay(250000); long udelay - prefer mdelay; see arch/arm/include/asm/delay.h https://review.coreboot.org/#/c/11791/13/src/mainboard/lenovo/t410/smihandl… PS13, Line 81: if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0) do not use assignment in if condition https://review.coreboot.org/#/c/11791/13/src/mainboard/lenovo/t410/smihandl… PS13, Line 89: if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10) do not use assignment in if condition https://review.coreboot.org/#/c/11791/13/src/mainboard/lenovo/t410/smihandl… PS13, Line 105: switch (event) { switch and case should be at the same indent https://review.coreboot.org/#/c/11791/13/src/mainboard/lenovo/t410/smihandl… PS13, Line 142: switch (data) { switch and case should be at the same indent https://review.coreboot.org/#/c/11791/13/src/mainboard/lenovo/t410/smihandl… PS13, Line 166: /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/11791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Gerrit-Change-Number: 11791 Gerrit-PatchSet: 13 Gerrit-Owner: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eloy Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Okashi Odayakana <brianblevins316(a)gmail.com> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Comment-Date: Tue, 09 Apr 2019 18:05:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: [WIP]mainboard/lenovo/t410: Add new port
by Peter Lemenkov (Code Review) 09 Apr '19

09 Apr '19

Peter Lemenkov has uploaded a new patch set (#13) to the change originally created by Nicolas Reinecke. ( https://review.coreboot.org/c/coreboot/+/11791 ) Change subject: [WIP]mainboard/lenovo/t410: Add new port ...................................................................... [WIP]mainboard/lenovo/t410: Add new port The port is based on the x201 / t410s. 2537-vg5 / i5, no discrete gpu Tested and working: * Native raminit * Native gfxinit * Booting Seabios 1.11.1 * Booting from EHCI * Running GNU/Linux 4.13.5 * No errors in dmesg * EHCI debug on the devices left side, bottom-right * Keyboard * Fn keys (Mute, Volume, Mic) * Touchpad * TPM * Ethernet * Wifi * Sound * USB Testing in progress. Untested: * VGA * Displayport * Ethernet Bugs: * Linux hangs in 2 out of 3 attempts when booting from USB * S3 resume is broken. TODOs: * Hide internal PCI devices Depends on: 1. Change-Id: Idd4986f39f21cb53cb019d0893d40fed94c6505b Details for flashing externally: 1. Disconnect all power 2. Connect the external flasher 3. Connect the power cord (This fixes internal power control) 4. Remove the power cord Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> --- A src/mainboard/lenovo/t410/Kconfig A src/mainboard/lenovo/t410/Kconfig.name A src/mainboard/lenovo/t410/Makefile.inc A src/mainboard/lenovo/t410/acpi/dock.asl A src/mainboard/lenovo/t410/acpi/ec.asl A src/mainboard/lenovo/t410/acpi/gpe.asl A src/mainboard/lenovo/t410/acpi/platform.asl A src/mainboard/lenovo/t410/acpi/superio.asl A src/mainboard/lenovo/t410/acpi_tables.c A src/mainboard/lenovo/t410/board_info.txt A src/mainboard/lenovo/t410/cmos.default A src/mainboard/lenovo/t410/cmos.layout A src/mainboard/lenovo/t410/devicetree.cb A src/mainboard/lenovo/t410/dock.c A src/mainboard/lenovo/t410/dock.h A src/mainboard/lenovo/t410/dsdt.asl A src/mainboard/lenovo/t410/gpio.c A src/mainboard/lenovo/t410/hda_verb.c A src/mainboard/lenovo/t410/mainboard.c A src/mainboard/lenovo/t410/romstage.c A src/mainboard/lenovo/t410/smi.h A src/mainboard/lenovo/t410/smihandler.c A src/mainboard/lenovo/t410/thermal.h 23 files changed, 1,976 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/11791/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/11791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id9d872e643dd242e925bfb46d18076e6ad100995 Gerrit-Change-Number: 11791 Gerrit-PatchSet: 13 Gerrit-Owner: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nicolas Reinecke <nr(a)das-labor.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eloy Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Okashi Odayakana <brianblevins316(a)gmail.com> Gerrit-CC: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: payload/libpayload: This is a fixe for potential NULL pointer derefer...
by Francois Toguo Fotso (Code Review) 09 Apr '19

09 Apr '19

Francois Toguo Fotso has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32083 Change subject: payload/libpayload: This is a fixe for potential NULL pointer dereferences ...................................................................... payload/libpayload: This is a fixe for potential NULL pointer dereferences These potential issues are flagged in Klockwork reports BUG=NONE TEST=Boot to OS on GLK Sparky Signed-off-by: Francois Toguo <francois.toguo.fotso(a)intel.com> Change-Id: I9d4636f0429de829e746909492c2f543026a02ac --- M payloads/libpayload/drivers/usb/ehci.c M payloads/libpayload/drivers/usb/ohci.c M payloads/libpayload/drivers/usb/uhci.c 3 files changed, 76 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/32083/1 diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index 30cf191..61a39a7 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -634,6 +634,8 @@ /* create #reqcount transfer descriptors (qTDs) */ intrq->head = (intr_qtd_t *)dma_memalign(64, sizeof(intr_qtd_t)); + if (!intrq->head) + fatal("Not enough memory to create #reqcount transfer descriptors. \n"); intr_qtd_t *cur_td = intrq->head; for (i = 0; i < reqcount; ++i) { fill_intr_queue_td(intrq, cur_td, data); @@ -642,6 +644,11 @@ /* create one more qTD */ intr_qtd_t *const next_td = (intr_qtd_t *)dma_memalign(64, sizeof(intr_qtd_t)); + if (!next_td) { + usb_debug("Not enough memory to add transfer descriptor. \n"); + free(next_td); + continue; + } cur_td->td.next_qtd = virt_to_phys(&next_td->td); cur_td->next = next_td; cur_td = next_td; @@ -651,6 +658,8 @@ /* create spare qTD */ intrq->spare = (intr_qtd_t *)dma_memalign(64, sizeof(intr_qtd_t)); + if (!intrq->spare) + fatal("Not enough memory to create spare transfer descriptors.\n"); intrq->spare->data = data; /* initialize QH */ @@ -824,15 +833,20 @@ * and doesn't violate the standard. */ EHCI_INST(controller)->dummy_qh = (ehci_qh_t *)dma_memalign(64, sizeof(ehci_qh_t)); - memset((void *)EHCI_INST(controller)->dummy_qh, 0, - sizeof(*EHCI_INST(controller)->dummy_qh)); - EHCI_INST(controller)->dummy_qh->horiz_link_ptr = QH_TERMINATE; - EHCI_INST(controller)->dummy_qh->td.next_qtd = QH_TERMINATE; - EHCI_INST(controller)->dummy_qh->td.alt_next_qtd = QH_TERMINATE; - for (i = 0; i < 1024; ++i) - periodic_list[i] = virt_to_phys(EHCI_INST(controller)->dummy_qh) - | PS_TYPE_QH; - + if (EHCI_INST(controller)->dummy_qh) { + memset((void *)EHCI_INST(controller)->dummy_qh, 0, + sizeof(*EHCI_INST(controller)->dummy_qh)); + EHCI_INST(controller)->dummy_qh->horiz_link_ptr = QH_TERMINATE; + EHCI_INST(controller)->dummy_qh->td.next_qtd = QH_TERMINATE; + EHCI_INST(controller)->dummy_qh->td.alt_next_qtd = QH_TERMINATE; + for (i = 0; i < 1024; ++i) + periodic_list[i] = virt_to_phys(EHCI_INST(controller)->dummy_qh) + | PS_TYPE_QH; + } else { + usb_debug("Not enough DMA memory for EHCI dummy QH!\n"); + free(EHCI_INST(controller)->dummy_qh); + } + /* Make sure periodic schedule is disabled */ ehci_set_periodic_schedule(EHCI_INST(controller), 0); /* Set periodic frame list pointer */ diff --git a/payloads/libpayload/drivers/usb/ohci.c b/payloads/libpayload/drivers/usb/ohci.c index 1964689..045bb7a 100644 --- a/payloads/libpayload/drivers/usb/ohci.c +++ b/payloads/libpayload/drivers/usb/ohci.c @@ -212,6 +212,8 @@ udelay (10); /* at most 10us for reset to complete. State must be set to Operational within 2ms (5.1.1.4) */ OHCI_INST (controller)->opreg->HcFmInterval = interval; OHCI_INST (controller)->hcca = dma_memalign(256, 256); + if (!OHCI_INST(controller)->hcca) + fatal("Not enough DMA memory for OHCI hcca.\n"); memset((void*)OHCI_INST (controller)->hcca, 0, 256); if (dma_initialized()) { @@ -223,6 +225,8 @@ /* Initialize interrupt table. */ u32 *const intr_table = OHCI_INST(controller)->hcca->HccaInterruptTable; ed_t *const periodic_ed = dma_memalign(sizeof(ed_t), sizeof(ed_t)); + if (!periodic_ed) + fatal("Not enough DMA memory for OHCI interrupt table .\n"); memset((void *)periodic_ed, 0, sizeof(*periodic_ed)); for (i = 0; i < 32; ++i) intr_table[i] = virt_to_phys(periodic_ed); @@ -378,6 +382,8 @@ /* First TD. */ td_t *const first_td = (td_t *)dma_memalign(sizeof(td_t), sizeof(td_t)); + if (!first_td) + fatal("Not enough DMA memory for OHCI first TD in buffer.\n"); memset((void *)first_td, 0, sizeof(*first_td)); cur = first_td; @@ -392,6 +398,8 @@ while (pages > 0) { /* One more TD. */ td_t *const next = (td_t *)dma_memalign(sizeof(td_t), sizeof(td_t)); + if (!next) + fatal("Not enough DMA memory for OHCI new page.\n"); memset((void *)next, 0, sizeof(*next)); /* Linked to the previous. */ cur->next_td = virt_to_phys(next); @@ -426,6 +434,8 @@ /* One more TD. */ td_t *const next_td = (td_t *)dma_memalign(sizeof(td_t), sizeof(td_t)); + if (!next_td) + fatal("Not enough DMA memory for OHCI additional TD.\n"); memset((void *)next_td, 0, sizeof(*next_td)); /* Linked to the previous. */ cur->next_td = virt_to_phys(next_td); @@ -441,12 +451,18 @@ /* Final dummy TD. */ td_t *const final_td = (td_t *)dma_memalign(sizeof(td_t), sizeof(td_t)); - memset((void *)final_td, 0, sizeof(*final_td)); - /* Linked to the previous. */ - cur->next_td = virt_to_phys(final_td); - + if (final_td) { + memset((void *)final_td, 0, sizeof(*final_td)); + /* Linked to the previous. */ + cur->next_td = virt_to_phys(final_td); + } else { + usb_debug("Not enough DMA memory for OHCI dummy TD!\n"); + free(final_td); + } /* Data structures */ ed_t *head = dma_memalign(sizeof(ed_t), sizeof(ed_t)); + if (!head) + fatal("Not enough DMA memory for OHCI data structures.\n"); memset((void*)head, 0, sizeof(*head)); head->config = (dev->address << ED_FUNC_SHIFT) | (0 << ED_EP_SHIFT) | @@ -519,6 +535,8 @@ /* First TD. */ td_t *const first_td = (td_t *)dma_memalign(sizeof(td_t), sizeof(td_t)); + if (!first_td) + fatal("Not enough DMA memory for OHCI first TD of bulk transfer.\n"); memset((void *)first_td, 0, sizeof(*first_td)); cur = next = first_td; @@ -557,6 +575,10 @@ } /* One more TD. */ next = (td_t *)dma_memalign(sizeof(td_t), sizeof(td_t)); + if (!next) { + usb_debug("Not enough DMA memory for OHCI addition TD in bulk transfer.\n"); + break; + } memset((void *)next, 0, sizeof(*next)); /* Linked to the previous. */ cur->next_td = virt_to_phys(next); @@ -569,6 +591,8 @@ /* Data structures */ ed_t *head = dma_memalign(sizeof(ed_t), sizeof(ed_t)); + if (!head) + fatal("Not enough DMA memory for OHCI bulk transfer's head.\n"); memset((void*)head, 0, sizeof(*head)); head->config = (ep->dev->address << ED_FUNC_SHIFT) | ((ep->endpoint & 0xf) << ED_EP_SHIFT) | @@ -665,6 +689,11 @@ intr_queue_t *const intrq = (intr_queue_t *)dma_memalign(sizeof(intrq->ed), sizeof(*intrq)); + if (!intrq) { + usb_debug("Not enough DMA memory for intr queue \n"); + free(final_td); + return NULL; + } memset(intrq, 0, sizeof(*intrq)); intrq->data = (u8 *)dma_malloc(reqcount * reqsize); intrq->reqsize = reqsize; @@ -674,6 +703,11 @@ u8 *cur_data = intrq->data; for (i = 0; i < reqcount; ++i) { intrq_td_t *const td = dma_memalign(sizeof(td->td), sizeof(*td)); + if (!td) { + usb_debug("Not enough memory to add transfer descriptor. \n"); + free(td); + continue; + } ++intrq->remaining_tds; ohci_fill_intrq_td(td, intrq, cur_data); cur_data += reqsize; @@ -686,12 +720,17 @@ /* Create last, dummy TD. */ intrq_td_t *dummy_td = dma_memalign(sizeof(dummy_td->td), sizeof(*dummy_td)); - memset(dummy_td, 0, sizeof(*dummy_td)); - dummy_td->intrq = intrq; - if (last_td) - last_td->td.next_td = virt_to_phys(&dummy_td->td); - last_td = dummy_td; - + if (dummy_td) { + memset(dummy_td, 0, sizeof(*dummy_td)); + dummy_td->intrq = intrq; + if (last_td) + last_td->td.next_td = virt_to_phys(&dummy_td->td); + last_td = dummy_td; + } else { + usb_debug("Not enough memory to add dummy TD. \n"); + free(dummy_td); + } + /* Initialize ED. */ intrq->ed.config = (ep->dev->address << ED_FUNC_SHIFT) | ((ep->endpoint & 0xf) << ED_EP_SHIFT) | diff --git a/payloads/libpayload/drivers/usb/uhci.c b/payloads/libpayload/drivers/usb/uhci.c index 70071eb..e62fd25 100644 --- a/payloads/libpayload/drivers/usb/uhci.c +++ b/payloads/libpayload/drivers/usb/uhci.c @@ -317,6 +317,8 @@ unsigned short req = ((unsigned short *) devreq)[0]; int i; td_t *tds = memalign (16, sizeof (td_t) * count); + if (!tds) + fatal("Not enough memory for uhci control.\n"); memset (tds, 0, sizeof (td_t) * count); count--; /* to compensate for 0-indexed array */ for (i = 0; i < count; i++) { @@ -386,6 +388,8 @@ if (numpackets == 0) return 0; td_t *tds = memalign (16, sizeof (td_t) * numpackets); + if (!tds) + fatal("Not enough memory for packets scheduling.\n"); memset (tds, 0, sizeof (td_t) * numpackets); int i; for (i = 0; i < numpackets; i++) { -- To view, visit https://review.coreboot.org/c/coreboot/+/32083 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d4636f0429de829e746909492c2f543026a02ac Gerrit-Change-Number: 32083 Gerrit-PatchSet: 1 Gerrit-Owner: Francois Toguo Fotso <francois.toguo.fotso(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/sandybridge: Set uninitialized run length
by Jacob Garber (Code Review) 09 Apr '19

09 Apr '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32249 Change subject: nb/intel/sandybridge: Set uninitialized run length ...................................................................... nb/intel/sandybridge: Set uninitialized run length If the entire array is zero, then the length of the longest zero run is the length of the array itself. Found-by: Coverity Scan, CID 1229715 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Change-Id: Id23292087b14182448d70117915fb044e9c579f7 --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/32249/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 55df03b..5ffb0d8 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1142,6 +1142,7 @@ ret.middle = sz / 2; ret.start = 0; ret.end = sz; + ret.length = sz; ret.all = 1; return ret; } -- To view, visit https://review.coreboot.org/c/coreboot/+/32249 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id23292087b14182448d70117915fb044e9c579f7 Gerrit-Change-Number: 32249 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: google/kukui: Configure AP_IN_SLEEP_L correctly.
by You-Cheng Syu (Code Review) 09 Apr '19

09 Apr '19

You-Cheng Syu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32120 Change subject: google/kukui: Configure AP_IN_SLEEP_L correctly. ...................................................................... google/kukui: Configure AP_IN_SLEEP_L correctly. This pin should be set to its alternative function SRCLKENA0 instead of GPIO, so that SPM can control it. BUG=b:113367227 BRANCH=none TEST=1. Boot. Run 'powerinfo' in EC console and see power state in S0. 2. Run 'powerd_dbus_suspend --wakeup_timeout=10', and then run 'powerinfo' in EC console and see power state in S3. 3. Wait until AP resume. 4. Run 'powerinfo' in EC console and see power state back to S0. Change-Id: I0a7e34f95381dec17eb6d166d6552c12e021bd9a Signed-off-by: You-Cheng Syu <youcheng(a)google.com> --- M src/mainboard/google/kukui/early_init.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/32120/1 diff --git a/src/mainboard/google/kukui/early_init.c b/src/mainboard/google/kukui/early_init.c index a16a335..1193bb3 100644 --- a/src/mainboard/google/kukui/early_init.c +++ b/src/mainboard/google/kukui/early_init.c @@ -32,8 +32,7 @@ setup_chromeos_gpios(); - /* Declare we are in S0 */ - gpio_output(AP_IN_SLEEP_L, 1); + gpio_set_mode(AP_IN_SLEEP_L, PAD_SRCLKENA0_FUNC_SRCLKENA0); mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz); gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING); -- To view, visit https://review.coreboot.org/c/coreboot/+/32120 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a7e34f95381dec17eb6d166d6552c12e021bd9a Gerrit-Change-Number: 32120 Gerrit-PatchSet: 1 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Support 16MiB fmap
by Philip Chen (Code Review) 09 Apr '19

09 Apr '19

Philip Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32219 Change subject: mb/google/hatch: Support 16MiB fmap ...................................................................... mb/google/hatch: Support 16MiB fmap Add an config and a fmd file for 16MiB fmap, so that we can support both 16MiB / 32MiB SPI flashroms. BUG=b:129464811 TEST=build hatch firmware image with 16MiB fmap and verify fmap is updated by 'fuility dump_fmap' Change-Id: Ifc0103c7fd0d99439f40a31d23422401a6dce826 Signed-off-by: Philip Chen <philipchen(a)google.com> --- M src/mainboard/google/hatch/Kconfig A src/mainboard/google/hatch/chromeos-16MiB.fmd 2 files changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/32219/1 diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig index 041ac2d..dd400b9 100644 --- a/src/mainboard/google/hatch/Kconfig +++ b/src/mainboard/google/hatch/Kconfig @@ -24,6 +24,11 @@ if BOARD_GOOGLE_BASEBOARD_HATCH +config HATCH_HAS_16MB_FLASH + bool "Build for a board with a 16MiB SPI flash" + default n if BOARD_GOOGLE_HATCH_WHL || BOARD_GOOGLE_HATCH + default y + config CHROMEOS bool default y @@ -54,6 +59,11 @@ config UART_FOR_CONSOLE default 0 +config FMDFILE + string + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-16MiB.fmd" if HATCH_HAS_16MB_FLASH + default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" + config GBB_HWID string depends on CHROMEOS diff --git a/src/mainboard/google/hatch/chromeos-16MiB.fmd b/src/mainboard/google/hatch/chromeos-16MiB.fmd new file mode 100644 index 0000000..1594ab3 --- /dev/null +++ b/src/mainboard/google/hatch/chromeos-16MiB.fmd @@ -0,0 +1,42 @@ +FLASH@0xff000000 0x1000000 { + SI_ALL@0x0 0x400000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x3ff000 + } + SI_BIOS@0x400000 0xc00000 { + RW_SECTION_A@0x0 0x380000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x36ffc0 + RW_FWID_A@0x37ffc0 0x40 + } + RW_SECTION_B@0x380000 0x380000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x36ffc0 + RW_FWID_B@0x37ffc0 0x40 + } + RW_MISC@0x700000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x20000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + } + RW_ELOG(PRESERVE)@0x20000 0x4000 + RW_SHARED@0x24000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD(PRESERVE)@0x28000 0x2000 + RW_NVRAM(PRESERVE)@0x2a000 0x6000 + } + RW_LEGACY(CBFS)@0x730000 0xd0000 + WP_RO@0x800000 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x3fc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0xef000 + COREBOOT(CBFS)@0xf0000 0x30c000 + } + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/32219 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc0103c7fd0d99439f40a31d23422401a6dce826 Gerrit-Change-Number: 32219 Gerrit-PatchSet: 1 Gerrit-Owner: Philip Chen <philipchen(a)google.com> Gerrit-MessageType: newchange

4 11

Change in ...coreboot[master]: arch/x86/smbios: Reference type 7
by Patrick Rudolph (Code Review) 09 Apr '19

09 Apr '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32132 Change subject: arch/x86/smbios: Reference type 7 ...................................................................... arch/x86/smbios: Reference type 7 Fill in the handle to cache entries of type 7 in the type 4 structure. Change-Id: Idf876b0c21c65f72a945d26c5898074b140763f8 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/smbios.c 1 file changed, 24 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/32132/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index be024c16..68fca21 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -694,10 +694,12 @@ * @param current Pointer to memory address to write the tables to * @param handle Pointer to the handle for the tables * @param max_struct_size Pointer to maximum struct size + * @param type4 Pointer to SMBIOS type 4 structure */ static int smbios_write_type7_cache_parameters(unsigned long *current, int *handle, - int *max_struct_size) + int *max_struct_size, + struct smbios_type4 *type4) { struct cpuid_result res; unsigned int cnt = 0; @@ -730,6 +732,7 @@ while (1) { enum smbios_cache_associativity associativity; enum smbios_cache_type type; + const int h = (*handle)++; res = cpuid_ext(leaf, cnt++); @@ -766,9 +769,23 @@ else associativity = smbios_cache_associativity(assoc); - update_max(len, *max_struct_size, smbios_write_type7(current, - *handle++, level, SMBIOS_CACHE_SRAM_TYPE_UNKNOWN, - associativity, type, cache_size, cache_size)); + update_max(len, *max_struct_size, smbios_write_type7(current, h, + level, SMBIOS_CACHE_SRAM_TYPE_UNKNOWN, associativity, + type, cache_size, cache_size)); + + if (type4) { + switch (level) { + case 1: + type4->l1_cache_handle = h; + break; + case 2: + type4->l2_cache_handle = h; + break; + case 3: + type4->l3_cache_handle = h; + break; + } + } }; return len; @@ -945,10 +962,12 @@ handle++; update_max(len, max_struct_size, smbios_write_type3(&current, handle++)); + + struct smbios_type4 *type4 = (struct smbios_type4 *)current; update_max(len, max_struct_size, smbios_write_type4(&current, handle++)); smbios_write_type7_cache_parameters(&current, &handle, - &max_struct_size); + &max_struct_size, type4); update_max(len, max_struct_size, smbios_write_type11(&current, &handle)); if (CONFIG(ELOG)) -- To view, visit https://review.coreboot.org/c/coreboot/+/32132 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf876b0c21c65f72a945d26c5898074b140763f8 Gerrit-Change-Number: 32132 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

5 8

Change in ...coreboot[master]: arch/x86/smbios: Add type 7
by Patrick Rudolph (Code Review) 09 Apr '19

09 Apr '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32131 Change subject: arch/x86/smbios: Add type 7 ...................................................................... arch/x86/smbios: Add type 7 The SMBIOS spec requires type 7 to be present. Add the type 7 fields and enums for SMBIOS 3.1+ and fill it with the "Deterministic Cache Parameters" as available on Intel and AMD. As CPUID only provides partial information on caches, some fields are set to unknown. The following fields are supported: * Cache Level * Cache Size * Cache Type * Cache Ways of Associativity Change-Id: I80ed25b8f2c7b425136b2f0c755324a8f5d1636d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/smbios.c M src/include/smbios.h 2 files changed, 256 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/32131/1 diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 8cb59df..be024c16 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -34,6 +34,14 @@ #include <vendorcode/google/chromeos/gnvs.h> #endif +#define update_max(len, max_len, stmt) \ + do { \ + int tmp = stmt; \ + \ + max_len = MAX(max_len, tmp); \ + len += tmp; \ + } while (0) + static u8 smbios_checksum(u8 *p, u32 length) { u8 ret = 0; @@ -580,6 +588,192 @@ return len; } +/* + * Write SMBIOS type 7. + * Fill in some fields with constant values, as gathering the information + * from CPUID is impossible. + */ +static int +smbios_write_type7(unsigned long *current, + const int handle, + const u8 level, + const u8 sram_type, + const enum smbios_cache_associativity associativity, + const enum smbios_cache_type type, + const size_t max_cache_size, + const size_t cache_size) +{ + struct smbios_type7 *t = (struct smbios_type7 *)*current; + int len = sizeof(struct smbios_type7); + static size_t cnt = 0; + char buf[8]; + + memset(t, 0, sizeof(struct smbios_type7)); + t->type = SMBIOS_CACHE_INFORMATION; + t->handle = handle; + t->length = len - 2; + + snprintf(buf, sizeof(buf), "CACHE%x", cnt++); + t->socket_designation = smbios_add_string(t->eos, buf); + + /* Cache level, Internal, Enabled, Mode Varies with Memory Address */ + t->cache_configuration = ((level & 7) << 0) | (1 << 7) | (2 << 8); + + if (max_cache_size < (32 * KiB)) { + t->max_cache_size = max_cache_size; + t->max_cache_size2 = t->max_cache_size; + } else if (max_cache_size < (0x7fff * 64 * KiB)) { + t->max_cache_size = (max_cache_size / (64 * KiB)) | (1 << 15); + t->max_cache_size2 = (max_cache_size / (64 * KiB)) | (1 << 31); + } else { + t->max_cache_size = 0xffff; + t->max_cache_size2 = (max_cache_size / (64 * KiB)) | (1 << 31); + } + + if (cache_size < (32 * KiB)) { + t->installed_size = cache_size; + t->installed_size2 = t->installed_size; + } else if (cache_size < (0x7fff * 64 * KiB)) { + t->installed_size = (cache_size / (64 * KiB)) | (1 << 15); + t->installed_size2 = (cache_size / (64 * KiB)) | (1 << 31); + } else { + t->installed_size = 0xffff; + t->installed_size2 = (cache_size / (64 * KiB)) | (1 << 31); + } + + t->associativity = associativity; + t->supported_sram_type = sram_type; + t->cache_speed = 0; //Unknown + t->error_correction_type = SMBIOS_CACHE_ERROR_CORRECTION_UNKNOWN; + t->system_cache_type = type; + + len = t->length + smbios_string_table_len(t->eos); + *current += len; + return len; +} + +/* Convert the associativity as integer to the SMBIOS enum if available */ +static enum smbios_cache_associativity +smbios_cache_associativity(const u8 num) +{ + switch (num) { + case 1: + return SMBIOS_CACHE_ASSOCIATIVITY_DIRECT; + case 2: + return SMBIOS_CACHE_ASSOCIATIVITY_2WAY; + case 4: + return SMBIOS_CACHE_ASSOCIATIVITY_4WAY; + case 8: + return SMBIOS_CACHE_ASSOCIATIVITY_8WAY; + case 12: + return SMBIOS_CACHE_ASSOCIATIVITY_12WAY; + case 16: + return SMBIOS_CACHE_ASSOCIATIVITY_16WAY; + case 20: + return SMBIOS_CACHE_ASSOCIATIVITY_20WAY; + case 24: + return SMBIOS_CACHE_ASSOCIATIVITY_24WAY; + case 32: + return SMBIOS_CACHE_ASSOCIATIVITY_32WAY; + case 48: + return SMBIOS_CACHE_ASSOCIATIVITY_48WAY; + case 64: + return SMBIOS_CACHE_ASSOCIATIVITY_64WAY; + case 0xff: + return SMBIOS_CACHE_ASSOCIATIVITY_FULL; + default: + return SMBIOS_CACHE_ASSOCIATIVITY_UNKNOWN; + }; + +} + +/* + * Parse the "Deterministic Cache Parameters" as provided by Intel in + * leaf 4 or AMD in extended leaf 0x8000001d. + * + * @param current Pointer to memory address to write the tables to + * @param handle Pointer to the handle for the tables + * @param max_struct_size Pointer to maximum struct size + */ +static int smbios_write_type7_cache_parameters(unsigned long *current, + int *handle, + int *max_struct_size) +{ + struct cpuid_result res; + unsigned int cnt = 0; + int len = 0; + u32 leaf; + + if (!cpu_have_cpuid()) + return len; + + if (cpu_is_intel()) { + res = cpuid(0); + if (res.eax < 4) + return len; + leaf = 4; + } else if (cpu_is_amd()) { + res = cpuid(0x80000000); + if (res.eax < 0x80000001) + return len; + + res = cpuid(0x80000001); + if (!(res.ecx & (1 << 22))) + return len; + + leaf = 0x8000001d; + } else { + printk(BIOS_DEBUG, "SMBIOS: Unknown CPU\n"); + return len; + } + + while (1) { + enum smbios_cache_associativity associativity; + enum smbios_cache_type type; + + res = cpuid_ext(leaf, cnt++); + + const size_t cache_type = res.eax & 0x1f; + const size_t level = (res.eax >> 5) & 0x7; + const size_t assoc = ((res.ebx >> 22) & 0x3ff) + 1; + const size_t partitions = ((res.ebx >> 12) & 0x3ff) + 1; + const size_t cache_line_size = ((res.ebx >> 0) & 0xfff) + 1; + const size_t number_of_sets = res.ecx + 1; + const size_t cache_size = assoc * partitions * cache_line_size * + number_of_sets; + + if (!cache_type) + /* No more caches in the system */ + break; + + switch (cache_type) { + case 1: + type = SMBIOS_CACHE_TYPE_DATA; + break; + case 2: + type = SMBIOS_CACHE_TYPE_INSTRUCTION; + break; + case 3: + type = SMBIOS_CACHE_TYPE_UNIFIED; + break; + default: + type = SMBIOS_CACHE_TYPE_UNKNOWN; + break; + } + + if (res.eax & (1 << 9)) + associativity = SMBIOS_CACHE_ASSOCIATIVITY_FULL; + else + associativity = smbios_cache_associativity(assoc); + + update_max(len, *max_struct_size, smbios_write_type7(current, + *handle++, level, SMBIOS_CACHE_SRAM_TYPE_UNKNOWN, + associativity, type, cache_size, cache_size)); + }; + + return len; +} + static int smbios_write_type11(unsigned long *current, int *handle) { struct smbios_type11 *t = (struct smbios_type11 *)*current; @@ -726,14 +920,6 @@ return len; } -#define update_max(len, max_len, stmt) \ - do { \ - int tmp = stmt; \ - \ - max_len = MAX(max_len, tmp); \ - len += tmp; \ - } while (0) - unsigned long smbios_write_tables(unsigned long current) { struct smbios_entry *se; @@ -761,6 +947,8 @@ handle++)); update_max(len, max_struct_size, smbios_write_type4(&current, handle++)); + smbios_write_type7_cache_parameters(&current, &handle, + &max_struct_size); update_max(len, max_struct_size, smbios_write_type11(&current, &handle)); if (CONFIG(ELOG)) diff --git a/src/include/smbios.h b/src/include/smbios.h index af83bfe..c9deca5 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -393,6 +393,66 @@ u8 eos[2]; } __packed; +#define SMBIOS_CACHE_SRAM_TYPE_OTHER (1 << 0) +#define SMBIOS_CACHE_SRAM_TYPE_UNKNOWN (1 << 1) +#define SMBIOS_CACHE_SRAM_TYPE_NON_BURST (1 << 2) +#define SMBIOS_CACHE_SRAM_TYPE_BURST (1 << 3) +#define SMBIOS_CACHE_SRAM_TYPE_PIPELINE_BURST (1 << 4) +#define SMBIOS_CACHE_SRAM_TYPE_SYNCHRONOUS (1 << 5) +#define SMBIOS_CACHE_SRAM_TYPE_ASYNCHRONOUS (1 << 6) + +enum smbios_cache_error_corr { + SMBIOS_CACHE_ERROR_CORRECTION_OTHER = 0, + SMBIOS_CACHE_ERROR_CORRECTION_UNKNOWN, + SMBIOS_CACHE_ERROR_CORRECTION_NONE, + SMBIOS_CACHE_ERROR_CORRECTION_PARITY, + SMBIOS_CACHE_ERROR_CORRECTION_SINGLE_BIT, + SMBIOS_CACHE_ERROR_CORRECTION_MULTI_BIT, +}; + +enum smbios_cache_type { + SMBIOS_CACHE_TYPE_OTHER = 0, + SMBIOS_CACHE_TYPE_UNKNOWN, + SMBIOS_CACHE_TYPE_INSTRUCTION, + SMBIOS_CACHE_TYPE_DATA, + SMBIOS_CACHE_TYPE_UNIFIED, +}; + +enum smbios_cache_associativity { + SMBIOS_CACHE_ASSOCIATIVITY_OTHER = 0, + SMBIOS_CACHE_ASSOCIATIVITY_UNKNOWN, + SMBIOS_CACHE_ASSOCIATIVITY_DIRECT, + SMBIOS_CACHE_ASSOCIATIVITY_2WAY, + SMBIOS_CACHE_ASSOCIATIVITY_4WAY, + SMBIOS_CACHE_ASSOCIATIVITY_FULL, + SMBIOS_CACHE_ASSOCIATIVITY_8WAY, + SMBIOS_CACHE_ASSOCIATIVITY_16WAY, + SMBIOS_CACHE_ASSOCIATIVITY_12WAY, + SMBIOS_CACHE_ASSOCIATIVITY_24WAY, + SMBIOS_CACHE_ASSOCIATIVITY_32WAY, + SMBIOS_CACHE_ASSOCIATIVITY_48WAY, + SMBIOS_CACHE_ASSOCIATIVITY_64WAY, + SMBIOS_CACHE_ASSOCIATIVITY_20WAY, +}; + +struct smbios_type7 { + u8 type; + u8 length; + u16 handle; + u8 socket_designation; + u16 cache_configuration; + u16 max_cache_size; + u16 installed_size; + u16 supported_sram_type; + u8 cache_speed; + u8 error_correction_type; + u8 system_cache_type; + u8 associativity; + u32 max_cache_size2; + u32 installed_size2; + u8 eos[2]; +} __packed; + struct smbios_type11 { u8 type; u8 length; -- To view, visit https://review.coreboot.org/c/coreboot/+/32131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80ed25b8f2c7b425136b2f0c755324a8f5d1636d Gerrit-Change-Number: 32131 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

7 27

Change in ...coreboot[master]: arch/x86/cpu: Add functions to determine CPU vendor
by Patrick Rudolph (Code Review) 09 Apr '19

09 Apr '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32130 Change subject: arch/x86/cpu: Add functions to determine CPU vendor ...................................................................... arch/x86/cpu: Add functions to determine CPU vendor Add two functions to determine if CPU is made by a specific vendor. Use Kconfig symbols and CPUID to determine the CPU vendor. Change-Id: I1bd6c3b59cfd992f7ba507bc9f9269669920b24f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/arch/x86/cpu.c M src/arch/x86/include/arch/cpu.h 2 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/32130/1 diff --git a/src/arch/x86/cpu.c b/src/arch/x86/cpu.c index 80d4d0d..e82df00 100644 --- a/src/arch/x86/cpu.c +++ b/src/arch/x86/cpu.c @@ -196,6 +196,36 @@ } } +bool cpu_is_amd(void) +{ + if (CONFIG(CPU_AMD_AGESA) || CONFIG(CPU_AMD_PI)) + return true; + else if (CONFIG(CPU_INTEL_COMMON) || CONFIG(SOC_INTEL_COMMON)) + return false; + else if (cpu_have_cpuid()) { + struct device cpu; + identify_cpu(&cpu); + return cpu.vendor == X86_VENDOR_AMD; + } + + return false; +} + +bool cpu_is_intel(void) +{ + if (CONFIG(CPU_INTEL_COMMON) || CONFIG(SOC_INTEL_COMMON)) + return true; + else if (CONFIG(CPU_AMD_AGESA) || CONFIG(CPU_AMD_PI)) + return false; + else if (cpu_have_cpuid()) { + struct device cpu; + identify_cpu(&cpu); + return cpu.vendor == X86_VENDOR_INTEL; + } + + return false; +} + struct cpu_driver *find_cpu_driver(struct device *cpu) { struct cpu_driver *driver; diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index b40dd1b..ce4ae11 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -217,6 +217,10 @@ ci = cpu_info(); return ci->index; } + +bool cpu_is_amd(void); +bool cpu_is_intel(void); + #endif #ifndef __ROMCC__ // romcc is segfaulting in some cases -- To view, visit https://review.coreboot.org/c/coreboot/+/32130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1bd6c3b59cfd992f7ba507bc9f9269669920b24f Gerrit-Change-Number: 32130 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

4 7

Change in ...coreboot[master]: hatch: Add ACPI support for BT reset functionality
by Tim Wawrzynczak (Code Review) 09 Apr '19

09 Apr '19

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32216 Change subject: hatch: Add ACPI support for BT reset functionality ...................................................................... hatch: Add ACPI support for BT reset functionality Expose the BT_DISABLE_L signal in Hatch's devicetree, on both USB2 port 5 and 10. BUG=b:123293169 BRANCH=none TEST=compiles, verified kernel is able to find the reset-gpio Change-Id: I6e4d9786e44f12da71533b6740fdd390f3a57e40 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/hatch/variants/baseboard/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/32216/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb index 2f1120a..7dd41a2 100644 --- a/src/mainboard/google/hatch/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/hatch/variants/baseboard/devicetree.cb @@ -131,6 +131,7 @@ chip drivers/usb/acpi register "desc" = ""Discrete bluetooth"" register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C14)" device usb 2.4 on end end chip drivers/usb/acpi @@ -146,6 +147,7 @@ chip drivers/usb/acpi register "desc" = ""Integrated CnVi bluetooth"" register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C14)" device usb 2.9 on end end chip drivers/usb/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/32216 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6e4d9786e44f12da71533b6740fdd390f3a57e40 Gerrit-Change-Number: 32216 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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