coreboot-gerrit April 2019

coreboot-gerrit@coreboot.org

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1219 discussions

Change in ...coreboot[master]: [WIP]mb/google/sarien: Change GPIOs to avoid leakages during s0ix
by Roy Mingi Park (Code Review) 11 Apr '19

11 Apr '19

Roy Mingi Park has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32164 Change subject: [WIP]mb/google/sarien: Change GPIOs to avoid leakages during s0ix ...................................................................... [WIP]mb/google/sarien: Change GPIOs to avoid leakages during s0ix Change-Id: Ie0208bd6c7affb2e87fd76005b727ea7effdf434 Signed-off-by: Roy Mingi Park <roy.mingi.park(a)intel.com> --- M src/mainboard/google/sarien/variants/arcada/gpio.c 1 file changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/32164/1 diff --git a/src/mainboard/google/sarien/variants/arcada/gpio.c b/src/mainboard/google/sarien/variants/arcada/gpio.c index 1b06301..c6eb3f5 100644 --- a/src/mainboard/google/sarien/variants/arcada/gpio.c +++ b/src/mainboard/google/sarien/variants/arcada/gpio.c @@ -71,7 +71,8 @@ /* SPKR */ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* GSPI0_CS# */ PAD_NC(GPP_B15, NONE), /* PRIM_CORE_OPT_DIS (nostuff) */ /* GSPI0_CLK */ PAD_CFG_GPI(GPP_B16, NONE, DEEP), /* ONE_DIMM# */ -/* GSPI0_MISO */ PAD_CFG_GPI(GPP_B17, NONE, DEEP), /* RTC_DET# */ +/* GSPI0_MISO */ /*PAD_CFG_GPI(GPP_B17, NONE, DEEP),*/ /* RTC_DET# */ +/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE), /* RTC_DET# */ /* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE), /* GSPI1_CS# */ PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */ /* GSPI1_CLK */ PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */ @@ -209,8 +210,10 @@ /* I2C3_SCL */ PAD_NC(GPP_H7, NONE), /* I2C4_SDA */ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */ /* I2C4_SCL */ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */ -/* I2C5_SDA */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* ISH_I2C2_SDA */ -/* I2C5_SCL */ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* ISH_I2C2_SCL */ +/* I2C5_SDA */ /*PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),*/ /* ISH_I2C2_SDA */ +/* I2C5_SDA */ PAD_NC(GPP_H10, NONE), /* ISH_I2C2_SDA */ +/* I2C5_SCL */ /*PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),*/ /* ISH_I2C2_SCL */ +/* I2C5_SCL */ PAD_NC(GPP_H11, NONE), /* ISH_I2C2_SCL */ /* M2_SKT2_CFG0 */ PAD_NC(GPP_H12, NONE), /* M2_SKT2_CFG1 */ PAD_NC(GPP_H13, NONE), /* M2_SKT2_CFG2 */ PAD_NC(GPP_H14, NONE), -- To view, visit https://review.coreboot.org/c/coreboot/+/32164 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0208bd6c7affb2e87fd76005b727ea7effdf434 Gerrit-Change-Number: 32164 Gerrit-PatchSet: 1 Gerrit-Owner: Roy Mingi Park <roy.mingi.park(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: nb/intel/{gm45,i945,x4x}: Correct array bounds checks
by Jacob Garber (Code Review) 11 Apr '19

11 Apr '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32244 Change subject: nb/intel/{gm45,i945,x4x}: Correct array bounds checks ...................................................................... nb/intel/{gm45,i945,x4x}: Correct array bounds checks There will be an out of bounds read if the index is equal to the array size. Fix the checks to exclude this case. Found-by: Coverity Scan, CID 1347350, 1347351 Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Change-Id: I5b4e8febb68dfd244faf597dfe5cdf509af7a2ae --- M src/northbridge/intel/gm45/ram_calc.c M src/northbridge/intel/i945/ram_calc.c M src/northbridge/intel/x4x/ram_calc.c 3 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/32244/1 diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index c72055f..c1307c4 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -39,7 +39,7 @@ static const u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64, 128, 256, 96, 160, 224, 352 }; - if (gms > ARRAY_SIZE(ggc2uma)) + if (gms >= ARRAY_SIZE(ggc2uma)) die("Bad Graphics Mode Select (GMS) setting.\n"); return ggc2uma[gms] << 10; diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c index 124a6a8..752c8f9 100644 --- a/src/northbridge/intel/i945/ram_calc.c +++ b/src/northbridge/intel/i945/ram_calc.c @@ -82,7 +82,7 @@ static const u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64 }; - if (gms > ARRAY_SIZE(ggc2uma)) + if (gms >= ARRAY_SIZE(ggc2uma)) die("Bad Graphics Mode Select (GMS) setting.\n"); return ggc2uma[gms] << 10; diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c index 8f9d739..3714969 100644 --- a/src/northbridge/intel/x4x/ram_calc.c +++ b/src/northbridge/intel/x4x/ram_calc.c @@ -36,7 +36,7 @@ static const u16 ggc2uma[] = { 0, 1, 4, 8, 16, 32, 48, 64, 128, 256, 96, 160, 224, 352 }; - if (gms > ARRAY_SIZE(ggc2uma)) + if (gms >= ARRAY_SIZE(ggc2uma)) die("Bad Graphics Mode Select (GMS) setting.\n"); return ggc2uma[gms] << 10; @@ -47,7 +47,7 @@ { static const u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4}; - if (gsm > ARRAY_SIZE(ggc2gtt)) + if (gsm >= ARRAY_SIZE(ggc2gtt)) die("Bad GTT Graphics Memory Size (GGMS) setting.\n"); return ggc2gtt[gsm] << 10; -- To view, visit https://review.coreboot.org/c/coreboot/+/32244 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b4e8febb68dfd244faf597dfe5cdf509af7a2ae Gerrit-Change-Number: 32244 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: util/inteltool: Swap conditions to prevent uninit reads
by Jacob Garber (Code Review) 11 Apr '19

11 Apr '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32269 Change subject: util/inteltool: Swap conditions to prevent uninit reads ...................................................................... util/inteltool: Swap conditions to prevent uninit reads Both values in each array are only initialized if `two_channels` is true, so we need to check that first. Found-by: Coverity Scan #1370{584,585,588,589,590-596,600} Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Change-Id: I592bc6ae00f834f74a61668d7a3919014ec635f3 --- M util/inteltool/ivy_memory.c 1 file changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/32269/1 diff --git a/util/inteltool/ivy_memory.c b/util/inteltool/ivy_memory.c index f0e473f..8ce8611 100644 --- a/util/inteltool/ivy_memory.c +++ b/util/inteltool/ivy_memory.c @@ -172,47 +172,47 @@ printf(".reg_4004_b30 = { %d, %d },\n", reg_4004_b30[0], reg_4004_b30[1]); - if (tFAW[0] != tFAW[1] && two_channels) + if (two_channels && tFAW[0] != tFAW[1]) printf("/* tFAW mismatch: %d, %d */\n", tFAW[0], tFAW[1]); print_time("tFAW", tFAW[0], tCK); - if (tWTR[0] != tWTR[1] && two_channels) + if (two_channels && tWTR[0] != tWTR[1]) printf("/* tWTR mismatch: %d, %d */\n", tWTR[0], tWTR[1]); print_time("tWTR", tWTR[0], tCK); - if (tCKE[0] != tCKE[1] && two_channels) + if (two_channels && tCKE[0] != tCKE[1]) printf("/* tCKE mismatch: %d, %d */\n", tCKE[0], tCKE[1]); print_time("tCKE", tCKE[0], tCK); - if (tRTP[0] != tRTP[1] && two_channels) + if (two_channels && tRTP[0] != tRTP[1]) printf("/* tRTP mismatch: %d, %d */\n", tRTP[0], tRTP[1]); print_time("tRTP", tRTP[0], tCK); - if (tRRD[0] != tRRD[1] && two_channels) + if (two_channels && tRRD[0] != tRRD[1]) printf("/* tRRD mismatch: %d, %d */\n", tRRD[0], tRRD[1]); print_time("tRRD", tRRD[0], tCK); - if (tRAS[0] != tRAS[1] && two_channels) + if (two_channels && tRAS[0] != tRAS[1]) printf("/* tRAS mismatch: %d, %d */\n", tRAS[0], tRAS[1]); print_time("tRAS", tRAS[0], tCK); - if (tCWL[0] != tCWL[1] && two_channels) + if (two_channels && tCWL[0] != tCWL[1]) printf("/* tCWL mismatch: %d, %d */\n", tCWL[0], tCWL[1]); print_time("tCWL", tCWL[0], tCK); - if (tRP[0] != tRP[1] && two_channels) + if (two_channels && tRP[0] != tRP[1]) printf("/* tRP mismatch: %d, %d */\n", tRP[0], tRP[1]); print_time("tRP", tRP[0], tCK); - if (tRCD[0] != tRCD[1] && two_channels) + if (two_channels && tRCD[0] != tRCD[1]) printf("/* tRCD mismatch: %d, %d */\n", tRCD[0], tRCD[1]); print_time("tRCD", tRCD[0], tCK); - if (tXPDLL[0] != tXPDLL[1] && two_channels) + if (two_channels && tXPDLL[0] != tXPDLL[1]) printf("/* tXPDLL mismatch: %d, %d */\n", tXPDLL[0], tXPDLL[1]); print_time("tXPDLL", tXPDLL[0], tCK); - if (tXP[0] != tXP[1] && two_channels) + if (two_channels && tXP[0] != tXP[1]) printf("/* tXP mismatch: %d, %d */\n", tXP[0], tXP[1]); print_time("tXP", tXP[0], tCK); - if (tAONPD[0] != tAONPD[1] && two_channels) + if (two_channels && tAONPD[0] != tAONPD[1]) printf("/* tAONPD mismatch: %d, %d */\n", tAONPD[0], tAONPD[1]); print_time("tAONPD", tAONPD[0], tCK); -- To view, visit https://review.coreboot.org/c/coreboot/+/32269 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I592bc6ae00f834f74a61668d7a3919014ec635f3 Gerrit-Change-Number: 32269 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Correct the GPE DWx mapping for GPIO groups
by Aamir Bohra (Code Review) 11 Apr '19

11 Apr '19

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32175 Change subject: soc/intel/cannonlake: Correct the GPE DWx mapping for GPIO groups ...................................................................... soc/intel/cannonlake: Correct the GPE DWx mapping for GPIO groups This implementation corrects the GPE DWx mapping for GPIO groups. The assignments is done in GPIO MISCFG register for all GPIO communities. And configures the which GPIO communities get register as Tier1. BUG=b:121212459 TEST: Verified the GPIO MISCFG is getting set as per updated map. Change-Id: I451997367025a6dc9e5931bd649524e935ad6aca Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h 1 file changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/32175/1 diff --git a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h index 03f4314..cca2bc4 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_soc_defs.h @@ -26,14 +26,14 @@ #define GPP_B 1 #define GPP_G 2 #define GROUP_SPI 3 -#define GPP_D 4 -#define GPP_F 5 -#define GPP_H 6 -#define GROUP_VGPIO 7 -#define GPD 9 -#define GROUP_AZA 0xA -#define GROUP_CPU 0xB -#define GPP_C 0xC +#define GPP_D 5 +#define GPP_F 6 +#define GPP_H 7 +#define GROUP_VGPIO 8 +#define GPD 0xA +#define GROUP_AZA 0xB +#define GROUP_CPU 0xC +#define GPP_C 4 #define GPP_E 0xD #define GROUP_JTAG 0xE #define GROUP_HVMOS 0xF -- To view, visit https://review.coreboot.org/c/coreboot/+/32175 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I451997367025a6dc9e5931bd649524e935ad6aca Gerrit-Change-Number: 32175 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: libpayload: keyboard: Add F11 and F12 support
by Matt Delco (Code Review) 11 Apr '19

11 Apr '19

Matt Delco has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32256 Change subject: libpayload: keyboard: Add F11 and F12 support ...................................................................... libpayload: keyboard: Add F11 and F12 support The firmware is basically ignoring F11 and F12 without this change. This existing source file doesn't see to comply with the automatic formatter, and it wants to make a lot of unrelated line changes so I've disabled it. BUG=b:130143385 TEST=local compile and flash to device. Confirmed that press of F11 and F12 keys now generates appropriate keypress events (and the same codes that are already generated by these keys on an external USB keyboard). Signed-off-by: Matt Delco <delco(a)chromium.org> Change-Id: Ic43114aa99fc0a1345782c81ed2b90f5569af383 --- M payloads/libpayload/drivers/i8042/keyboard.c 1 file changed, 18 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/32256/1 diff --git a/payloads/libpayload/drivers/i8042/keyboard.c b/payloads/libpayload/drivers/i8042/keyboard.c index be22497..1035bf2 100644 --- a/payloads/libpayload/drivers/i8042/keyboard.c +++ b/payloads/libpayload/drivers/i8042/keyboard.c @@ -38,7 +38,7 @@ struct layout_maps { const char *country; - const unsigned short map[4][0x57]; + const unsigned short map[4][0x59]; }; static struct layout_maps *map; @@ -58,7 +58,8 @@ 0x00, 0x20, 0x00, KEY_F(1), KEY_F(2), KEY_F(3), KEY_F(4), KEY_F(5), KEY_F(6), KEY_F(7), KEY_F(8), KEY_F(9), KEY_F(10), 0x00, 0x00, KEY_HOME, KEY_UP, KEY_NPAGE, 0x00, KEY_LEFT, 0x00, KEY_RIGHT, 0x00, KEY_END, - KEY_DOWN, KEY_PPAGE, 0x00, KEY_DC, 0x00, 0x00, 0x00 + KEY_DOWN, KEY_PPAGE, 0x00, KEY_DC, 0x00, 0x00, 0x00, KEY_F(11), + KEY_F(12), }, { /* Shift */ 0x00, 0x1B, 0x21, 0x40, 0x23, 0x24, 0x25, 0x5E, @@ -71,7 +72,8 @@ 0x00, 0x20, 0x00, KEY_F(1), KEY_F(2), KEY_F(3), KEY_F(4), KEY_F(5), KEY_F(6), KEY_F(7), KEY_F(8), KEY_F(9), KEY_F(10), 0x00, 0x00, KEY_HOME, KEY_UP, KEY_NPAGE, 0x00, KEY_LEFT, 0x00, KEY_RIGHT, 0x00, KEY_END, - KEY_DOWN, KEY_PPAGE, 0x00, KEY_DC, 0x00, 0x00, 0x00 + KEY_DOWN, KEY_PPAGE, 0x00, KEY_DC, 0x00, 0x00, 0x00, KEY_F(11), + KEY_F(12), }, { /* ALT */ 0x00, 0x1B, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, @@ -84,7 +86,8 @@ 0x00, 0x20, 0x00, KEY_F(1), KEY_F(2), KEY_F(3), KEY_F(4), KEY_F(5), KEY_F(6), KEY_F(7), KEY_F(8), KEY_F(9), KEY_F(10), 0x00, 0x00, KEY_HOME, KEY_UP, KEY_NPAGE, 0x00, KEY_LEFT, 0x00, KEY_RIGHT, 0x00, KEY_END, - KEY_DOWN, KEY_PPAGE, 0x00, KEY_DC, 0x00, 0x00, 0x00 + KEY_DOWN, KEY_PPAGE, 0x00, KEY_DC, 0x00, 0x00, 0x00, KEY_F(11), + KEY_F(12), }, { /* Shift-ALT */ 0x00, 0x1B, 0x21, 0x40, 0x23, 0x24, 0x25, 0x5E, @@ -97,7 +100,8 @@ 0x00, 0x20, 0x00, KEY_F(1), KEY_F(2), KEY_F(3), KEY_F(4), KEY_F(5), KEY_F(6), KEY_F(7), KEY_F(8), KEY_F(9), KEY_F(10), 0x00, 0x00, KEY_HOME, KEY_UP, KEY_NPAGE, 0x00, KEY_LEFT, 0x00, KEY_RIGHT, 0x00, KEY_END, - KEY_DOWN, KEY_PPAGE, 0x00, KEY_DC, 0x00, 0x00, 0x00 + KEY_DOWN, KEY_PPAGE, 0x00, KEY_DC, 0x00, 0x00, 0x00, KEY_F(11), + KEY_F(12), } }}, #endif @@ -114,7 +118,8 @@ 0x00, 0x20, 0x00, KEY_F(1), KEY_F(2), KEY_F(3), KEY_F(4), KEY_F(5), KEY_F(6), KEY_F(7), KEY_F(8), KEY_F(9), KEY_F(10), 0x00, 0x00, KEY_HOME, KEY_UP, KEY_NPAGE, 0x00, KEY_LEFT, 0x00, KEY_RIGHT, 0x00, KEY_END, - KEY_DOWN, KEY_PPAGE, 0x00, KEY_DC, 0x00, 0x00, 0x3C + KEY_DOWN, KEY_PPAGE, 0x00, KEY_DC, 0x00, 0x00, 0x3C, KEY_F(11), + KEY_F(12), }, { /* Shift */ 0x00, 0x1B, 0x21, 0x22, 0xA7, 0x24, 0x25, 0x26, @@ -127,7 +132,8 @@ 0x00, 0x20, 0x00, KEY_F(1), KEY_F(2), KEY_F(3), KEY_F(4), KEY_F(5), KEY_F(6), KEY_F(7), KEY_F(8), KEY_F(9), KEY_F(10), 0x00, 0x00, KEY_HOME, KEY_UP, KEY_NPAGE, 0x00, KEY_LEFT, 0x00, KEY_RIGHT, 0x00, KEY_END, - KEY_DOWN, KEY_PPAGE, 0x00, KEY_DC, 0x00, 0x00, 0x3E + KEY_DOWN, KEY_PPAGE, 0x00, KEY_DC, 0x00, 0x00, 0x3E, KEY_F(11), + KEY_F(12), }, { /* ALT */ 0x00, 0x1B, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, @@ -140,7 +146,8 @@ 0x00, 0x20, 0x00, KEY_F(1), KEY_F(2), KEY_F(3), KEY_F(4), KEY_F(5), KEY_F(6), KEY_F(7), KEY_F(8), KEY_F(9), KEY_F(10), 0x00, 0x00, KEY_HOME, KEY_UP, KEY_NPAGE, 0x00, KEY_LEFT, 0x00, KEY_RIGHT, 0x00, KEY_END, - KEY_DOWN, KEY_PPAGE, 0x00, KEY_DC, 0x00, 0x00, 0x7C + KEY_DOWN, KEY_PPAGE, 0x00, KEY_DC, 0x00, 0x00, 0x7C, KEY_F(11), + KEY_F(12), }, { /* Shift-ALT */ /* copied from US */ @@ -154,7 +161,8 @@ 0x00, 0x20, 0x00, KEY_F(1), KEY_F(2), KEY_F(3), KEY_F(4), KEY_F(5), KEY_F(6), KEY_F(7), KEY_F(8), KEY_F(9), KEY_F(10), 0x00, 0x00, KEY_HOME, KEY_UP, KEY_NPAGE, 0x00, KEY_LEFT, 0x00, KEY_RIGHT, 0x00, KEY_END, - KEY_DOWN, KEY_PPAGE, 0x00, KEY_DC, 0x00, 0x00, 0x00 + KEY_DOWN, KEY_PPAGE, 0x00, KEY_DC, 0x00, 0x00, 0x00, KEY_F(11), + KEY_F(12), } }}, #endif @@ -232,7 +240,7 @@ ch = keyboard_get_scancode(); - if (!(ch & 0x80) && ch < 0x57) { + if (!(ch & 0x80) && ch < 0x59) { shift = (modifier & KB_MOD_SHIFT) ^ (modifier & KB_MOD_CAPSLOCK) ? 1 : 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/32256 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic43114aa99fc0a1345782c81ed2b90f5569af383 Gerrit-Change-Number: 32256 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Delco <delco(a)chromium.org> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/ampton: Fix polarity of EN_PP3300_WLAN_L signal.
by Tim Wawrzynczak (Code Review) 11 Apr '19

11 Apr '19

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32255 Change subject: mb/google/ampton: Fix polarity of EN_PP3300_WLAN_L signal. ...................................................................... mb/google/ampton: Fix polarity of EN_PP3300_WLAN_L signal. WiFi enable signal Was configured and driven as active-high, but the signal is actually active-low. BUG=b:130196983 BRANCH=none TEST=Verified WiFi still works after boot, and also after a suspend/resume cycle. Device powers down correctly using "poweroff". Change-Id: I64a67f73564188ad0548a1a770169ef2bca47453 Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/mainboard/google/octopus/variants/ampton/gpio.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/32255/1 diff --git a/src/mainboard/google/octopus/variants/ampton/gpio.c b/src/mainboard/google/octopus/variants/ampton/gpio.c index 984dae0..0eac121 100644 --- a/src/mainboard/google/octopus/variants/ampton/gpio.c +++ b/src/mainboard/google/octopus/variants/ampton/gpio.c @@ -246,7 +246,7 @@ /* SCC COMMUNITY GPIOS */ PAD_NC(GPIO_176, UP_20K), /* SMB_ALERTB -- unused */ PAD_NC(GPIO_177, UP_20K), /* SMB_CLK -- unused */ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 1, DEEP, NONE, Tx1RxDCRx0, DISPUPD), /* EN_PP3300_WLAN */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 1, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* EN_PP3300_WLAN */ PAD_NC(GPIO_179, NONE), /* SDCARD_CLK -- unused */ PAD_NC(GPIO_180, NONE), /* SDCARD_CMD -- unused */ PAD_NC(GPIO_181, UP_20K), /* SDCARD_D0 -- unused */ @@ -305,11 +305,11 @@ PAD_CFG_NF(GPIO_83, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MOSI_R */ /* Enable power to wifi early in bootblock and de-assert PERST#. */ - PAD_CFG_GPO(GPIO_178, 1, DEEP), /* EN_PP3300_WLAN */ + PAD_CFG_GPO(GPIO_178, 0, DEEP), /* EN_PP3300_WLAN */ PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */ /* - * ESPI_IO1 acts as ALERT# (which is open-drain) and requies a weak + * ESPI_IO1 acts as ALERT# (which is open-drain) and requires a weak * pull-up for proper operation. Since there is no external pull present * on this platform, configure an internal weak pull-up. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32255 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I64a67f73564188ad0548a1a770169ef2bca47453 Gerrit-Change-Number: 32255 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

5 13

Change in ...coreboot[master]: Documentation: Explain FMAP and FMD
by Hung-Te Lin (Code Review) 11 Apr '19

11 Apr '19

Hung-Te Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31766 Change subject: Documentation: Explain FMAP and FMD ...................................................................... Documentation: Explain FMAP and FMD The Flashmap (FMAP) was not clearly documented. The new flashmap.md explains where to find more details about that and how / why it was used in coreboot. Also explained what is FMD and how to use it. BUG=None TEST=None (only documentation). Change-Id: Ia389e56c632096d7c905ed221fd4f140dec382e6 Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> --- A Documentation/flashmap.md M Documentation/index.md D util/cbfstool/README.fmaptool 3 files changed, 116 insertions(+), 69 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/31766/1 diff --git a/Documentation/flashmap.md b/Documentation/flashmap.md new file mode 100644 index 0000000..c6780b6 --- /dev/null +++ b/Documentation/flashmap.md @@ -0,0 +1,115 @@ +# Flashmap and Flashmap Descriptor in coreboot + +## Flashmap + +[Flashmap](https://code.google.com/p/flashmap) (FMAP) is a binary format +originally developed for Chromium OS to manipulate firmware image and to +represent the layout of flash chips. With Flashmap, the firmware image is split +into multiple `fmap_area` (may also be referred as 'regions', or 'sections'). +Each area has a name, offset, size and 16 bits of flags. + +coreboot puts most data in the CBFS structure. But many systems, especially +Chromium OS, need some area to be created in different format and layout. For +example, Chromium OS has defined a key-value style "Vital Product Data" (VPD) +that cannot live inside CBFS. Intel firmware also usually need a place to put +the firmware for management engine. Some ARM SOCs also need to preserve +calibration data in the fixed location. This is very helpful to manipulate +non-coreboot data. + +As a result, Flashmap is now directly supported by coreboot, and is the +de facto standard FMAP implementation. + +## Flashmap Descriptor + +Since coreboot is starting to use a "partition" of Flashmap to describe the +flash chip layout (both at runtime and when flashing a new image onto a +chip), the project needs a reasonably expressive plain text format for +representing such sections in the source tree. + +Flashmap Descriptor (FMD) is a [language and +compiler](https://chromium-review.googlesource.com/#/c/255031) inside coreboot +utility folder that can be used to generate final firmware images (i.e. +`coreboot.rom`) formatted by Flashmap. + +The FMD in coreboot `utils` folder contains a scanner, parser, semantic +analyzer, and Flashmap converter. Here's an informal language description: + +``` +# <line comment> +<image name>[@<memory-mapped address>] <image size> { + <section name>[(flags)][@<offset from start of image>] [<section size>] [{ + <subsection name>[@<offset from start of parent section>] [<subsection size>] [{ + # Sections can be nested as deeply as desired + <subsubsection name>[(flags)][@...] [...] [{...}] + }] + [<subsection name>[(flags)][@...] [...] [{...}]] + # There can be many subsections at each level of nesting: they will be inserted + # sequentially, and although gaps are allowed, any provided offsets are always + # relative to the closest parent node's and must be strictly increasing with neither + # overlapping nor degenerate-size sections. + }] +} +``` + +Note that the above example contains a few symbols that are actually meta +syntax, and therefore have neither meaning nor place in a real file. The `<.*>`s +indicate placeholders for parameters: + +* The names are strings, which are provided as single-word (no white space) + groups of syntactically unimportant symbols (i.e. every thing except `@`, `{`, + and `}`): they are not surrounded by quotes or any other form of delimiter. +* The other fields are non-negative integers, which may be given as decimal or + hexadecimal; in either case, a `K`, `M`, or `G` may be appended (without + intermediate white space) as a multiplier. +* Comments consist of anything one manages to enter, provided it doesn't start a + new line. + +The `[.*]`s indicate that a portion of the file could be omitted altogether: + +* Just because something is noted as optional doesn't mean it is in every case: + the answer might actually depend on which other information is---or + isn't---provided. +* The "flag" specifies the attribute or type for given section. The most + important supported flag is "CBFS", which indicates the section will contain + a CBFS structure. +* In particular, it is only legal to place a (CBFS) flag on a leaf section; that + is, choosing to add child sections excludes the possibility of putting a CBFS + in their parent. Such flags are only used to decide where CBFS empty file + headers should be created, and do not result in the storage of any additional + metadata in the resulting FMAP section. + +Additionally, it's important to note these properties of the overall file and +its values: + +* Other than within would-be strings and numbers, white space is ignored. It + goes without saying that such power comes with responsibility, which is why + this sentence is here. +* Although the `section name` must be globally unique, one of them may (but is + not required to) match the image name. +* It is a syntax error to supply a number (besides 0) that begins with the + character `0`, as there is no intention of adding octals to the mix. +* The image's memory address should be present on (and only on) layouts for + memory-mapped chips. +* Although it may be evident from above, all `section` offsets are relative only + to the immediate parent. There is no way to include an absolute offset (i.e. + from the beginning of flash), which means that it is "safe" to reorder the + sections within a particular level of nesting, as long as the change doesn't + cause their positions and sizes to necessitate overlap or zero sizes. +* A `section` with omitted offset is assumed to start at as low a position as + possible (with no consideration of alignment) and one with omitted size is + assumed to fill the remaining space until the next sibling or before the end + of its parent. +* It's fine to omit any `section`'s offset, size, or both, provided its position + and size are still unambiguous in the context of its *sibling* sections and + its parent's *size*. In particular, knowledge of one .*section 's children or + the `section`s' common parent's siblings will not be used for this purpose. +* Although `section`s are not required to have children, the flash chip as a + whole must have at least one. +* Though the braces after `section`s may be omitted for those that have no + children, if they are present, they must contain at least one child. + +PL people and sympathizers may wish to examine the formal abstract syntax and +context-free grammar, which are located in `fmd_scanner.l` and `fmd_scanner.y`, +respectively. Those interested in the algorithm used to infer omitted values +will feel at home in `fmd.c`, particularly near the definition of +`validate_and_complete_info()`. diff --git a/Documentation/index.md b/Documentation/index.md index dd8714c..9398458 100644 --- a/Documentation/index.md +++ b/Documentation/index.md @@ -186,3 +186,4 @@ * [Utilities](util.md) * [Release notes for past releases](releases/index.md) * [Flashing firmware tutorial](flash_tutorial/index.md) +* [Flashmap and Flashmap Descriptor](flashmap.md) diff --git a/util/cbfstool/README.fmaptool b/util/cbfstool/README.fmaptool deleted file mode 100644 index 86fc3b2..0000000 --- a/util/cbfstool/README.fmaptool +++ /dev/null @@ -1,69 +0,0 @@ -Flashmap descriptors in coreboot -================================ -Flashmap (https://code.google.com/p/flashmap) is a binary format for representing the layout of -flash chips. Since coreboot is starting to use a "partition" of this format to describe the flash -chip layout---both at runtime and when flashing a new image onto a chip---, the project needed a -reasonably expressive plaintext format for representing such sections in the source tree. Our -solution is the fmd ("flashmap descriptor") language, and the files in this directory contain a -scanner, parser, semantic analyser, and flashmap converter. Here's an informal language description: - -# <line comment> -<image name>[@<memory-mapped address>] <image size> { - <section name>[(flags)][@<offset from start of image>] [<section size>] [{ - <subsection name>[@<offset from start of parent section>] [<subsection size>] [{ - # Sections can be nested as deeply as desired - <subsubsection name>[(flags)][@...] [...] [{...}] - }] - [<subsection name>[(flags)][@...] [...] [{...}]] - # There can be many subsections at each level of nesting: they will be inserted - # sequentially, and although gaps are allowed, any provided offsets are always - # relative to the closest parent node's and must be strictly increasing with neither - # overlapping nor degenerate-size sections. - }] -} - -Note that the above example contains a few symbols that are actually metasyntax, and therefore have -neither meaning nor place in a real file. The <.*> s indicate placeholders for parameters: - - The names are strings, which are provided as single-word---no whitespace---groups of - syntactically unimportant symbols (i.e. everything except @, {, and }): they are not surrounded - by quotes or any other form of delimiter. - - The other fields are nonnegative integers, which may be given as decimal or hexadecimal; in - either case, a K, M, or G may be appended---without intermediate whitespace---as a multiplier. - - Comments consist of anything one manages to enter, provided it doesn't start a new line. -The [.*] s indicate that a portion of the file could be omitted altogether: - - Just because something is noted as optional doesn't mean it is in every case: the answer might - actually depend on which other information is---or isn't---provided. - - The "flag" specifies the attribute or type for given section. The most - important supported flag is "CBFS", which indicates the section will contain a CBFS structure. - - In particular, it is only legal to place a (CBFS) flag on a leaf section; that is, choosing - to add child sections excludes the possibility of putting a CBFS in their parent. Such - flags are only used to decide where CBFS empty file headers should be created, and do not - result in the storage of any additional metadata in the resulting FMAP section. -Additionally, it's important to note these properties of the overall file and its values: - - Other than within would-be strings and numbers, whitespace is ignored. It goes without saying - that such power comes with responsibility, which is why this sentence is here. - - Although the .*section names must be globally unique, one of them may---but is not required to--- - match the image name. - - It is a syntax error to supply a number---besides 0---that begins with the character 0, as there - is no intention of adding octals to the mix. - - The image's memory address should be present on---and only on---layouts for memory-mapped chips. - - Although it may be evident from above, all .*section offsets are relative only to the immediate - parent. There is no way to include an absolute offset (i.e. from the beginning of flash), which - means that it is "safe" to reorder the .*section s within a particular level of nesting, as long - as the change doesn't cause their positions and sizes to necessitate overlap or zero sizes. - - A .*section with omitted offset is assumed to start at as low a position as possible---with no - consideration of alignment---and one with omitted size is assumed to fill the remaining space - until the next sibling or before the end of its parent. - - It's fine to omit any .*section 's offset, size, or both, provided its position and size are - still unambiguous in the context of its *sibling* sections and its parent's *size*. In - particular, knowledge of one .*section 's children or the .*section s' common parent's siblings - will not be used for this purpose. - - Although .*section s are not required to have children, the flash chip as a whole must have at - least one. - - Though the braces after .*section s may be omitted for those that have no children, if they are - present, they must contain at least one child. - -PL people and sympathizers may wish to examine the formal abstract syntax and context-free grammar, -which are located in fmd_scanner.l and fmd_scanner.y, respectively. Those interested in the -algorithm used to infer omitted values will feel at home in fmd.c, particularly near the definition -of validate_and_complete_info(). -- To view, visit https://review.coreboot.org/c/coreboot/+/31766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia389e56c632096d7c905ed221fd4f140dec382e6 Gerrit-Change-Number: 31766 Gerrit-PatchSet: 1 Gerrit-Owner: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: newchange

6 28

Change in ...coreboot[master]: vboot: do not set VBSD_BOOT_FIRMWARE_WP_ENABLED flag
by Joel Kitching (Code Review) 11 Apr '19

11 Apr '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32234 Change subject: vboot: do not set VBSD_BOOT_FIRMWARE_WP_ENABLED flag ...................................................................... vboot: do not set VBSD_BOOT_FIRMWARE_WP_ENABLED flag The value of "write protect" GPIO shall be read in depthcharge, and the flag shall be set there instead. BUG=b:124141368, b:124192753, chromium:1556855 TEST=Build locally CQ-DEPEND=CL:1556855 BRANCH=none Change-Id: I4d24a057b1385244a836a67c565ee6726a894fdc Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/security/vboot/vboot_handoff.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/32234/1 diff --git a/src/security/vboot/vboot_handoff.c b/src/security/vboot/vboot_handoff.c index 2f239e6..047fcaf 100644 --- a/src/security/vboot/vboot_handoff.c +++ b/src/security/vboot/vboot_handoff.c @@ -58,9 +58,6 @@ vb_sd->data_used = sizeof(VbSharedDataHeader); vb_sd->fw_version_tpm = vb2_sd->fw_version_secdata; - if (get_write_protect_state()) - vb_sd->flags |= VBSD_BOOT_FIRMWARE_WP_ENABLED; - if (vb2_sd->recovery_reason) { vb_sd->firmware_index = 0xFF; if (vb2_sd->flags & VB2_SD_FLAG_MANUAL_RECOVERY) -- To view, visit https://review.coreboot.org/c/coreboot/+/32234 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4d24a057b1385244a836a67c565ee6726a894fdc Gerrit-Change-Number: 32234 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

4 6

Change in ...coreboot[master]: chromeos: clean up "recovery" and "write protect" GPIOs
by Joel Kitching (Code Review) 11 Apr '19

11 Apr '19

Joel Kitching has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32233 Change subject: chromeos: clean up "recovery" and "write protect" GPIOs ...................................................................... chromeos: clean up "recovery" and "write protect" GPIOs The "write protect" GPIO's cached value is never actually read after entering depthcharge. Ensure the value from get_write_protect_state() is being transferred accurately, so that we may read this GPIO value in depthcharge without resampling. The cached value of the "recovery" GPIO is read only on certain boards which have a physical recovery switch. Correct some of the values sent to boards which presumably never read the previously incorrect value. Most of these inaccuracies are from non-inverted values on ACTIVE_LOW GPIOs. BUG=b:124141368, b:124192753, chromium:950273 TEST=make clean && make test-abuild BRANCH=none Change-Id: Ic17a98768703d7098480a9233b752fe5b201bd51 Signed-off-by: Joel Kitching <kitching(a)google.com> --- M src/mainboard/google/auron/chromeos.c M src/mainboard/google/beltino/chromeos.c M src/mainboard/google/cheza/chromeos.c M src/mainboard/google/daisy/chromeos.c M src/mainboard/google/foster/chromeos.c M src/mainboard/google/gale/chromeos.c M src/mainboard/google/gru/chromeos.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/nyan/chromeos.c M src/mainboard/google/nyan_big/chromeos.c M src/mainboard/google/nyan_blaze/chromeos.c M src/mainboard/google/oak/chromeos.c M src/mainboard/google/peach_pit/chromeos.c M src/mainboard/google/sarien/chromeos.c M src/mainboard/google/slippy/chromeos.c M src/mainboard/google/smaug/chromeos.c M src/mainboard/google/storm/chromeos.c M src/mainboard/google/veyron/chromeos.c M src/mainboard/google/veyron_mickey/chromeos.c M src/mainboard/google/veyron_rialto/chromeos.c M src/mainboard/intel/baskingridge/chromeos.c M src/mainboard/intel/emeraldlake2/chromeos.c M src/mainboard/intel/wtm2/chromeos.c 23 files changed, 51 insertions(+), 49 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/32233/1 diff --git a/src/mainboard/google/auron/chromeos.c b/src/mainboard/google/auron/chromeos.c index c27ad9e..942e9dd 100644 --- a/src/mainboard/google/auron/chromeos.c +++ b/src/mainboard/google/auron/chromeos.c @@ -25,7 +25,8 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {CROS_WP_GPIO, ACTIVE_HIGH, 0, "write protect"}, + {CROS_WP_GPIO, ACTIVE_HIGH, get_write_protect_state(), + "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, diff --git a/src/mainboard/google/beltino/chromeos.c b/src/mainboard/google/beltino/chromeos.c index 1a1d0a2..92bb7b4 100644 --- a/src/mainboard/google/beltino/chromeos.c +++ b/src/mainboard/google/beltino/chromeos.c @@ -33,9 +33,10 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {GPIO_SPI_WP, ACTIVE_HIGH, 0, "write protect"}, + {GPIO_SPI_WP, ACTIVE_HIGH, + get_write_protect_state(), "write protect"}, {GPIO_REC_MODE, ACTIVE_LOW, - get_recovery_mode_switch(), "recovery"}, + !get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, 1, "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/cheza/chromeos.c b/src/mainboard/google/cheza/chromeos.c index 1c2c4f5..e840613 100644 --- a/src/mainboard/google/cheza/chromeos.c +++ b/src/mainboard/google/cheza/chromeos.c @@ -38,7 +38,7 @@ "EC in RW"}, {GPIO_AP_EC_INT.addr, ACTIVE_LOW, gpio_get(GPIO_AP_EC_INT), "EC interrupt"}, - {GPIO_WP_STATE.addr, ACTIVE_LOW, gpio_get(GPIO_WP_STATE), + {GPIO_WP_STATE.addr, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, {GPIO_H1_AP_INT.addr, ACTIVE_LOW, gpio_get(GPIO_H1_AP_INT), "TPM interrupt"}, diff --git a/src/mainboard/google/daisy/chromeos.c b/src/mainboard/google/daisy/chromeos.c index 65139bb..c06f839 100644 --- a/src/mainboard/google/daisy/chromeos.c +++ b/src/mainboard/google/daisy/chromeos.c @@ -27,7 +27,7 @@ { struct lb_gpio chromeos_gpios[] = { /* Write Protect: active low (WP_GPIO) */ - {EXYNOS5_GPD1, ACTIVE_LOW, gpio_get_value(GPIO_D16), + {EXYNOS5_GPD1, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, /* Recovery: active low */ diff --git a/src/mainboard/google/foster/chromeos.c b/src/mainboard/google/foster/chromeos.c index 024fd4c..026dd3e 100644 --- a/src/mainboard/google/foster/chromeos.c +++ b/src/mainboard/google/foster/chromeos.c @@ -27,7 +27,7 @@ /* TBD(twarren(a)nvidia.com): Any analogs for these on Foster-FFD? */ struct lb_gpio chromeos_gpios[] = { /* Write Protect: active low */ - {-1, ACTIVE_LOW, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, /* Recovery: active high */ {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, diff --git a/src/mainboard/google/gale/chromeos.c b/src/mainboard/google/gale/chromeos.c index 66b1a62..69c3a7a 100644 --- a/src/mainboard/google/gale/chromeos.c +++ b/src/mainboard/google/gale/chromeos.c @@ -25,9 +25,6 @@ #include <vendorcode/google/chromeos/chromeos.h> #define PP_SW 41 -#define PP_POL ACTIVE_LOW -#define REC_POL ACTIVE_LOW -#define WP_POL ACTIVE_LOW static int get_rec_sw_gpio_pin(void) { @@ -70,11 +67,11 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {PP_SW, PP_POL, read_gpio(PP_SW), "presence"}, - {get_rec_sw_gpio_pin(), REC_POL, + {PP_SW, ACTIVE_LOW, read_gpio(PP_SW), "presence"}, + {get_rec_sw_gpio_pin(), ACTIVE_LOW, read_gpio(get_rec_sw_gpio_pin()), "recovery"}, - {get_wp_status_gpio_pin(), WP_POL, - read_gpio(get_wp_status_gpio_pin()), "write protect"}, + {get_wp_status_gpio_pin(), ACTIVE_LOW, + !get_write_protect_state(), "write protect"}, {-1, ACTIVE_LOW, 1, "power"}, {-1, ACTIVE_LOW, 0, "lid"}, }; @@ -119,7 +116,7 @@ return saved_state; rec_sw = get_rec_sw_gpio_pin(); - sampled_value = read_gpio(rec_sw) ^ !REC_POL; + sampled_value = !read_gpio(rec_sw); if (!sampled_value) { saved_state = no_req; @@ -133,7 +130,7 @@ stopwatch_init_msecs_expire(&sw, WIPEOUT_MODE_DELAY_MS); do { - sampled_value = read_gpio(rec_sw) ^ !REC_POL; + sampled_value = !read_gpio(rec_sw); if (!sampled_value) break; } while (!stopwatch_expired(&sw)); @@ -143,7 +140,7 @@ printk(BIOS_INFO, "wipeout requested, checking recovery\n"); stopwatch_init_msecs_expire(&sw, RECOVERY_MODE_EXTRA_DELAY_MS); do { - sampled_value = read_gpio(rec_sw) ^ !REC_POL; + sampled_value = !read_gpio(rec_sw); if (!sampled_value) break; } while (!stopwatch_expired(&sw)); @@ -175,5 +172,5 @@ int get_write_protect_state(void) { - return read_gpio(get_wp_status_gpio_pin()) ^ !WP_POL; + return !read_gpio(get_wp_status_gpio_pin()); } diff --git a/src/mainboard/google/gru/chromeos.c b/src/mainboard/google/gru/chromeos.c index a856e45..53d00fb 100644 --- a/src/mainboard/google/gru/chromeos.c +++ b/src/mainboard/google/gru/chromeos.c @@ -26,15 +26,14 @@ int get_write_protect_state(void) { - int raw = gpio_get(GPIO_WP); - return wp_polarity == ACTIVE_HIGH ? raw : !raw; + return gpio_get(GPIO_WP) ^ !wp_polarity; } void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {GPIO_WP.raw, wp_polarity, gpio_get(GPIO_WP), - "write protect"}, + {GPIO_WP.raw, wp_polarity, + get_write_protect_state() ^ !wp_polarity, "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, #if CONFIG(GRU_BASEBOARD_SCARLET) {GPIO_BACKLIGHT.raw, ACTIVE_HIGH, -1, "backlight"}, diff --git a/src/mainboard/google/jecht/chromeos.c b/src/mainboard/google/jecht/chromeos.c index c0b14f3..b3215a0 100644 --- a/src/mainboard/google/jecht/chromeos.c +++ b/src/mainboard/google/jecht/chromeos.c @@ -35,9 +35,9 @@ { struct lb_gpio chromeos_gpios[] = { {GPIO_SPI_WP, ACTIVE_HIGH, - get_gpio(GPIO_SPI_WP), "write protect"}, + get_write_protect_state(), "write protect"}, {GPIO_REC_MODE, ACTIVE_LOW, - get_recovery_mode_switch(), "recovery"}, + !get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, 1, "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, diff --git a/src/mainboard/google/nyan/chromeos.c b/src/mainboard/google/nyan/chromeos.c index be1b98d..ba851c7 100644 --- a/src/mainboard/google/nyan/chromeos.c +++ b/src/mainboard/google/nyan/chromeos.c @@ -20,7 +20,8 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {GPIO(R1), ACTIVE_LOW, gpio_get(GPIO(R1)), "write protect"}, + {GPIO(R1), ACTIVE_LOW, !get_write_protect_state(), + "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {GPIO(R4), ACTIVE_HIGH, -1, "lid"}, {GPIO(Q0), ACTIVE_LOW, -1, "power"}, diff --git a/src/mainboard/google/nyan_big/chromeos.c b/src/mainboard/google/nyan_big/chromeos.c index 945a0e7..f297998 100644 --- a/src/mainboard/google/nyan_big/chromeos.c +++ b/src/mainboard/google/nyan_big/chromeos.c @@ -20,7 +20,8 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {GPIO(R1), ACTIVE_LOW, gpio_get(GPIO(R1)), "write protect"}, + {GPIO(R1), ACTIVE_LOW, + !get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {GPIO(R4), ACTIVE_HIGH, -1, "lid"}, {GPIO(Q0), ACTIVE_LOW, -1, "power"}, diff --git a/src/mainboard/google/nyan_blaze/chromeos.c b/src/mainboard/google/nyan_blaze/chromeos.c index 945a0e7..dbbd91f 100644 --- a/src/mainboard/google/nyan_blaze/chromeos.c +++ b/src/mainboard/google/nyan_blaze/chromeos.c @@ -20,7 +20,8 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {GPIO(R1), ACTIVE_LOW, gpio_get(GPIO(R1)), "write protect"}, + {GPIO(R1), ACTIVE_LOW, !get_write_protect_state(), + "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {GPIO(R4), ACTIVE_HIGH, -1, "lid"}, {GPIO(Q0), ACTIVE_LOW, -1, "power"}, diff --git a/src/mainboard/google/oak/chromeos.c b/src/mainboard/google/oak/chromeos.c index b5d7023..4e07236 100644 --- a/src/mainboard/google/oak/chromeos.c +++ b/src/mainboard/google/oak/chromeos.c @@ -35,7 +35,7 @@ { struct lb_gpio chromeos_gpios[] = { {WRITE_PROTECT.id, ACTIVE_LOW, - gpio_get(WRITE_PROTECT), "write protect"}, + !get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {LID.id, ACTIVE_HIGH, -1, "lid"}, {POWER_BUTTON.id, ACTIVE_HIGH, -1, "power"}, diff --git a/src/mainboard/google/peach_pit/chromeos.c b/src/mainboard/google/peach_pit/chromeos.c index f507bd8..00dd1f3 100644 --- a/src/mainboard/google/peach_pit/chromeos.c +++ b/src/mainboard/google/peach_pit/chromeos.c @@ -27,7 +27,7 @@ { struct lb_gpio chromeos_gpios[] = { /* Write Protect: active low (WP_GPIO) */ - {EXYNOS5_GPX3, ACTIVE_LOW, gpio_get_value(GPIO_X30), + {EXYNOS5_GPX3, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, /* Recovery: active low */ diff --git a/src/mainboard/google/sarien/chromeos.c b/src/mainboard/google/sarien/chromeos.c index 2bef829..15670d0 100644 --- a/src/mainboard/google/sarien/chromeos.c +++ b/src/mainboard/google/sarien/chromeos.c @@ -36,7 +36,7 @@ struct lb_gpio chromeos_gpios[] = { {GPIO_PCH_WP, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, - {GPIO_REC_MODE, ACTIVE_LOW, get_recovery_mode_switch(), + {GPIO_REC_MODE, ACTIVE_LOW, !get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, diff --git a/src/mainboard/google/slippy/chromeos.c b/src/mainboard/google/slippy/chromeos.c index 6cae38d..15779ee 100644 --- a/src/mainboard/google/slippy/chromeos.c +++ b/src/mainboard/google/slippy/chromeos.c @@ -24,7 +24,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {58, ACTIVE_HIGH, 0, "write protect"}, + {58, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, get_lid_switch(), "lid"}, {-1, ACTIVE_HIGH, 0, "power"}, diff --git a/src/mainboard/google/smaug/chromeos.c b/src/mainboard/google/smaug/chromeos.c index 86e8cb2..567a3ae 100644 --- a/src/mainboard/google/smaug/chromeos.c +++ b/src/mainboard/google/smaug/chromeos.c @@ -22,7 +22,7 @@ { struct lb_gpio chromeos_gpios[] = { {WRITE_PROTECT_L, ACTIVE_LOW, - gpio_get(WRITE_PROTECT_L), "write protect"}, + !get_write_protect_state(), "write protect"}, {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {POWER_BUTTON, ACTIVE_LOW, -1, "power"}, {EC_IN_RW, ACTIVE_HIGH, -1, "EC in RW"}, diff --git a/src/mainboard/google/storm/chromeos.c b/src/mainboard/google/storm/chromeos.c index b829457..ccc0b53 100644 --- a/src/mainboard/google/storm/chromeos.c +++ b/src/mainboard/google/storm/chromeos.c @@ -25,11 +25,8 @@ #include <vendorcode/google/chromeos/chromeos.h> #define DEV_SW 15 -#define DEV_POL ACTIVE_LOW #define REC_SW 16 -#define REC_POL ACTIVE_LOW #define WP_SW 17 -#define WP_POL ACTIVE_LOW static int read_gpio(gpio_t gpio_num) { @@ -43,7 +40,8 @@ { struct lb_gpio chromeos_gpios[] = { {REC_SW, ACTIVE_LOW, read_gpio(REC_SW), "recovery"}, - {WP_SW, ACTIVE_LOW, read_gpio(WP_SW), "write protect"}, + {WP_SW, ACTIVE_LOW, !get_write_protect_state(), + "write protect"}, {-1, ACTIVE_LOW, 1, "power"}, {-1, ACTIVE_LOW, 0, "lid"}, }; @@ -87,7 +85,7 @@ if (saved_state != not_probed) return saved_state; - sampled_value = read_gpio(REC_SW) ^ !REC_POL; + sampled_value = !read_gpio(REC_SW); if (!sampled_value) { saved_state = no_req; @@ -101,7 +99,7 @@ stopwatch_init_msecs_expire(&sw, WIPEOUT_MODE_DELAY_MS); do { - sampled_value = read_gpio(REC_SW) ^ !REC_POL; + sampled_value = !read_gpio(REC_SW); if (!sampled_value) break; } while (!stopwatch_expired(&sw)); @@ -111,7 +109,7 @@ printk(BIOS_INFO, "wipeout requested, checking recovery\n"); stopwatch_init_msecs_expire(&sw, RECOVERY_MODE_EXTRA_DELAY_MS); do { - sampled_value = read_gpio(REC_SW) ^ !REC_POL; + sampled_value = !read_gpio(REC_SW); if (!sampled_value) break; } while (!stopwatch_expired(&sw)); @@ -143,5 +141,5 @@ int get_write_protect_state(void) { - return read_gpio(WP_SW) ^ !WP_POL; + return !read_gpio(WP_SW); } diff --git a/src/mainboard/google/veyron/chromeos.c b/src/mainboard/google/veyron/chromeos.c index ac14e37..357a7fc 100644 --- a/src/mainboard/google/veyron/chromeos.c +++ b/src/mainboard/google/veyron/chromeos.c @@ -40,9 +40,10 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {GPIO_WP.raw, ACTIVE_LOW, gpio_get(GPIO_WP), "write protect"}, + {GPIO_WP.raw, ACTIVE_LOW, !get_write_protect_state(), + "write protect"}, {GPIO_RECOVERY.raw, ACTIVE_LOW, - get_recovery_mode_switch(), "recovery"}, + !get_recovery_mode_switch(), "recovery"}, {GPIO_LID.raw, ACTIVE_HIGH, -1, "lid"}, {GPIO_POWER.raw, ACTIVE_LOW, -1, "power"}, {GPIO_ECINRW.raw, ACTIVE_HIGH, -1, "EC in RW"}, diff --git a/src/mainboard/google/veyron_mickey/chromeos.c b/src/mainboard/google/veyron_mickey/chromeos.c index c775e48..46a6738 100644 --- a/src/mainboard/google/veyron_mickey/chromeos.c +++ b/src/mainboard/google/veyron_mickey/chromeos.c @@ -31,9 +31,10 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {GPIO_WP.raw, ACTIVE_LOW, gpio_get(GPIO_WP), "write protect"}, + {GPIO_WP.raw, ACTIVE_LOW, + !get_write_protect_state(), "write protect"}, {GPIO_RECOVERY.raw, ACTIVE_LOW, - gpio_get(GPIO_RECOVERY), "recovery"}, + !get_recovery_mode_switch(), "recovery"}, {GPIO_RESET.raw, ACTIVE_HIGH, -1, "reset"}, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); diff --git a/src/mainboard/google/veyron_rialto/chromeos.c b/src/mainboard/google/veyron_rialto/chromeos.c index a0ac77e..e86d863 100644 --- a/src/mainboard/google/veyron_rialto/chromeos.c +++ b/src/mainboard/google/veyron_rialto/chromeos.c @@ -36,7 +36,8 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {GPIO_WP.raw, ACTIVE_LOW, gpio_get(GPIO_WP), "write protect"}, + {GPIO_WP.raw, ACTIVE_LOW, + !get_write_protect_state(), "write protect"}, /* Note for early development, we want to support both servo * and pushkey recovery buttons in firmware boot stages. */ {GPIO_RECOVERY_PUSHKEY.raw, ACTIVE_LOW, diff --git a/src/mainboard/intel/baskingridge/chromeos.c b/src/mainboard/intel/baskingridge/chromeos.c index 0c8d0b2..f1fd3ed 100644 --- a/src/mainboard/intel/baskingridge/chromeos.c +++ b/src/mainboard/intel/baskingridge/chromeos.c @@ -30,7 +30,7 @@ { struct lb_gpio chromeos_gpios[] = { /* Write Protect: GPIO22 */ - {0, ACTIVE_LOW, get_write_protect_state(), "write protect"}, + {0, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, /* Recovery: GPIO69 - SV_DETECT - J8E3 (silkscreen: J8E2) */ {69, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, diff --git a/src/mainboard/intel/emeraldlake2/chromeos.c b/src/mainboard/intel/emeraldlake2/chromeos.c index aa0d9aa..78610d3 100644 --- a/src/mainboard/intel/emeraldlake2/chromeos.c +++ b/src/mainboard/intel/emeraldlake2/chromeos.c @@ -30,10 +30,10 @@ { struct lb_gpio chromeos_gpios[] = { /* Write Protect: GPIO48 */ - {48, ACTIVE_LOW, get_write_protect_state(), "write protect"}, + {48, ACTIVE_LOW, !get_write_protect_state(), "write protect"}, /* Recovery: GPIO22 */ - {22, ACTIVE_LOW, get_recovery_mode_switch(), "recovery"}, + {22, ACTIVE_LOW, !get_recovery_mode_switch(), "recovery"}, /* Hard code the lid switch GPIO to open. */ {-1, ACTIVE_HIGH, 1, "lid"}, diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index 6464ef4..0f5cfbb 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -28,8 +28,8 @@ void fill_lb_gpios(struct lb_gpios *gpios) { struct lb_gpio chromeos_gpios[] = { - {-1, ACTIVE_HIGH, 0, "write protect"}, - {-1, ACTIVE_HIGH, REC_MODE_SETTING, "recovery"}, + {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"}, + {-1, ACTIVE_HIGH, get_recovery_mode_switch(), "recovery"}, {-1, ACTIVE_HIGH, 1, "lid"}, // force open {-1, ACTIVE_HIGH, 0, "power"}, {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"}, -- To view, visit https://review.coreboot.org/c/coreboot/+/32233 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic17a98768703d7098480a9233b752fe5b201bd51 Gerrit-Change-Number: 32233 Gerrit-PatchSet: 1 Gerrit-Owner: Joel Kitching <kitching(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: google/kukui: Use internal CR50_IRQ pull-up
by You-Cheng Syu (Code Review) 11 Apr '19

11 Apr '19

You-Cheng Syu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32116 Change subject: google/kukui: Use internal CR50_IRQ pull-up ...................................................................... google/kukui: Use internal CR50_IRQ pull-up For Kukui CR50_IRQ pin, we're going to replace external pull-up with internal pull-up. This change won't break older boards, so we can just always do that when setting up GPIOs. BUG=b:124821269 BRANCH=none TEST=Waveform looks correct. Change-Id: Ib1a90dce583a6aa0cec8ac8ba96d1362f50c16a8 Signed-off-by: You-Cheng Syu <youcheng(a)google.com> --- M src/mainboard/google/kukui/chromeos.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/32116/1 diff --git a/src/mainboard/google/kukui/chromeos.c b/src/mainboard/google/kukui/chromeos.c index 132f0d3..09c47ee 100644 --- a/src/mainboard/google/kukui/chromeos.c +++ b/src/mainboard/google/kukui/chromeos.c @@ -24,6 +24,7 @@ { gpio_input_pullup(EC_IN_RW); gpio_input_pullup(EC_IRQ); + gpio_input_pullup(CR50_IRQ); gpio_output(GPIO_RESET, 0); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32116 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1a90dce583a6aa0cec8ac8ba96d1362f50c16a8 Gerrit-Change-Number: 32116 Gerrit-PatchSet: 1 Gerrit-Owner: You-Cheng Syu <youcheng(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit April 2019