coreboot-gerrit April 2019

coreboot-gerrit@coreboot.org

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1219 discussions

Change in ...coreboot[master]: mb/google/hatch: Use GPIO IRQ for sx9310 device
by Furquan Shaikh (Code Review) 12 Apr '19

12 Apr '19

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32270 Change subject: mb/google/hatch: Use GPIO IRQ for sx9310 device ...................................................................... mb/google/hatch: Use GPIO IRQ for sx9310 device This change uses GPIO IRQ instead of IOAPIC for GPP_A0 pad which is the interrupt line for sx9310. This is required because IRQ# used by GPP_A0 is allocated for PIRQ which does not allow IRQ# sharing. Additionally, this change also configures GPP_A6 for GPIO IRQ. GPP_A6 is currently unused in the devicetree. BUG=b:129794308 TEST=Verified that there are no interrupt storms on GPP_A0. Change-Id: Ibb510a647391c0d9cb854d23656bb4b1cb7756ab Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c M src/mainboard/google/hatch/variants/hatch/overridetree.cb M src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb 3 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/32270/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 1c8cfba..eaa8dd3 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -20,14 +20,14 @@ static const struct pad_config gpio_table[] = { /* A0 : SAR0_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A0, NONE, PLTRST, LEVEL, NONE), + PAD_CFG_GPI_INT(GPP_A0, NONE, PLTRST, LEVEL), /* A1 : ESPI_IO0 */ /* A2 : ESPI_IO1 */ /* A3 : ESPI_IO2 */ /* A4 : ESPI_IO3 */ /* A5 : ESPI_CS# */ /* A6 : SAR1_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A6, NONE, PLTRST, LEVEL, NONE), + PAD_CFG_GPI_INT(GPP_A6, NONE, PLTRST, LEVEL), /* A7 : PP3300_SOC_A */ PAD_NC(GPP_A7, NONE), /* A8 : EMR_GARAGE_DET */ diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index 28644d1..bdc0256 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -83,7 +83,7 @@ device pci 15.3 on chip drivers/i2c/sx9310 register "desc" = ""SAR Proximity Sensor"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A0_IRQ)" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A0)" register "speed" = "I2C_SPEED_FAST" register "uid" = "1" register "reg_prox_ctrl0" = "0x10" diff --git a/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb b/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb index 9b772c2..dad372f 100644 --- a/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb @@ -68,7 +68,7 @@ device pci 15.3 on chip drivers/i2c/sx9310 register "desc" = ""SAR Proximity Sensor"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A0_IRQ)" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A0)" register "speed" = "I2C_SPEED_FAST" register "uid" = "1" register "reg_prox_ctrl0" = "0x10" -- To view, visit https://review.coreboot.org/c/coreboot/+/32270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibb510a647391c0d9cb854d23656bb4b1cb7756ab Gerrit-Change-Number: 32270 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: drivers/i2c/sx9310: Add support for GPIO IRQ
by Furquan Shaikh (Code Review) 12 Apr '19

12 Apr '19

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32273 Change subject: drivers/i2c/sx9310: Add support for GPIO IRQ ...................................................................... drivers/i2c/sx9310: Add support for GPIO IRQ This change adds support for mainboards to use GPIO IRQ instead of IOAPIC to accomodate for cases where IOAPIC routing might not be available for certain pads. BUG=b:129794308 Change-Id: I3e2bb4280303cea177cc0c803d29140731e2b44a Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/drivers/i2c/sx9310/chip.h M src/drivers/i2c/sx9310/sx9310.c 2 files changed, 20 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/32273/1 diff --git a/src/drivers/i2c/sx9310/chip.h b/src/drivers/i2c/sx9310/chip.h index 2799f5b..c99a8a1 100644 --- a/src/drivers/i2c/sx9310/chip.h +++ b/src/drivers/i2c/sx9310/chip.h @@ -22,10 +22,20 @@ #define REGISTER(NAME) uint8_t NAME struct drivers_i2c_sx9310_config { - const char *desc; /* Device Description */ - unsigned int uid; /* ACPI _UID */ - enum i2c_speed speed; /* Bus speed in Hz, default is I2C_SPEED_FAST */ - struct acpi_irq irq; /* Interrupt */ + /* Device Description */ + const char *desc; + + /* ACPI _UID */ + unsigned int uid; + + /* Bus speed in Hz, default is I2C_SPEED_FAST */ + enum i2c_speed speed; + + /* Use GPIO-based interrupt instead of IO-APIC */ + struct acpi_gpio irq_gpio; + + /* IO-APIC interrupt */ + struct acpi_irq irq; #include "registers.h" }; diff --git a/src/drivers/i2c/sx9310/sx9310.c b/src/drivers/i2c/sx9310/sx9310.c index afd9e35..aafd7c7 100644 --- a/src/drivers/i2c/sx9310/sx9310.c +++ b/src/drivers/i2c/sx9310/sx9310.c @@ -59,7 +59,12 @@ acpigen_write_name("_CRS"); acpigen_write_resourcetemplate_header(); acpi_device_write_i2c(&i2c); - acpi_device_write_interrupt(&config->irq); + + if (config->irq_gpio.pin_count) + acpi_device_write_gpio(&config->irq_gpio); + else + acpi_device_write_interrupt(&config->irq); + acpigen_write_resourcetemplate_footer(); /* DSD */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32273 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3e2bb4280303cea177cc0c803d29140731e2b44a Gerrit-Change-Number: 32273 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Configure reset config to PLTRST for IOAPIC pads
by Furquan Shaikh (Code Review) 12 Apr '19

12 Apr '19

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32268 Change subject: mb/google/hatch: Configure reset config to PLTRST for IOAPIC pads ...................................................................... mb/google/hatch: Configure reset config to PLTRST for IOAPIC pads This change configures reset config for all pads routed to IOAPIC as PLTRST. This is required to ensure that the internal logic of the GPIO gets reset any time the platform enters S3 or powers off and avoids any interrupt storms on boot-up. BUG=b:129933011 TEST=Verified that there are no interrupt storms on boot-up from S5. Change-Id: Ib790280c9f1410fa18746d4d7d2a5027afd7585b Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/hatch/variants/baseboard/gpio.c 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/32268/1 diff --git a/src/mainboard/google/hatch/variants/baseboard/gpio.c b/src/mainboard/google/hatch/variants/baseboard/gpio.c index 0391dfe..1c8cfba 100644 --- a/src/mainboard/google/hatch/variants/baseboard/gpio.c +++ b/src/mainboard/google/hatch/variants/baseboard/gpio.c @@ -20,14 +20,14 @@ static const struct pad_config gpio_table[] = { /* A0 : SAR0_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A0, NONE, DEEP, LEVEL, NONE), + PAD_CFG_GPI_APIC(GPP_A0, NONE, PLTRST, LEVEL, NONE), /* A1 : ESPI_IO0 */ /* A2 : ESPI_IO1 */ /* A3 : ESPI_IO2 */ /* A4 : ESPI_IO3 */ /* A5 : ESPI_CS# */ /* A6 : SAR1_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A6, NONE, DEEP, LEVEL, NONE), + PAD_CFG_GPI_APIC(GPP_A6, NONE, PLTRST, LEVEL, NONE), /* A7 : PP3300_SOC_A */ PAD_NC(GPP_A7, NONE), /* A8 : EMR_GARAGE_DET */ @@ -53,7 +53,7 @@ /* A19 : WWAN_RADIO_DISABLE_1V8_ODL */ PAD_CFG_GPO(GPP_A19, 1, DEEP), /* A20 : M2_INT_L */ - PAD_CFG_GPI_APIC(GPP_A20, NONE, DEEP, LEVEL, NONE), + PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST, LEVEL, NONE), /* * A21 : TRACKPAD_INT_ODL (wake) * TODO Combine into single gpio, when ITSS IPCx configuration @@ -147,7 +147,7 @@ * TODO Configure it back to invert mode, when * ITSS IPCx configuration is fixed in FSP. */ - PAD_CFG_GPI_APIC(GPP_C13, NONE, DEEP, LEVEL, NONE), + PAD_CFG_GPI_APIC(GPP_C13, NONE, PLTRST, LEVEL, NONE), /* C14 : BT_DISABLE_L */ PAD_CFG_GPO(GPP_C14, 1, DEEP), /* C15 : WWAN_DPR_SAR_ODL @@ -171,7 +171,7 @@ * TODO Configure it back to invert mode, when * ITSS IPCx configuration is fixed in FSP. */ - PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, NONE), + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, NONE), /* C22 : EC_IN_RW_OD */ PAD_CFG_GPI(GPP_C22, NONE, DEEP), /* C23 : WLAN_PE_RST# */ @@ -210,7 +210,7 @@ /* D15 : TOUCHSCREEN_RST_L */ PAD_CFG_GPO(GPP_D15, 0, DEEP), /* D16 : USI_INT */ - PAD_CFG_GPI_APIC(GPP_D16, NONE, DEEP, LEVEL, NONE), + PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, NONE), /* D17 : PCH_HP_SDW_CLK */ PAD_NC(GPP_D17, NONE), /* D18 : PCH_HP_SDW_DAT */ @@ -457,7 +457,7 @@ * TODO Configure it back to invert mode, when * ITSS IPCx configuration is fixed in FSP. */ - PAD_CFG_GPI_APIC(GPP_C21, NONE, DEEP, LEVEL, NONE), + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, NONE), /* C23 : WLAN_PE_RST# */ PAD_CFG_GPO(GPP_C23, 1, DEEP), /* F2 : MEM_CH_SEL */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32268 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib790280c9f1410fa18746d4d7d2a5027afd7585b Gerrit-Change-Number: 32268 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/cannonlake: Do not use XIP_ROM_SIZE
by Furquan Shaikh (Code Review) 12 Apr '19

12 Apr '19

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32258 Change subject: soc/intel/cannonlake: Do not use XIP_ROM_SIZE ...................................................................... soc/intel/cannonlake: Do not use XIP_ROM_SIZE XIP_ROM_SIZE Kconfig option isn't used on Cannon Lake and family. Thus, this change selects NO_FIXED_XIP_ROM_SIZE to indicate to build system so that romstage can be placed in less rigid manner. BUG=b:129802811 Change-Id: I5f3786396246c89b1039ba1b6b332a32e6a0345d Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/cannonlake/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/32258/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 9796546..55fef5a 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -70,6 +70,7 @@ select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select IOAPIC select MRC_SETTINGS_PROTECT + select NO_FIXED_XIP_ROM_SIZE select PARALLEL_MP select PARALLEL_MP_AP_WORK select PLATFORM_USES_FSP2_0 -- To view, visit https://review.coreboot.org/c/coreboot/+/32258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f3786396246c89b1039ba1b6b332a32e6a0345d Gerrit-Change-Number: 32258 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Skip UART0 config in FSP
by Furquan Shaikh (Code Review) 12 Apr '19

12 Apr '19

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32278 Change subject: mb/google/hatch: Skip UART0 config in FSP ...................................................................... mb/google/hatch: Skip UART0 config in FSP UART0 is already configured in coreboot, so this change sets SerialIo config for UART0 to PchSerialIoSkipInit to skip initialization in FSP. BUG=b:130325418 Change-Id: Ifc88f4fa11bff2144417d5194776c15f9f7b60ac Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/hatch/variants/hatch/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/32278/1 diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index bdc0256..5492379 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -10,7 +10,7 @@ [PchSerialIoIndexSPI0] = PchSerialIoPci, [PchSerialIoIndexSPI1] = PchSerialIoPci, [PchSerialIoIndexSPI2] = PchSerialIoDisabled, - [PchSerialIoIndexUART0] = PchSerialIoPci, + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, [PchSerialIoIndexUART1] = PchSerialIoDisabled, [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/32278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifc88f4fa11bff2144417d5194776c15f9f7b60ac Gerrit-Change-Number: 32278 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: superio: Add ASpeed AST2400
by Felix Singer (Code Review) 12 Apr '19

12 Apr '19

Felix Singer has uploaded a new patch set (#14) to the change originally created by Frans Hendriks. ( https://review.coreboot.org/c/coreboot/+/23135 ) Change subject: superio: Add ASpeed AST2400 ...................................................................... superio: Add ASpeed AST2400 Add support for ASpeed AST2400. This device uses write twice 0xA5 to enter config mode. BUG = N/A TEST = ASRock D1521D4U Change-Id: I58fce31f0a2483e61e9d31f38ab5a059b8cf4f83 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de> --- M src/include/superio/conf_mode.h M src/superio/Makefile.inc A src/superio/aspeed/Makefile.inc A src/superio/aspeed/ast2400/Kconfig A src/superio/aspeed/ast2400/Makefile.inc A src/superio/aspeed/ast2400/ast2400.h A src/superio/aspeed/ast2400/superio.c A src/superio/aspeed/common/Kconfig A src/superio/aspeed/common/aspeed.h A src/superio/aspeed/common/early_serial.c M src/superio/common/conf_mode.c 11 files changed, 312 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/23135/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/23135 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58fce31f0a2483e61e9d31f38ab5a059b8cf4f83 Gerrit-Change-Number: 23135 Gerrit-PatchSet: 14 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/gigabyte/ga-h61ma-d3v: Add new mainboard as variant
by Angel Pons (Code Review) 11 Apr '19

11 Apr '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31832 ) Change subject: mb/gigabyte/ga-h61ma-d3v: Add new mainboard as variant ...................................................................... Patch Set 6: (1 comment) Oops. https://review.coreboot.org/#/c/31832/6/src/mainboard/gigabyte/ga-h61m-s2pv… File src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig: https://review.coreboot.org/#/c/31832/6/src/mainboard/gigabyte/ga-h61m-s2pv… PS6, Line 57: H61MA_D3V s/_/- -- To view, visit https://review.coreboot.org/c/coreboot/+/31832 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37928de158bb8fbb47fbda5d1ccd4efba7edab26 Gerrit-Change-Number: 31832 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 11 Apr 2019 21:43:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: mb/gigabyte/ga-h61ma-d3v: Add new mainboard as variant
by Angel Pons (Code Review) 11 Apr '19

11 Apr '19

Hello Arthur Heymans, Paul Menzel, build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/31832 to look at the new patch set (#6). Change subject: mb/gigabyte/ga-h61ma-d3v: Add new mainboard as variant ...................................................................... mb/gigabyte/ga-h61ma-d3v: Add new mainboard as variant Tested with SeaBIOS as a payload, booting Arch Linux with a Linux kernel. The new code is based on autoport and the existing GA-H61M-S2PV code. The GA-H61M-S2PV has been boot-tested too, it still boots. Working: - S3 suspend/resume - USB ports and headers (Intel USB2 and EtronTech USB3) - Gigabit Ethernet - Integrated DVI/VGA graphics (libgfxinit) - PCIe x16 graphics - PCIe x1 ports - PS/2 port with a keyboard - SATA controllers (Intel SATA2 and Marvell SATA3) - Fan Control (fancontrol on linux works well) - Native raminit (4+4GB DDR3-1333) - flashrom, using the internal programmer. Tested with coreboot, as well as with the vendor firmware. Backup chip is untested. Untested: - VGA BIOS for integrated graphics init - Audio: Only front/read outputs has been tested. - Non-Linux OSes - ACPI thermal zone and fan control Not working: - Default IFD defines the BIOS region as the entire flash chip. Care should be taken when using flashrom and ifd-as-layout! Change-Id: I37928de158bb8fbb47fbda5d1ccd4efba7edab26 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig M src/mainboard/gigabyte/ga-h61m-s2pv/Kconfig.name M src/mainboard/gigabyte/ga-h61m-s2pv/Makefile.inc M src/mainboard/gigabyte/ga-h61m-s2pv/hda_verb.c M src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c R src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/devicetree.cb R src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/gpio.c A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61m-s2pv/hda_verb.c A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/gpio.c A src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/hda_verb.c 11 files changed, 435 insertions(+), 81 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/31832/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/31832 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37928de158bb8fbb47fbda5d1ccd4efba7edab26 Gerrit-Change-Number: 31832 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: mb/gigabyte/ga-h61ma-d3v: Add new mainboard as variant
by Angel Pons (Code Review) 11 Apr '19

11 Apr '19

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31832 ) Change subject: mb/gigabyte/ga-h61ma-d3v: Add new mainboard as variant ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/31832/5/src/mainboard/gigabyte/ga-h61m-s2pv… File src/mainboard/gigabyte/ga-h61m-s2pv/variants/ga-h61ma-d3v/devicetree.cb: https://review.coreboot.org/#/c/31832/5/src/mainboard/gigabyte/ga-h61m-s2pv… PS5, Line 83: irq 0x62 = 0x0a > Looks like there are 2 i/o resources missing around this […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/31832 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I37928de158bb8fbb47fbda5d1ccd4efba7edab26 Gerrit-Change-Number: 31832 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 11 Apr 2019 21:39:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in ...coreboot[master]: sdm845: Add QCLib to RomStage to perform IP init
by build bot (Jenkins) (Code Review) 11 Apr '19

11 Apr '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25208 ) Change subject: sdm845: Add QCLib to RomStage to perform IP init ...................................................................... Patch Set 72: (2 comments) https://review.coreboot.org/#/c/25208/72/src/soc/qualcomm/sdm845/soc_blob_l… File src/soc/qualcomm/sdm845/soc_blob_load.c: https://review.coreboot.org/#/c/25208/72/src/soc/qualcomm/sdm845/soc_blob_l… PS72, Line 29: printk(BIOS_INFO, "soc_blob_load(sdm845)\n"); Prefer using '"%s...", __func__' to using 'soc_blob_load', this function's name, in a string https://review.coreboot.org/#/c/25208/72/src/soc/qualcomm/sdm845/soc_blob_l… PS72, Line 57: die("Couldn't run soc_blob_load.\n"); Prefer using '"%s...", __func__' to using 'soc_blob_load', this function's name, in a string -- To view, visit https://review.coreboot.org/c/coreboot/+/25208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I073186674a1a593547d1ee1d15c7cd4fd8ad5bc1 Gerrit-Change-Number: 25208 Gerrit-PatchSet: 72 Gerrit-Owner: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: T Michael Turney <mturney(a)codeaurora.org> Gerrit-Reviewer: T.Michael Turney <tturne(a)codeaurora.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Comment-Date: Thu, 11 Apr 2019 21:13:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit April 2019