Philipp Deppenwiese has uploaded a new patch set (#7) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/31548 )
Change subject: security: Add memory subfolder
......................................................................
security: Add memory subfolder
Add files to introduce a memory clearing framework.
Introduce Kconfig PLATFORM_HAS_DRAM_CLEAR that is to be selected by
platforms, that are able to clear all DRAM.
Introduce Kconfig SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT that is user
selectable to always clear DRAM on non S3 boot.
The function security_clear_dram_request tells the calling platform when
to wipe all DRAM. Will be extended by TEE frameworks.
Add Documentation for the new security API.
Change-Id: Ifba25bfdd1057049f5cbae8968501bd9be487110
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M Documentation/index.md
M Documentation/security/index.md
A Documentation/security/memory_clearing.md
M src/security/Kconfig
M src/security/Makefile.inc
A src/security/memory/Kconfig
A src/security/memory/Makefile.inc
A src/security/memory/memory.c
A src/security/memory/memory.h
9 files changed, 131 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/31548/7
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Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31548 )
Change subject: security: Add memory subfolder
......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/31548/5/Documentation/security/memory_clear…
File Documentation/security/memory_clearing.md:
https://review.coreboot.org/#/c/31548/5/Documentation/security/memory_clear…
PS5, Line 22: 4. All DRAM is cleared with zeros
> Can you elaborate, why 0 is the way to go and not something random?
Because DRAM is initialized in a random way anyway. We are not on a harddrive here ;)
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Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23135 )
Change subject: superio: Add ASpeed AST2400
......................................................................
Patch Set 20:
(2 comments)
https://review.coreboot.org/#/c/23135/20/src/superio/aspeed/ast2400/Kconfig
File src/superio/aspeed/ast2400/Kconfig:
https://review.coreboot.org/#/c/23135/20/src/superio/aspeed/ast2400/Kconfig…
PS20, Line 19: bool
default n
https://review.coreboot.org/#/c/23135/20/src/superio/aspeed/common/Kconfig
File src/superio/aspeed/common/Kconfig:
https://review.coreboot.org/#/c/23135/20/src/superio/aspeed/common/Kconfig@…
PS20, Line 21: bool
default n
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/27532 )
Change subject: nb/intel/sandybridge: Remove the C native graphic init
......................................................................
Patch Set 11:
I think this patch orphaned code in src/mainboard/google/link/i915.c, and (presumably) broke Link when selecting DO_NATIVE_VGA_INIT in menuconfig. If the intention was to get rid of that option entirely, can you please remove HAS_NATIVE_VGA_INIT and any associated code from affected boards?
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Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32275
Change subject: soc/intel/cannonlake: Select FSP_M_XIP
......................................................................
soc/intel/cannonlake: Select FSP_M_XIP
Cannon lake and family require that FSP-M component should be
XIP. This change selects FSP_M_XIP so that the right arguments are
passed into cbfstool when adding this component.
BUG=b:130306520
TEST=Verified that hatch boots fine to OS.
Change-Id: Ifd8a829ebdc7681c81ece4540aa38cdcea7b6fac
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
M src/soc/intel/cannonlake/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/32275/1
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index 55fef5a..c30b562 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -60,6 +60,7 @@
select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
select COMMON_FADT
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
+ select FSP_M_XIP
select GENERIC_GPIO_LIB
select HAVE_FSP_GOP
select INTEL_DESCRIPTOR_MODE_CAPABLE
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Felix Singer has uploaded a new patch set (#20) to the change originally created by Frans Hendriks. ( https://review.coreboot.org/c/coreboot/+/23135 )
Change subject: superio: Add ASpeed AST2400
......................................................................
superio: Add ASpeed AST2400
Add support for ASpeed AST2400.
This device uses write twice 0xA5 to enter config mode.
BUG = N/A
TEST = ASRock D1521D4U
Change-Id: I58fce31f0a2483e61e9d31f38ab5a059b8cf4f83
Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com>
Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de>
---
M src/include/superio/conf_mode.h
M src/superio/Makefile.inc
A src/superio/aspeed/Makefile.inc
A src/superio/aspeed/ast2400/Kconfig
A src/superio/aspeed/ast2400/Makefile.inc
A src/superio/aspeed/ast2400/ast2400.h
A src/superio/aspeed/ast2400/superio.c
A src/superio/aspeed/common/Kconfig
A src/superio/aspeed/common/aspeed.h
A src/superio/aspeed/common/early_serial.c
M src/superio/common/conf_mode.c
11 files changed, 310 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/23135/20
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23135 )
Change subject: superio: Add ASpeed AST2400
......................................................................
Patch Set 19:
(4 comments)
https://review.coreboot.org/#/c/23135/17/src/superio/aspeed/ast2400/ast2400…
File src/superio/aspeed/ast2400/ast2400.h:
https://review.coreboot.org/#/c/23135/17/src/superio/aspeed/ast2400/ast2400…
PS17, Line 21: #include <arch/io.h>
> no need for arch/io. […]
Done
https://review.coreboot.org/#/c/23135/17/src/superio/aspeed/ast2400/ast2400…
PS17, Line 22: #include <superio/aspeed/common/aspeed.h>
> why include it here if it's only linked in romstage?
Done
https://review.coreboot.org/#/c/23135/17/src/superio/aspeed/ast2400/ast2400…
PS17, Line 32: #define AST2400_MAILBOX 0xE /* Mailbox */
> one more tab to align with ILPC2AHB
Done
https://review.coreboot.org/#/c/23135/17/src/superio/aspeed/common/aspeed.h
File src/superio/aspeed/common/aspeed.h:
https://review.coreboot.org/#/c/23135/17/src/superio/aspeed/common/aspeed.h…
PS17, Line 21: #include <arch/io.h>
> no need for arch/io. […]
Done
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Felix Singer has uploaded a new patch set (#19) to the change originally created by Frans Hendriks. ( https://review.coreboot.org/c/coreboot/+/23135 )
Change subject: superio: Add ASpeed AST2400
......................................................................
superio: Add ASpeed AST2400
Add support for ASpeed AST2400.
This device uses write twice 0xA5 to enter config mode.
BUG = N/A
TEST = ASRock D1521D4U
Change-Id: I58fce31f0a2483e61e9d31f38ab5a059b8cf4f83
Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com>
Signed-off-by: Felix Singer <migy(a)darmstadt.ccc.de>
---
M src/include/superio/conf_mode.h
M src/superio/Makefile.inc
A src/superio/aspeed/Makefile.inc
A src/superio/aspeed/ast2400/Kconfig
A src/superio/aspeed/ast2400/Makefile.inc
A src/superio/aspeed/ast2400/ast2400.h
A src/superio/aspeed/ast2400/superio.c
A src/superio/aspeed/common/Kconfig
A src/superio/aspeed/common/aspeed.h
A src/superio/aspeed/common/early_serial.c
M src/superio/common/conf_mode.c
11 files changed, 311 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/23135/19
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23135 )
Change subject: superio: Add ASpeed AST2400
......................................................................
Patch Set 18:
(3 comments)
https://review.coreboot.org/#/c/23135/17/src/superio/aspeed/Makefile.inc
File src/superio/aspeed/Makefile.inc:
https://review.coreboot.org/#/c/23135/17/src/superio/aspeed/Makefile.inc@17
PS17, Line 17: fintek
> aspeed
Done
https://review.coreboot.org/#/c/23135/17/src/superio/aspeed/Makefile.inc@18
PS17, Line 18: romstage-$(CONFIG_SUPERIO_ASPEED_COMMON_ROMSTAGE) += common/early_serial.c
> also link it in the bootblock, as with C_ENVIRONMENT_BOOTBLOCK you want serial output there too.
Done
https://review.coreboot.org/#/c/23135/17/src/superio/aspeed/common/Kconfig
File src/superio/aspeed/common/Kconfig:
https://review.coreboot.org/#/c/23135/17/src/superio/aspeed/common/Kconfig@…
PS17, Line 20: ROMSTAGE
> PRE_RAM
Done
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