coreboot-gerrit April 2019

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Change in ...coreboot[master]: src/arch/x86/acpi.c: Update SRAT revision number
by HAOUAS Elyes (Code Review) 13 Apr '19

13 Apr '19

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31565 Change subject: src/arch/x86/acpi.c: Update SRAT revision number ...................................................................... src/arch/x86/acpi.c: Update SRAT revision number We currently use ACPI v3.0, so the SRAT revision number is "2". Change-Id: I14311029c887a2260c3a93d0b7fca6e8d546edd0 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/acpi.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/31565/1 diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index 6396877..fc9dfe1 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -1383,8 +1383,8 @@ return 4; case SSDT: /* ACPI 3.0 upto 6.3: 2 */ return 2; - case SRAT: /* ACPI 2.0: 1, ACPI 3.0: 2, ACPI 4.0 upto 6.3: 3 */ - return 1; /* TODO Should probably be upgraded to 2 */ + case SRAT: /* ACPI 3.0: 2, ACPI 4.0 upto 6.3: 3 */ + return 2; case DMAR: return 1; case SLIT: /* ACPI 2.0 upto 6.3: 1 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/31565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I14311029c887a2260c3a93d0b7fca6e8d546edd0 Gerrit-Change-Number: 31565 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: superio: Add ASpeed AST2400
by Kyösti Mälkki (Code Review) 13 Apr '19

13 Apr '19

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/23135 ) Change subject: superio: Add ASpeed AST2400 ...................................................................... Patch Set 20: (5 comments) https://review.coreboot.org/#/c/23135/20/src/superio/aspeed/Makefile.inc File src/superio/aspeed/Makefile.inc: https://review.coreboot.org/#/c/23135/20/src/superio/aspeed/Makefile.inc@18 PS20, Line 18: bootblock-$(CONFIG_C_ENVIRONMENT_BOOTBLOCK) += common/early_serial.c .. COMMON_PRE_RAM https://review.coreboot.org/#/c/23135/20/src/superio/aspeed/Makefile.inc@21 PS20, Line 21: romstage-$(CONFIG_SUPERIO_ASPEED_COMMON_ROMSTAGE) += common/early_serial.c ..COMMON_PRE_RAM https://review.coreboot.org/#/c/23135/20/src/superio/aspeed/ast2400/ast2400… File src/superio/aspeed/ast2400/ast2400.h: https://review.coreboot.org/#/c/23135/20/src/superio/aspeed/ast2400/ast2400… PS20, Line 31: void pnp_enter_ext_func_mode(pnp_devfn_t dev); <device/pnp_type.h> https://review.coreboot.org/#/c/23135/20/src/superio/aspeed/ast2400/ast2400… PS20, Line 34: void aspeed2400_enable_serial(u16 port, u16 device, u16 iobase); <stdint.h> ? https://review.coreboot.org/#/c/23135/20/src/superio/aspeed/common/early_se… File src/superio/aspeed/common/early_serial.c: https://review.coreboot.org/#/c/23135/20/src/superio/aspeed/common/early_se… PS20, Line 50: outb(ASPEED_ENTRY_KEY, port); You want <arch/io.h> for this. -- To view, visit https://review.coreboot.org/c/coreboot/+/23135 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58fce31f0a2483e61e9d31f38ab5a059b8cf4f83 Gerrit-Change-Number: 23135 Gerrit-PatchSet: 20 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Comment-Date: Sat, 13 Apr 2019 07:07:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: [Test] Remaining unused variables
by HAOUAS Elyes (Code Review) 13 Apr '19

13 Apr '19

HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29926 ) Change subject: [Test] Remaining unused variables ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/29926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic3dde296ab4b84add8a8ab6a3bb5ecb65da2c158 Gerrit-Change-Number: 29926 Gerrit-PatchSet: 22 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: src/Kconfig: Unhide SMBIOS_ENCLOSURE_TYPE field
by HAOUAS Elyes (Code Review) 13 Apr '19

13 Apr '19

HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/29825 ) Change subject: src/Kconfig: Unhide SMBIOS_ENCLOSURE_TYPE field ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/29825 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifea2376e5abd44232c80daa73e480e695de7d87c Gerrit-Change-Number: 29825 Gerrit-PatchSet: 3 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: soc/intel/../../cpu: Remove redundent enable/disable functions
by Subrata Banik (Code Review) 13 Apr '19

13 Apr '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32282 Change subject: soc/intel/../../cpu: Remove redundent enable/disable functions ...................................................................... soc/intel/../../cpu: Remove redundent enable/disable functions This patch removes multiple enable/disable function definitions and make use of single function with argument to know feature status (enable/disable). Change-Id: I502cd2497b07e9de062df453ecbb9c11df692f5a Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/apollolake/cpu.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/cannonlake/cpu.c M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/cpulib.h M src/soc/intel/icelake/cpu.c 6 files changed, 34 insertions(+), 56 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/32282/1 diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 8f1d933..488b02e 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -94,10 +94,12 @@ /* Set Max Non-Turbo ratio if RAPL is disabled. */ if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) { cpu_set_p_state_to_max_non_turbo_ratio(); - cpu_disable_eist(); + /* Disable speed step */ + cpu_set_eist(FALSE); } else if (CONFIG(APL_SET_MIN_CLOCK_RATIO)) { cpu_set_p_state_to_min_clock_ratio(); - cpu_disable_eist(); + /* Disable speed step */ + cpu_set_eist(FALSE); } } diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 47fbc0d..e8c27d8 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -197,10 +197,10 @@ } /* Enable burst mode */ - cpu_enable_burst_mode(); + cpu_burst_mode(TRUE); /* Enable speed step. */ - cpu_enable_eist(); + cpu_set_eist(TRUE); /* Set P-State ratio */ cpu_set_p_state_to_turbo_ratio(); diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 7c06d25..01386dd 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -269,10 +269,8 @@ msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - if (conf && conf->eist_enable) - cpu_enable_eist(); - else - cpu_disable_eist(); + /* Set EIST status */ + cpu_set_eist(conf->eist_enable); wrmsr(IA32_MISC_ENABLE, msr); /* Disable Thermal interrupts */ diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 9964f2b..b0061cc 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -185,50 +185,36 @@ } /* - * Enable Burst mode. + * Program CPU Burst mode + * TRUE = Enable Burst mode. + * FALSE = Disable Burst mode. */ -void cpu_enable_burst_mode(void) +void cpu_burst_mode(bool burst_mode_status) { msr_t msr; msr = rdmsr(IA32_MISC_ENABLE); - msr.hi &= ~BURST_MODE_DISABLE; + if (burst_mode_status) + msr.hi &= ~BURST_MODE_DISABLE; + else + msr.hi |= BURST_MODE_DISABLE; wrmsr(IA32_MISC_ENABLE, msr); } /* - * Disable Burst mode. + * Program Enhanced Intel Speed Step Technology + * TRUE = Enable EIST. + * FALSE = Disable EIST. */ -void cpu_disable_burst_mode(void) +void cpu_set_eist(bool eist_status) { msr_t msr; msr = rdmsr(IA32_MISC_ENABLE); - msr.hi |= BURST_MODE_DISABLE; - wrmsr(IA32_MISC_ENABLE, msr); -} - -/* - * Enable Intel Enhanced Speed Step Technology. - */ -void cpu_enable_eist(void) -{ - msr_t msr; - - msr = rdmsr(IA32_MISC_ENABLE); - msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ - wrmsr(IA32_MISC_ENABLE, msr); -} - -/* - * Disable Intel Enhanced Speed Step Technology. - */ -void cpu_disable_eist(void) -{ - msr_t msr; - - msr = rdmsr(IA32_MISC_ENABLE); - msr.lo &= ~(1 << 16); /* Enhanced SpeedStep Disable */ + if (eist_status) + msr.lo |= (1 << 16); + else + msr.lo &= ~(1 << 16); wrmsr(IA32_MISC_ENABLE, msr); } diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index 5cea96e..23d9909 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -97,24 +97,18 @@ int cpu_get_burst_mode_state(void); /* - * Enable Burst mode. + * Program CPU Burst mode + * TRUE = Enable Burst mode. + * FALSE = Disable Burst mode. */ -void cpu_enable_burst_mode(void); +void cpu_burst_mode(bool burst_mode_status); /* - * Disable Burst mode. + * Program Enhanced Intel Speed Step Technology + * TRUE = Enable EIST. + * FALSE = Disable EIST. */ -void cpu_disable_burst_mode(void); - -/* - * Enable Intel Enhanced Speed Step Technology. - */ -void cpu_enable_eist(void); - -/* - * Disable Intel Enhanced Speed Step Technology. - */ -void cpu_disable_eist(void); +void cpu_set_eist(bool eist_status); /* * Set Bit 6 (ENABLE_IA_UNTRUSTED_MODE) of MSR 0x120 diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index f4ebacf..62bcff6 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -73,10 +73,8 @@ msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ - if (conf->eist_enable) - cpu_enable_eist(); - else - cpu_disable_eist(); + /* Set EIST status */ + cpu_set_eist(conf->eist_enable); wrmsr(IA32_MISC_ENABLE, msr); /* Disable Thermal interrupts */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32282 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I502cd2497b07e9de062df453ecbb9c11df692f5a Gerrit-Change-Number: 32282 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: soc/intel/../../cpu: Helper function to set IA32_PERF_CTL (0x199) MSR
by Subrata Banik (Code Review) 13 Apr '19

13 Apr '19

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32281 Change subject: soc/intel/../../cpu: Helper function to set IA32_PERF_CTL (0x199) MSR ...................................................................... soc/intel/../../cpu: Helper function to set IA32_PERF_CTL (0x199) MSR This patch replaces multiple IA32_PERF_CTL programming with single helper function. TEST=Build and boot WHL and CML platform. Change-Id: I212daa61aa11191dd832630461b517d3dbedd6e1 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/cpu/cpulib.c 1 file changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/32281/1 diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index c847390..9964f2b 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -73,6 +73,13 @@ return (platform_info.hi >> 1) & 3; } +static void set_perf_control_msr(msr_t msr) +{ + wrmsr(IA32_PERF_CTL, msr); + printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", + ((msr.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ); +} + /* * TURBO_RATIO_LIMIT MSR (0x1AD) Bits 31:0 indicates the * factory configured values for of 1-core, 2-core, 3-core @@ -93,9 +100,7 @@ perf_ctl.lo = (msr.lo & 0xff) << 8; perf_ctl.hi = 0; - wrmsr(IA32_PERF_CTL, perf_ctl); - printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", - ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ); + set_perf_control_msr(perf_ctl); } /* @@ -113,9 +118,7 @@ perf_ctl.lo = (msr.lo & 0xff) << 8; perf_ctl.hi = 0; - wrmsr(IA32_PERF_CTL, perf_ctl); - printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", - ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ); + set_perf_control_msr(perf_ctl); } /* @@ -133,9 +136,7 @@ perf_ctl.lo = msr.lo & 0xff00; perf_ctl.hi = 0; - wrmsr(IA32_PERF_CTL, perf_ctl); - printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", - ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ); + set_perf_control_msr(perf_ctl); } /* @@ -152,9 +153,8 @@ min_ratio = cpu_get_min_ratio(); perf_ctl.lo = (min_ratio << 8) & 0xff00; perf_ctl.hi = 0; - wrmsr(IA32_PERF_CTL, perf_ctl); - printk(BIOS_DEBUG, "CPU: frequency set to %u MHz\n", - (min_ratio * CONFIG_CPU_BCLK_MHZ)); + + set_perf_control_msr(perf_ctl); } /* -- To view, visit https://review.coreboot.org/c/coreboot/+/32281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I212daa61aa11191dd832630461b517d3dbedd6e1 Gerrit-Change-Number: 32281 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: mb/google/hatch: Restore Goodix Touch Screen
by EricR Lai (Code Review) 13 Apr '19

13 Apr '19

EricR Lai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32265 Change subject: mb/google/hatch: Restore Goodix Touch Screen ...................................................................... mb/google/hatch: Restore Goodix Touch Screen Restore Goodix devicetree config because of the missing when moving to override. BUG=b:124460799 BRANCH=None TEST=local build and tested with Goodix touch screen Signed-off-by: Eric Lai <ericr_lai(a)compal.corp-partner.google.com> Change-Id: Ic028c5d7b687a069d7f0510897bea91dca58e91f --- M src/mainboard/google/hatch/variants/hatch/overridetree.cb M src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb 2 files changed, 24 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/32265/1 diff --git a/src/mainboard/google/hatch/variants/hatch/overridetree.cb b/src/mainboard/google/hatch/variants/hatch/overridetree.cb index 7d668fe..b4cd241 100644 --- a/src/mainboard/google/hatch/variants/hatch/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch/overridetree.cb @@ -68,18 +68,18 @@ register "stop_off_delay_ms" = "5" device i2c 49 on end end - chip drivers/i2c/hid - register "generic.hid" = ""GDIX0000"" - register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "generic.reset_delay_ms" = "30" - register "generic.reset_off_delay_ms" = "3" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 5d on end + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D15)" + register "generic.enable_delay_ms" = "30" + register "generic.enable_off_delay_ms" = "3" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end end end # I2C #1 device pci 15.2 on diff --git a/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb b/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb index caa80a5..3242eb1 100644 --- a/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb +++ b/src/mainboard/google/hatch/variants/hatch_whl/overridetree.cb @@ -53,18 +53,18 @@ register "stop_off_delay_ms" = "5" device i2c 49 on end end - chip drivers/i2c/hid - register "generic.hid" = ""GDIX0000"" - register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" - register "generic.reset_delay_ms" = "30" - register "generic.reset_off_delay_ms" = "3" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 5d on end + chip drivers/i2c/hid + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" + register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_D16_IRQ)" + register "generic.probed" = "1" + register "generic.enable_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D15)" + register "generic.enable_delay_ms" = "30" + register "generic.enable_off_delay_ms" = "3" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 5d on end end end # I2C #1 device pci 15.2 on -- To view, visit https://review.coreboot.org/c/coreboot/+/32265 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic028c5d7b687a069d7f0510897bea91dca58e91f Gerrit-Change-Number: 32265 Gerrit-PatchSet: 1 Gerrit-Owner: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: security: Add memory subfolder
by Philipp Deppenwiese (Code Review) 12 Apr '19

12 Apr '19

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31548 ) Change subject: security: Add memory subfolder ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifba25bfdd1057049f5cbae8968501bd9be487110 Gerrit-Change-Number: 31548 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 12 Apr 2019 21:58:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in ...coreboot[master]: cpu/x86/pae/pgtbl: Add memset with PAE
by build bot (Jenkins) (Code Review) 12 Apr '19

12 Apr '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31549 ) Change subject: cpu/x86/pae/pgtbl: Add memset with PAE ...................................................................... Patch Set 9: (2 comments) https://review.coreboot.org/#/c/31549/9/src/cpu/x86/pae/pgtbl.c File src/cpu/x86/pae/pgtbl.c: https://review.coreboot.org/#/c/31549/9/src/cpu/x86/pae/pgtbl.c@158 PS9, Line 158: printk(BIOS_ERR, "%s: destination overlaps page tables\n", __func__); line over 80 characters https://review.coreboot.org/#/c/31549/9/src/cpu/x86/pae/pgtbl.c@166 PS9, Line 166: printk(BIOS_ERR, "%s: vmem address overlaps page tables\n", __func__); line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/31549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I00f7ecf87b5c9227a9d58a0b61eecc38007e1a57 Gerrit-Change-Number: 31549 Gerrit-PatchSet: 9 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 12 Apr 2019 21:52:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in ...coreboot[master]: security: Add memory subfolder
by Philipp Deppenwiese (Code Review) 12 Apr '19

12 Apr '19

Philipp Deppenwiese has uploaded a new patch set (#8) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/31548 ) Change subject: security: Add memory subfolder ...................................................................... security: Add memory subfolder Add files to introduce a memory clearing framework. Introduce Kconfig PLATFORM_HAS_DRAM_CLEAR that is to be selected by platforms, that are able to clear all DRAM. Introduce Kconfig SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT that is user selectable to always clear DRAM on non S3 boot. The function security_clear_dram_request tells the calling platform when to wipe all DRAM. Will be extended by TEE frameworks. Add Documentation for the new security API. Change-Id: Ifba25bfdd1057049f5cbae8968501bd9be487110 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M Documentation/index.md M Documentation/security/index.md A Documentation/security/memory_clearing.md M src/security/Kconfig M src/security/Makefile.inc A src/security/memory/Kconfig A src/security/memory/Makefile.inc A src/security/memory/memory.c A src/security/memory/memory.h 9 files changed, 131 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/31548/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/31548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifba25bfdd1057049f5cbae8968501bd9be487110 Gerrit-Change-Number: 31548 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Roy Wen <rgzwen(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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coreboot-gerrit April 2019