Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26859 )
Change subject: cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCK
......................................................................
Patch Set 48:
(1 comment)
https://review.coreboot.org/#/c/26859/48/src/cpu/intel/car/non-evict/cache_…
File src/cpu/intel/car/non-evict/cache_as_ram.S:
https://review.coreboot.org/#/c/26859/48/src/cpu/intel/car/non-evict/cache_…
PS48, Line 36: #if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
> #if CONFIG() […]
haswell, broadwell and all users of soc/intel/common/block/cpu/car/cache_as_ram.S are doing this. All other targets are not doing this. Probably best to test if this does not mess up things on those other targets, enabling it here?
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Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26859 )
Change subject: cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCK
......................................................................
Patch Set 48:
(1 comment)
https://review.coreboot.org/#/c/26859/48/src/cpu/intel/car/non-evict/cache_…
File src/cpu/intel/car/non-evict/cache_as_ram.S:
https://review.coreboot.org/#/c/26859/48/src/cpu/intel/car/non-evict/cache_…
PS48, Line 36: #if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
> The cache as ram code set's up those MTRR's after which they can't be used as an indication that the […]
#if CONFIG()
Also, this affects other than haswell so maybe should be split out.
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26859 )
Change subject: cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCK
......................................................................
Patch Set 48:
(1 comment)
https://review.coreboot.org/#/c/26859/48/src/cpu/intel/car/non-evict/cache_…
File src/cpu/intel/car/non-evict/cache_as_ram.S:
https://review.coreboot.org/#/c/26859/48/src/cpu/intel/car/non-evict/cache_…
PS48, Line 36: #if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
> why is it implemented in assembly? It could be part of soc early init.
The cache as ram code set's up those MTRR's after which they can't be used as an indication that the CPU has not been reset properly. Previously this was done in romcc code.
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30315 )
Change subject: sb/intel/lynxpoint: Enable LPC/SIO setup in bootblock
......................................................................
Patch Set 40: Code-Review+1
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26926 )
Change subject: nb/intel/haswell: Add an option for where verstage starts
......................................................................
Patch Set 43: Code-Review+1
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/26859 )
Change subject: cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCK
......................................................................
Patch Set 48: Code-Review+1
(1 comment)
https://review.coreboot.org/#/c/26859/48/src/cpu/intel/car/non-evict/cache_…
File src/cpu/intel/car/non-evict/cache_as_ram.S:
https://review.coreboot.org/#/c/26859/48/src/cpu/intel/car/non-evict/cache_…
PS48, Line 36: #if IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK)
why is it implemented in assembly? It could be part of soc early init.
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Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30383
to look at the new patch set (#29).
Change subject: soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK
......................................................................
soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK
This puts the cache as ram in the bootblock.
Before setting up cache as ram the microcode updates are applied.
This removes the possibility for a normal/fallback setup although
implementing this should be quite easy.
Setting up LPC in the bootblock to output console on SuperIOs is not
done in this patch, therefore BOOTBLOCK_CONSOLE is not yet selected.
Change-Id: I44eb6d380dea5b82e3f009a46381a0f611bb7935
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/soc/intel/broadwell/Kconfig
M src/soc/intel/broadwell/Makefile.inc
M src/soc/intel/broadwell/bootblock/cpu.c
M src/soc/intel/broadwell/bootblock/pch.c
M src/soc/intel/broadwell/bootblock/systemagent.c
M src/soc/intel/broadwell/romstage/Makefile.inc
M src/soc/intel/broadwell/romstage/romstage.c
7 files changed, 29 insertions(+), 92 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/30383/29
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Hello Patrick Rudolph, Tristan Corrick, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30315
to look at the new patch set (#40).
Change subject: sb/intel/lynxpoint: Enable LPC/SIO setup in bootblock
......................................................................
sb/intel/lynxpoint: Enable LPC/SIO setup in bootblock
This allows for serial console during the bootblock and enables
console in general for the bootblock.
Change-Id: I5c6e107c267a7acb5bf9cbeb54eb5361af3b6db4
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/asrock/h81m-hds/Makefile.inc
A src/mainboard/asrock/h81m-hds/bootblock.c
M src/mainboard/asrock/h81m-hds/romstage.c
M src/northbridge/intel/haswell/Kconfig
M src/southbridge/intel/lynxpoint/Makefile.inc
M src/southbridge/intel/lynxpoint/bootblock.c
M src/southbridge/intel/lynxpoint/early_pch.c
7 files changed, 56 insertions(+), 37 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/30315/40
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Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30384
to look at the new patch set (#31).
Change subject: nb/intel/broadwell: Add an option for where verstage starts
......................................................................
nb/intel/broadwell: Add an option for where verstage starts
Previously broadwell used a romcc bootblock and starting verstage in
romstage was madatory but with C_ENVIRONMENT_BOOTBLOCK it is also
possible to have a separate verstage.
This selects using a separate verstage by default but still keeps the
option around to use verstage in romstage.
Also make sure mrc.bin is only added to the COREBOOT fmap region as it
requires to be run at a specific offset. This means that coreboot will
have to jump from a RW region to the RO region for that binary and
back to that RW region after that binary is done initializing the
memory.
Change-Id: I900233cadb3c76da329fb98f93917570e633365f
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/google/auron/Makefile.inc
M src/mainboard/google/jecht/Makefile.inc
M src/mainboard/intel/wtm2/Makefile.inc
M src/soc/intel/broadwell/Kconfig
M src/soc/intel/broadwell/Makefile.inc
M src/soc/intel/broadwell/romstage/raminit.c
6 files changed, 35 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/30384/31
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