build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29470 )
Change subject: mainboard/portwell/m107: Do initial mainboard commit
......................................................................
Patch Set 11:
(2 comments)
https://review.coreboot.org/#/c/29470/11/src/mainboard/portwell/m107/irqrou…
File src/mainboard/portwell/m107/irqroute.h:
https://review.coreboot.org/#/c/29470/11/src/mainboard/portwell/m107/irqrou…
PS11, Line 40: #define PCI_DEV_PIRQ_ROUTES \
Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/#/c/29470/11/src/mainboard/portwell/m107/irqrou…
PS11, Line 62: #define PIRQ_PIC_ROUTES \
Macros with complex values should be enclosed in parentheses
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Gerrit-Change-Number: 29470
Gerrit-PatchSet: 11
Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>
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Hello Patrick Rudolph, Piotr Król, Paul Menzel, build bot (Jenkins), Michał Żygowski, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29470
to look at the new patch set (#11).
Change subject: mainboard/portwell/m107: Do initial mainboard commit
......................................................................
mainboard/portwell/m107: Do initial mainboard commit
Initial support for Portwell PQ7-M107 (Q7) module.
Code based on Intel Strago mainboard.
BUG=N/A
TEST=booting SeaBIOS and Linux 4.15 kernel on PQ7-M107
Change-Id: I7d3173fdcf881f894a75cd9798ba173b425d4e62
Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com>
---
M Documentation/mainboard/index.md
A Documentation/mainboard/portwell/pq7-m107.md
A src/mainboard/portwell/Kconfig
A src/mainboard/portwell/Kconfig.name
A src/mainboard/portwell/m107/Kconfig
A src/mainboard/portwell/m107/Kconfig.name
A src/mainboard/portwell/m107/Makefile.inc
A src/mainboard/portwell/m107/acpi/ec.asl
A src/mainboard/portwell/m107/acpi/mainboard.asl
A src/mainboard/portwell/m107/acpi/sleepstates.asl
A src/mainboard/portwell/m107/acpi/superio.asl
A src/mainboard/portwell/m107/acpi_tables.c
A src/mainboard/portwell/m107/board_info.txt
A src/mainboard/portwell/m107/bootblock.c
A src/mainboard/portwell/m107/cmos.layout
A src/mainboard/portwell/m107/com_init.c
A src/mainboard/portwell/m107/devicetree.cb
A src/mainboard/portwell/m107/dsdt.asl
A src/mainboard/portwell/m107/fadt.c
A src/mainboard/portwell/m107/gpio.c
A src/mainboard/portwell/m107/hda_verb.c
A src/mainboard/portwell/m107/irqroute.c
A src/mainboard/portwell/m107/irqroute.h
A src/mainboard/portwell/m107/mainboard.c
A src/mainboard/portwell/m107/onboard.h
A src/mainboard/portwell/m107/romstage.c
A src/mainboard/portwell/m107/smihandler.c
A src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex
A src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex
A src/mainboard/portwell/m107/w25q64.c
30 files changed, 1,940 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/29470/11
--
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Gerrit-Change-Number: 29470
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Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>
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Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29414 )
Change subject: soc/intel/braswell: Remove disabled LPE ACPI code
......................................................................
Patch Set 8:
(1 comment)
https://review.coreboot.org/#/c/29414/8/src/soc/intel/braswell/acpi/southcl…
File src/soc/intel/braswell/acpi/southcluster.asl:
https://review.coreboot.org/#/c/29414/8/src/soc/intel/braswell/acpi/southcl…
PS8, Line 291:
> Can't we simply move this #include to each mainboard? That […]
This issue can be solved different ways.
I did have quick check and agree with moving this include to mainboards.
We create new patch
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Gerrit-Change-Number: 29414
Gerrit-PatchSet: 8
Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>
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Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de>
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Hello Patrick Rudolph, Subrata Banik, Maulik V Vaghela, Rizwan Qureshi, build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/31928
to look at the new patch set (#7).
Change subject: soc/intel/cannonlake: Implement soc side VMX support
......................................................................
soc/intel/cannonlake: Implement soc side VMX support
Implement required soc side API to enable VMX support using CPU_COMMON
BUG=b:124518711
TEST= read msr 0x3a and verify vmx is enabled (value should be 5).
Change-Id: I33dbffa6301afabd688080751ba3b85a43e00156
Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com>
---
M src/soc/intel/cannonlake/Kconfig
M src/soc/intel/cannonlake/Makefile.inc
M src/soc/intel/cannonlake/cpu.c
3 files changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/31928/7
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Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32295
Change subject: mb/siemens/mc_apl1: Enable HDA in devicetree for all mainboard variants
......................................................................
mb/siemens/mc_apl1: Enable HDA in devicetree for all mainboard variants
With commit
'4074ce0cc7 (intel/apollolake: Add HDA to disable_dev function)'
FSP is now requested to switch off HDA PCI device if it is disabled in
devicetree. Doing so results in a warm restart. Normally this event
will be stored in CMOS RAM (if the descriptor is configured to do so)
and therefore no further resets are requested by FSP on the next boots
as long as CMOS RAM is kept alive.
The Siemens mainboards based on Apollo Lake do not have a CMOS battery
and therefore the CMOS is not backed up. This leads to reset requests
from FSP after PCI enumeration on every boot. To avoid this reset enable
HDA in devicetree for these mainboards. Though we do not have any usage
of HDA it should not be an issue that the HDA device is now enabled. The
benefit is though that no reset is requested anymore by FSP.
Change-Id: I637c7c01d73350700c6066fee74fecbb5b93b221
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
5 files changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/32295/1
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
index f3e8a77..539c8d9 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
@@ -68,7 +68,7 @@
device pci 0d.1 off end # - PMC
device pci 0d.2 on end # - SPI
device pci 0d.3 off end # - Shared SRAM
- device pci 0e.0 off end # - Audio
+ device pci 0e.0 on end # - Audio
device pci 11.0 on end # - ISH
device pci 12.0 on end # - SATA
device pci 13.0 on end # - RP 2 - PCIe A 0 - MACPHY
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
index 42c474e..aa1e46a 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
@@ -60,7 +60,7 @@
device pci 0d.1 off end # - PMC
device pci 0d.2 on end # - SPI
device pci 0d.3 off end # - Shared SRAM
- device pci 0e.0 off end # - Audio
+ device pci 0e.0 on end # - Audio
device pci 11.0 on end # - ISH
device pci 12.0 on end # - SATA
device pci 13.0 on end # - RP 2 - PCIe A 0
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
index b6839c1..28d6aeb 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
@@ -56,7 +56,7 @@
device pci 0d.1 off end # - PMC
device pci 0d.2 on end # - SPI
device pci 0d.3 off end # - Shared SRAM
- device pci 0e.0 off end # - Audio
+ device pci 0e.0 on end # - Audio
device pci 11.0 on end # - ISH
device pci 12.0 on end # - SATA
device pci 13.0 on end # - RP 2 - PCIe A 0
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
index e6feb48..865f9f5 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
@@ -57,7 +57,7 @@
device pci 0d.1 off end # - PMC
device pci 0d.2 on end # - SPI
device pci 0d.3 off end # - Shared SRAM
- device pci 0e.0 off end # - Audio
+ device pci 0e.0 on end # - Audio
device pci 11.0 on end # - ISH
device pci 12.0 on end # - SATA
device pci 13.0 on end # - RP 2 - PCIe A 0
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
index 15be7ff..f914906 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
@@ -59,7 +59,7 @@
device pci 0d.1 off end # - PMC
device pci 0d.2 on end # - SPI
device pci 0d.3 off end # - Shared SRAM
- device pci 0e.0 off end # - Audio
+ device pci 0e.0 on end # - Audio
device pci 11.0 on end # - ISH
device pci 12.0 on end # - SATA
device pci 13.0 on end # - RP 2 - PCIe A 0
--
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Gerrit-Change-Id: I637c7c01d73350700c6066fee74fecbb5b93b221
Gerrit-Change-Number: 32295
Gerrit-PatchSet: 1
Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com>
Gerrit-MessageType: newchange
build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29470 )
Change subject: mainboard/portwell/m107: Do initial mainboard commit
......................................................................
Patch Set 10:
(2 comments)
https://review.coreboot.org/#/c/29470/10/src/mainboard/portwell/m107/irqrou…
File src/mainboard/portwell/m107/irqroute.h:
https://review.coreboot.org/#/c/29470/10/src/mainboard/portwell/m107/irqrou…
PS10, Line 40: #define PCI_DEV_PIRQ_ROUTES \
Macros with complex values should be enclosed in parentheses
https://review.coreboot.org/#/c/29470/10/src/mainboard/portwell/m107/irqrou…
PS10, Line 62: #define PIRQ_PIC_ROUTES \
Macros with complex values should be enclosed in parentheses
--
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Gerrit-Comment-Date: Mon, 15 Apr 2019 09:54:03 +0000
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Gerrit-MessageType: comment
Hello Patrick Rudolph, Piotr Król, Paul Menzel, build bot (Jenkins), Michał Żygowski, Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/29470
to look at the new patch set (#10).
Change subject: mainboard/portwell/m107: Do initial mainboard commit
......................................................................
mainboard/portwell/m107: Do initial mainboard commit
Initial support for Portwell PQ7-M107 (Q7) module.
Code based on Intel Strago mainboard.
BUG=N/A
TEST=booting SeaBIOS and Linux 4.9 kernel on PQ7-M107
Change-Id: I7d3173fdcf881f894a75cd9798ba173b425d4e62
Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com>
---
M Documentation/mainboard/index.md
A Documentation/mainboard/portwell/pq7-m107.md
A src/mainboard/portwell/Kconfig
A src/mainboard/portwell/Kconfig.name
A src/mainboard/portwell/m107/Kconfig
A src/mainboard/portwell/m107/Kconfig.name
A src/mainboard/portwell/m107/Makefile.inc
A src/mainboard/portwell/m107/acpi/ec.asl
A src/mainboard/portwell/m107/acpi/mainboard.asl
A src/mainboard/portwell/m107/acpi/sleepstates.asl
A src/mainboard/portwell/m107/acpi/superio.asl
A src/mainboard/portwell/m107/acpi_tables.c
A src/mainboard/portwell/m107/board_info.txt
A src/mainboard/portwell/m107/bootblock.c
A src/mainboard/portwell/m107/cmos.layout
A src/mainboard/portwell/m107/com_init.c
A src/mainboard/portwell/m107/devicetree.cb
A src/mainboard/portwell/m107/dsdt.asl
A src/mainboard/portwell/m107/fadt.c
A src/mainboard/portwell/m107/gpio.c
A src/mainboard/portwell/m107/hda_verb.c
A src/mainboard/portwell/m107/irqroute.c
A src/mainboard/portwell/m107/irqroute.h
A src/mainboard/portwell/m107/mainboard.c
A src/mainboard/portwell/m107/onboard.h
A src/mainboard/portwell/m107/romstage.c
A src/mainboard/portwell/m107/smihandler.c
A src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex
A src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex
A src/mainboard/portwell/m107/w25q64.c
30 files changed, 1,941 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/29470/10
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