coreboot-gerrit April 2019

coreboot-gerrit@coreboot.org

1 participants
1219 discussions

Change in ...coreboot[master]: mainboard/facebook/fbg1701: Do initial mainboard commit
by build bot (Jenkins) (Code Review) 16 Apr '19

16 Apr '19

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30414 ) Change subject: mainboard/facebook/fbg1701: Do initial mainboard commit ...................................................................... Patch Set 18: (3 comments) https://review.coreboot.org/#/c/30414/18/src/mainboard/facebook/fbg1701/irq… File src/mainboard/facebook/fbg1701/irqroute.h: https://review.coreboot.org/#/c/30414/18/src/mainboard/facebook/fbg1701/irq… PS18, Line 40: #define PCI_DEV_PIRQ_ROUTES \ Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/30414/18/src/mainboard/facebook/fbg1701/irq… PS18, Line 62: #define PIRQ_PIC_ROUTES \ Macros with complex values should be enclosed in parentheses https://review.coreboot.org/#/c/30414/18/src/mainboard/facebook/fbg1701/rom… File src/mainboard/facebook/fbg1701/romstage.c: https://review.coreboot.org/#/c/30414/18/src/mainboard/facebook/fbg1701/rom… PS18, Line 100: status = mboot_hash_extend_log(activePcr, 0, (uint8_t *)crtm_version, line over 80 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/30414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28ac78a630ee705b1e546031f024bfe7f952ab39 Gerrit-Change-Number: 30414 Gerrit-PatchSet: 18 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Comment-Date: Tue, 16 Apr 2019 14:56:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: mainboard/facebook/fbg1701: Do initial mainboard commit
by Patrick Rudolph (Code Review) 16 Apr '19

16 Apr '19

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30414 ) Change subject: mainboard/facebook/fbg1701: Do initial mainboard commit ...................................................................... Patch Set 18: (1 comment) https://review.coreboot.org/#/c/30414/18/src/mainboard/facebook/fbg1701/mai… File src/mainboard/facebook/fbg1701/mainboard.h: https://review.coreboot.org/#/c/30414/18/src/mainboard/facebook/fbg1701/mai… PS18, Line 25: : static const edp_data_t mainboard_TC348860InitTable[] = { looks unused -- To view, visit https://review.coreboot.org/c/coreboot/+/30414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28ac78a630ee705b1e546031f024bfe7f952ab39 Gerrit-Change-Number: 30414 Gerrit-PatchSet: 18 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Comment-Date: Tue, 16 Apr 2019 14:45:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: soc/intel/cannonlake: Vmx support based on Kconfig
by Ronak Kanabar (Code Review) 16 Apr '19

16 Apr '19

Ronak Kanabar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32117 Change subject: soc/intel/cannonlake: Vmx support based on Kconfig ...................................................................... soc/intel/cannonlake: Vmx support based on Kconfig Change VmxEnable UPD values based on Kconfig ENABLE_VMX and remove it from Devicetree. Change-Id: I4180c2270038a28befd6ed53c9485905025a15ba Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/mainboard/google/sarien/variants/arcada/devicetree.cb M src/mainboard/google/sarien/variants/sarien/devicetree.cb M src/soc/intel/cannonlake/romstage/fsp_params.c 3 files changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/32117/1 diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 6f167c2..90b92a7 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -22,7 +22,6 @@ register "SataPortsDevSlp[2]" = "1" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" - register "VmxEnable" = "1" register "PchPmSlpS3MinAssert" = "3" # 50ms register "PchPmSlpS4MinAssert" = "4" # 4s register "PchPmSlpSusMinAssert" = "4" # 4s diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 2714b60..5b88dfc 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -26,7 +26,6 @@ register "SataPortsDevSlp[2]" = "1" register "InternalGfx" = "1" register "SkipExtGfxScan" = "1" - register "VmxEnable" = "1" register "PchPmSlpS3MinAssert" = "3" # 50ms register "PchPmSlpS4MinAssert" = "4" # 4s register "PchPmSlpSusMinAssert" = "4" # 4s diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index ffdcee4..235cda8 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -65,7 +65,7 @@ if (config->VtdDisable) m_cfg->VmxEnable = 0; else - m_cfg->VmxEnable = config->VmxEnable; + m_cfg->VmxEnable = CONFIG(ENABLE_VMX); #if CONFIG(SOC_INTEL_COMMON_CANNONLAKE_BASE) m_cfg->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT; -- To view, visit https://review.coreboot.org/c/coreboot/+/32117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4180c2270038a28befd6ed53c9485905025a15ba Gerrit-Change-Number: 32117 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newchange

8 12

Change in ...coreboot[master]: soc/intel/cannonlake: Implement soc side VMX support
by Nico Huber (Code Review) 16 Apr '19

16 Apr '19

Nico Huber has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31928 ) Change subject: soc/intel/cannonlake: Implement soc side VMX support ...................................................................... soc/intel/cannonlake: Implement soc side VMX support Implement required soc side API to enable VMX support using CPU_COMMON BUG=b:124518711 TEST= read msr 0x3a and verify vmx is enabled (value should be 5). Change-Id: I33dbffa6301afabd688080751ba3b85a43e00156 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31928 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/cpu.c 3 files changed, 6 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved Furquan Shaikh: Looks good to me, approved Maulik V Vaghela: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 14404f7..026aaf2 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -67,6 +67,7 @@ select CACHE_MRC_SETTINGS select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM select COMMON_FADT + select CPU_INTEL_COMMON select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_M_XIP select GENERIC_GPIO_LIB diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index 87898f2..7ad0c7c 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -7,6 +7,7 @@ subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc +subdirs-y += ../../../cpu/intel/common bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/cpu.c diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 01386dd..34b7891 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -33,6 +33,7 @@ #include <soc/systemagent.h> #include <cpu/x86/mtrr.h> #include <cpu/intel/microcode.h> +#include <cpu/intel/common/common.h> /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ static const u8 power_limit_time_sec_to_msr[] = { @@ -437,6 +438,9 @@ /* Enable Turbo */ enable_turbo(); + + /* Enable Vmx */ + set_vmx_and_lock(); } static void per_cpu_smm_trigger(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/31928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33dbffa6301afabd688080751ba3b85a43e00156 Gerrit-Change-Number: 31928 Gerrit-PatchSet: 8 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: RONAK KANABAR <ronak199323(a)gmail.com> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-MessageType: merged

1 0

Change in ...coreboot[master]: soc/intel/cannonlake: Implement soc side VMX support
by Nico Huber (Code Review) 16 Apr '19

16 Apr '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31928 ) Change subject: soc/intel/cannonlake: Implement soc side VMX support ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/31928 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33dbffa6301afabd688080751ba3b85a43e00156 Gerrit-Change-Number: 31928 Gerrit-PatchSet: 7 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: RONAK KANABAR <ronak199323(a)gmail.com> Gerrit-CC: Thomas Heijligen <src(a)posteo.de> Gerrit-Comment-Date: Tue, 16 Apr 2019 14:36:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: drivers/intel/fsp1_1/raminit.c: Make check FSP HOBs independent of CO...
by Frans Hendriks (Code Review) 16 Apr '19

16 Apr '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29371 ) Change subject: drivers/intel/fsp1_1/raminit.c: Make check FSP HOBs independent of CONFIG_DISPLAY_HOBS ...................................................................... Patch Set 3: > Patch Set 3: > > (3 comments) > > Please clean up and separate HOB checking and HOB displaying. You have also enabled prints that are a part of displaying the hobs after removing the macro. I don't agree 100% with your comment. The Hobs are handled the same way as FSP_BOOTLOADER_TOLUM_HOB and FSP_SMBIOS_MEMORY_INFO_HOB now. We might consider if CONFIG_DISPLAY_HOBS should disable and hob information, but don't disable verification of the required hobs. -- To view, visit https://review.coreboot.org/c/coreboot/+/29371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3776fa37866c7ef3aea090842387660c22bbdd4d Gerrit-Change-Number: 29371 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: York Yang <yyang024(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 16 Apr 2019 14:03:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: mainboard/facebook/fbg1701: Do initial mainboard commit
by Frans Hendriks (Code Review) 16 Apr '19

16 Apr '19

Hello Patrick Rudolph, build bot (Jenkins), Michał Żygowski, Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/30414 to look at the new patch set (#18). Change subject: mainboard/facebook/fbg1701: Do initial mainboard commit ...................................................................... mainboard/facebook/fbg1701: Do initial mainboard commit Initial support for Facebook FBG-1701 system. coreboot implementation is prepared for VENDORCODE_ELTAN measured boot and verified boot support. These features are default disabled. Code based on Intel Strago mainboard. BUG=N/A TEST=booting Linux 4.120 kernel on Facebook FBG-1701 Change-Id: I28ac78a630ee705b1e546031f024bfe7f952ab39 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- A Documentation/mainboard/facebook/fbg1701.md M Documentation/mainboard/index.md A src/mainboard/facebook/fbg1701/Kconfig A src/mainboard/facebook/fbg1701/Kconfig.name A src/mainboard/facebook/fbg1701/Makefile.inc A src/mainboard/facebook/fbg1701/acpi/dptf.asl A src/mainboard/facebook/fbg1701/acpi/ec.asl A src/mainboard/facebook/fbg1701/acpi/mainboard.asl A src/mainboard/facebook/fbg1701/acpi/sleepstates.asl A src/mainboard/facebook/fbg1701/acpi/superio.asl A src/mainboard/facebook/fbg1701/acpi_tables.c A src/mainboard/facebook/fbg1701/board_info.txt A src/mainboard/facebook/fbg1701/board_mboot.c A src/mainboard/facebook/fbg1701/board_verified_boot.c A src/mainboard/facebook/fbg1701/board_verified_boot.h A src/mainboard/facebook/fbg1701/bootblock.c A src/mainboard/facebook/fbg1701/cmos.layout A src/mainboard/facebook/fbg1701/com_init.c A src/mainboard/facebook/fbg1701/devicetree.cb A src/mainboard/facebook/fbg1701/dsdt.asl A src/mainboard/facebook/fbg1701/fadt.c A src/mainboard/facebook/fbg1701/fmap.fmd A src/mainboard/facebook/fbg1701/gpio.c A src/mainboard/facebook/fbg1701/hda_verb.c A src/mainboard/facebook/fbg1701/irqroute.c A src/mainboard/facebook/fbg1701/irqroute.h A src/mainboard/facebook/fbg1701/logo.c A src/mainboard/facebook/fbg1701/mainboard.c A src/mainboard/facebook/fbg1701/mainboard.h A src/mainboard/facebook/fbg1701/manifest.h A src/mainboard/facebook/fbg1701/onboard.h A src/mainboard/facebook/fbg1701/ramstage.c A src/mainboard/facebook/fbg1701/romstage.c A src/mainboard/facebook/fbg1701/smihandler.c A src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex A src/mainboard/facebook/fbg1701/w25q64.c 36 files changed, 2,362 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/30414/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/30414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28ac78a630ee705b1e546031f024bfe7f952ab39 Gerrit-Change-Number: 30414 Gerrit-PatchSet: 18 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: mainboard/facebook/fbg1701: Do initial mainboard commit
by Frans Hendriks (Code Review) 16 Apr '19

16 Apr '19

Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30414 ) Change subject: mainboard/facebook/fbg1701: Do initial mainboard commit ...................................................................... Patch Set 17: (10 comments) Have implemented the comment. Will update with new patch https://review.coreboot.org/#/c/30414/17/src/mainboard/facebook/fbg1701/Mak… File src/mainboard/facebook/fbg1701/Makefile.inc: https://review.coreboot.org/#/c/30414/17/src/mainboard/facebook/fbg1701/Mak… PS17, Line 27: ramstage-y += logo.c > Why not use such notation: […] Done https://review.coreboot.org/#/c/30414/17/src/mainboard/facebook/fbg1701/acp… File src/mainboard/facebook/fbg1701/acpi/superio.asl: https://review.coreboot.org/#/c/30414/17/src/mainboard/facebook/fbg1701/acp… PS17, Line 21: Device (COM1) { > Any reason for the indentation? UART of onboard IT8528 https://review.coreboot.org/#/c/30414/17/src/mainboard/facebook/fbg1701/boa… File src/mainboard/facebook/fbg1701/board_info.txt: https://review.coreboot.org/#/c/30414/17/src/mainboard/facebook/fbg1701/boa… PS17, Line 3: Category: misc > Does the board really not fit into any category? Change to sbc https://review.coreboot.org/#/c/30414/17/src/mainboard/facebook/fbg1701/com… File src/mainboard/facebook/fbg1701/com_init.c: https://review.coreboot.org/#/c/30414/17/src/mainboard/facebook/fbg1701/com… PS17, Line 24: #if !IS_ENABLED(CONFIG_C_ENVIRONMENT_BOOTBLOCK) > Please use CONFIG() macro This IS_ENABLED can be remove, since C_ENVIRONMENT_BOOTBLOCK is defaault https://review.coreboot.org/#/c/30414/17/src/mainboard/facebook/fbg1701/dev… File src/mainboard/facebook/fbg1701/devicetree.cb: https://review.coreboot.org/#/c/30414/17/src/mainboard/facebook/fbg1701/dev… PS17, Line 75: register "DptfDisable" = "1" > Why DPTF is disabled here but enabled in domain 0? DPTF should be disabled https://review.coreboot.org/#/c/30414/17/src/mainboard/facebook/fbg1701/fma… File src/mainboard/facebook/fbg1701/fmap.fmd: https://review.coreboot.org/#/c/30414/17/src/mainboard/facebook/fbg1701/fma… PS17, Line 1: # layout for firmware residing at top of 4GB address space > If the mainboard is intended to use VBOOT I also recommend to provide second fmd file for that case. This file is used for VENDORCODE_ELTAN_VBOOT. It can be used with VENDORCODE_ELTAN_VBOOT disabled. https://review.coreboot.org/#/c/30414/17/src/mainboard/facebook/fbg1701/gpi… File src/mainboard/facebook/fbg1701/gpio.c: https://review.coreboot.org/#/c/30414/17/src/mainboard/facebook/fbg1701/gpi… PS17, Line 116: NATIVE_PU1K_CSEN_INVTX(1), /* 61 I2C0_SDA */ > All I2C devices are disabled, why configuring the pins for I2C? Configure the pins in not used state. Need to configure any state. https://review.coreboot.org/#/c/30414/17/src/mainboard/facebook/fbg1701/ram… File src/mainboard/facebook/fbg1701/ramstage.c: https://review.coreboot.org/#/c/30414/17/src/mainboard/facebook/fbg1701/ram… PS17, Line 21: #if IS_ENABLED(CONFIG_FSP1_1_DISPLAY_LOGO) > Why is this split into two blocks with macro? Mistake. The IS_ENABLED will be covered by 1 macro. https://review.coreboot.org/#/c/30414/17/src/mainboard/facebook/fbg1701/rom… File src/mainboard/facebook/fbg1701/romstage.c: https://review.coreboot.org/#/c/30414/17/src/mainboard/facebook/fbg1701/rom… PS17, Line 41: ps->spd_data_ch0 = cbfs_boot_map_with_leak(buf, CBFS_TYPE_SPD, NULL); > Change filename to spd. […] Done https://review.coreboot.org/#/c/30414/17/src/mainboard/facebook/fbg1701/smi… File src/mainboard/facebook/fbg1701/smihandler.c: https://review.coreboot.org/#/c/30414/17/src/mainboard/facebook/fbg1701/smi… PS17, Line 60: case ACPI_S3: > Board does not seem to support S3, why is this case implemented? Copy/paste result from Intel Strago. Removed unused code in next patch set. -- To view, visit https://review.coreboot.org/c/coreboot/+/30414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I28ac78a630ee705b1e546031f024bfe7f952ab39 Gerrit-Change-Number: 30414 Gerrit-PatchSet: 17 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Comment-Date: Tue, 16 Apr 2019 12:38:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: sb/intel/bd82x6x/early_pch: Make use of RCBA and DMIBAR marcros
by Patrick Rudolph (Code Review) 16 Apr '19

16 Apr '19

Hello Patrick Rudolph, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/32072 to look at the new patch set (#7). Change subject: sb/intel/bd82x6x/early_pch: Make use of RCBA and DMIBAR marcros ...................................................................... sb/intel/bd82x6x/early_pch: Make use of RCBA and DMIBAR marcros Use RCBA and DMIBAR macros to get rid of DEFAULT_RCBA and DEFAULT_DMIBAR. Tested on Lenovo T520 (Intel Sandy Bridge). Still boots to OS, no errors visible in dmesg. Change-Id: Ic9be2240ea10b17c8cc289007dccadbb9e3f69ab Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/southbridge/intel/bd82x6x/early_pch.c 1 file changed, 164 insertions(+), 162 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/32072/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/32072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic9be2240ea10b17c8cc289007dccadbb9e3f69ab Gerrit-Change-Number: 32072 Gerrit-PatchSet: 7 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

1 0

Change in ...coreboot[master]: sb/intel/bd82x6x: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB
by Patrick Rudolph (Code Review) 16 Apr '19

16 Apr '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32037 Change subject: sb/intel/bd82x6x: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB ...................................................................... sb/intel/bd82x6x: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB Use common code to detect ACPI S3. Untested. Change-Id: I283a841575430f2f179997db8d2f08fa3978a0bb Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/romstage.c M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/bd82x6x/Makefile.inc D src/southbridge/intel/bd82x6x/early_pch_common.c M src/southbridge/intel/bd82x6x/pch.h 5 files changed, 3 insertions(+), 55 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/32037/1 diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 6112c76..8ddc156 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -28,6 +28,7 @@ #include <device/device.h> #include <northbridge/intel/sandybridge/chip.h> #include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/common/pmclib.h> static void early_pch_reset_pmcon(void) { diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 1396a63..dae3c32 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -29,6 +29,7 @@ select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI + select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select IOAPIC select HAVE_USBDEBUG_OPTIONS select HAVE_SMI_HANDLER diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index 24d7e2d..7ce3da7 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -38,7 +38,7 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c pch.c romstage-y += early_smbus.c me_status.c -romstage-y += early_spi.c early_pch_common.c +romstage-y += early_spi.c romstage-y += early_rcba.c ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y) @@ -47,6 +47,4 @@ romstage-y += early_me_mrc.c early_usb_mrc.c endif -ramstage-y += early_pch_common.c - endif diff --git a/src/southbridge/intel/bd82x6x/early_pch_common.c b/src/southbridge/intel/bd82x6x/early_pch_common.c deleted file mode 100644 index 2e9ad7f..0000000 --- a/src/southbridge/intel/bd82x6x/early_pch_common.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> -#include "pch.h" -#include <arch/acpi.h> -#include <console/console.h> - -#if ENV_ROMSTAGE -int southbridge_detect_s3_resume(void) -{ - u32 pm1_cnt; - u16 pm1_sts; - - /* Check PM1_STS[15] to see if we are waking from Sx */ - pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); - - /* Read PM1_CNT[12:10] to determine which Sx state */ - pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); - - if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { - if (acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); - return 1; - } else { - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); - } - } - - return 0; -} -#endif diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 0097e15..21b6031 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -76,7 +76,6 @@ void southbridge_rcba_config(void); void mainboard_rcba_config(void); void early_pch_init_native(void); -int southbridge_detect_s3_resume(void); void early_pch_init(void); struct southbridge_usb_port -- To view, visit https://review.coreboot.org/c/coreboot/+/32037 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I283a841575430f2f179997db8d2f08fa3978a0bb Gerrit-Change-Number: 32037 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

2 6

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2019