Hello Aaron Durbin, Patrick Rudolph, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/26926
to look at the new patch set (#43).
Change subject: nb/intel/haswell: Add an option for where verstage starts
......................................................................
nb/intel/haswell: Add an option for where verstage starts
Previously Haswell used a romcc bootblock and starting verstage in
romstage was madatory but with C_ENVIRONMENT_BOOTBLOCK it is also
possible to have a separate verstage.
This selects using a separate verstage by default but still keeps the
option around to use verstage in romstage.
Also make sure mrc.bin is only added to the COREBOOT fmap region as it
requires to be run at a specific offset. This means that coreboot will
have to jump from a RW region to the RO region for that binary and
back to that RW region after that binary is done initializing the
memory.
Change-Id: I3b7b29f4a24c0fb830ff76fe31a35b6afcae4e67
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/intel/haswell/Makefile.inc
M src/mainboard/google/beltino/Makefile.inc
M src/mainboard/intel/baskingridge/Makefile.inc
M src/northbridge/intel/haswell/Kconfig
M src/southbridge/intel/common/Makefile.inc
M src/southbridge/intel/lynxpoint/Makefile.inc
M src/southbridge/intel/lynxpoint/pmutil.c
7 files changed, 36 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/26926/43
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I3b7b29f4a24c0fb830ff76fe31a35b6afcae4e67
Gerrit-Change-Number: 26926
Gerrit-PatchSet: 43
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Nico Huber <nico.h(a)gmx.de>
Gerrit-MessageType: newpatchset
Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30383
to look at the new patch set (#27).
Change subject: soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK
......................................................................
soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK
This puts the cache as ram in the bootblock.
Before setting up cache as ram the microcode updates are applied.
This removes the possibility for a normal/fallback setup although
implementing this should be quite easy.
Setting up LPC in the bootblock to output console on SuperIOs is not
done in this patch, therefore BOOTBLOCK_CONSOLE is not yet selected.
Change-Id: I44eb6d380dea5b82e3f009a46381a0f611bb7935
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/soc/intel/broadwell/Kconfig
M src/soc/intel/broadwell/Makefile.inc
M src/soc/intel/broadwell/bootblock/cpu.c
M src/soc/intel/broadwell/bootblock/pch.c
M src/soc/intel/broadwell/bootblock/systemagent.c
M src/soc/intel/broadwell/romstage/Makefile.inc
M src/soc/intel/broadwell/romstage/romstage.c
7 files changed, 28 insertions(+), 92 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/30383/27
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I44eb6d380dea5b82e3f009a46381a0f611bb7935
Gerrit-Change-Number: 30383
Gerrit-PatchSet: 27
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-MessageType: newpatchset
Hello Patrick Rudolph, Tristan Corrick, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30315
to look at the new patch set (#38).
Change subject: sb/intel/lynxpoint: Enable LPC/SIO setup in bootblock
......................................................................
sb/intel/lynxpoint: Enable LPC/SIO setup in bootblock
This allows for serial console during the bootblock and enables
console in general for the bootblock.
Change-Id: I5c6e107c267a7acb5bf9cbeb54eb5361af3b6db4
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/asrock/h81m-hds/Makefile.inc
A src/mainboard/asrock/h81m-hds/bootblock.c
M src/mainboard/asrock/h81m-hds/romstage.c
M src/northbridge/intel/haswell/Kconfig
M src/southbridge/intel/lynxpoint/Makefile.inc
M src/southbridge/intel/lynxpoint/bootblock.c
M src/southbridge/intel/lynxpoint/early_pch.c
7 files changed, 55 insertions(+), 37 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/30315/38
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Gerrit-Change-Id: I5c6e107c267a7acb5bf9cbeb54eb5361af3b6db4
Gerrit-Change-Number: 30315
Gerrit-PatchSet: 38
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-MessageType: newpatchset
Hello Patrick Rudolph, Julius Werner, Matt DeVillier, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/26859
to look at the new patch set (#48).
Change subject: cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCK
......................................................................
cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCK
This puts the cache as ram in the bootblock.
Before setting up cache as ram the microcode updates are applied.
This removes the possibility for a normal/fallback setup although
implementing this should be quite easy.
This adds a linker symbol _car_bist_result to easily share to bist
result between stages.
Tested on Google peppy (Acer C720).
Setting up LPC in the bootblock to output console on SuperIOs is not
done in this patch, hence BOOTBLOCK_CONSOLE is not yet enabled by
default.
Change-Id: Ia96499a9d478127f6b9d880883ac41397b58dbea
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/intel/car/non-evict/cache_as_ram.S
M src/cpu/intel/haswell/Kconfig
M src/cpu/intel/haswell/Makefile.inc
M src/cpu/intel/haswell/bootblock.c
M src/northbridge/intel/haswell/Kconfig
M src/northbridge/intel/haswell/Makefile.inc
M src/northbridge/intel/haswell/bootblock.c
M src/southbridge/intel/lynxpoint/Kconfig
M src/southbridge/intel/lynxpoint/Makefile.inc
M src/southbridge/intel/lynxpoint/bootblock.c
M src/southbridge/intel/lynxpoint/early_pch.c
11 files changed, 48 insertions(+), 77 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/26859/48
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Gerrit-Branch: master
Gerrit-Change-Id: Ia96499a9d478127f6b9d880883ac41397b58dbea
Gerrit-Change-Number: 26859
Gerrit-PatchSet: 48
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr>
Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi>
Gerrit-MessageType: newpatchset
Hello Patrick Rudolph, Felix Held, Matt DeVillier, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30385
to look at the new patch set (#30).
Change subject: soc/intel/broadwell: Enable LPC/SIO setup in bootblock
......................................................................
soc/intel/broadwell: Enable LPC/SIO setup in bootblock
This allows for serial console during the bootblock and enables
bootblock console by default.
Change-Id: I7746e4f819486d6142c96bc4c7480076fbfdfbde
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/google/jecht/Makefile.inc
A src/mainboard/google/jecht/bootblock.c
M src/mainboard/google/jecht/romstage.c
M src/soc/intel/broadwell/Kconfig
M src/soc/intel/broadwell/bootblock/pch.c
A src/soc/intel/broadwell/include/soc/bootblock.h
M src/soc/intel/broadwell/romstage/pch.c
M src/soc/intel/broadwell/romstage/romstage.c
8 files changed, 109 insertions(+), 63 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/30385/30
--
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Gerrit-Branch: master
Gerrit-Change-Id: I7746e4f819486d6142c96bc4c7480076fbfdfbde
Gerrit-Change-Number: 30385
Gerrit-PatchSet: 30
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-MessageType: newpatchset
Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30383
to look at the new patch set (#26).
Change subject: soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK
......................................................................
soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK
This puts the cache as ram in the bootblock.
Before setting up cache as ram the microcode updates are applied.
This removes the possibility for a normal/fallback setup although
implementing this should be quite easy.
Setting up LPC in the bootblock to output console on SuperIOs is not
done in this patch, therefore BOOTBLOCK_CONSOLE is not yet selected.
Change-Id: I44eb6d380dea5b82e3f009a46381a0f611bb7935
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/soc/intel/broadwell/Kconfig
M src/soc/intel/broadwell/Makefile.inc
M src/soc/intel/broadwell/bootblock/cpu.c
M src/soc/intel/broadwell/bootblock/pch.c
M src/soc/intel/broadwell/bootblock/systemagent.c
M src/soc/intel/broadwell/romstage/Makefile.inc
M src/soc/intel/broadwell/romstage/romstage.c
7 files changed, 28 insertions(+), 92 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/30383/26
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I44eb6d380dea5b82e3f009a46381a0f611bb7935
Gerrit-Change-Number: 30383
Gerrit-PatchSet: 26
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-MessageType: newpatchset
Hello Patrick Rudolph, Tristan Corrick, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30315
to look at the new patch set (#37).
Change subject: sb/intel/lynxpoint: Enable LPC/SIO setup in bootblock
......................................................................
sb/intel/lynxpoint: Enable LPC/SIO setup in bootblock
This allows for serial console during the bootblock and enables
console in general for the bootblock.
Change-Id: I5c6e107c267a7acb5bf9cbeb54eb5361af3b6db4
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/asrock/h81m-hds/Makefile.inc
A src/mainboard/asrock/h81m-hds/bootblock.c
M src/mainboard/asrock/h81m-hds/romstage.c
M src/northbridge/intel/haswell/Kconfig
M src/southbridge/intel/lynxpoint/Makefile.inc
M src/southbridge/intel/lynxpoint/bootblock.c
M src/southbridge/intel/lynxpoint/early_pch.c
7 files changed, 55 insertions(+), 37 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/30315/37
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Gerrit-Change-Id: I5c6e107c267a7acb5bf9cbeb54eb5361af3b6db4
Gerrit-Change-Number: 30315
Gerrit-PatchSet: 37
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-MessageType: newpatchset
Hello Patrick Rudolph, Julius Werner, Matt DeVillier, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/26859
to look at the new patch set (#47).
Change subject: cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCK
......................................................................
cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCK
This puts the cache as ram in the bootblock.
Before setting up cache as ram the microcode updates are applied.
This removes the possibility for a normal/fallback setup although
implementing this should be quite easy.
This adds a linker symbol _car_bist_result to easily share to bist
result between stages.
Tested on Google peppy (Acer C720).
Setting up LPC in the bootblock to output console on SuperIOs is not
done in this patch, hence BOOTBLOCK_CONSOLE is not yet enabled by
default.
Change-Id: Ia96499a9d478127f6b9d880883ac41397b58dbea
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/cpu/intel/car/non-evict/cache_as_ram.S
M src/cpu/intel/haswell/Kconfig
M src/cpu/intel/haswell/Makefile.inc
M src/cpu/intel/haswell/bootblock.c
M src/northbridge/intel/haswell/Kconfig
M src/northbridge/intel/haswell/Makefile.inc
M src/northbridge/intel/haswell/bootblock.c
M src/southbridge/intel/lynxpoint/Kconfig
M src/southbridge/intel/lynxpoint/Makefile.inc
M src/southbridge/intel/lynxpoint/bootblock.c
M src/southbridge/intel/lynxpoint/early_pch.c
11 files changed, 48 insertions(+), 77 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/26859/47
--
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Gerrit-Change-Id: Ia96499a9d478127f6b9d880883ac41397b58dbea
Gerrit-Change-Number: 26859
Gerrit-PatchSet: 47
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr>
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Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi>
Gerrit-MessageType: newpatchset
Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30384
to look at the new patch set (#27).
Change subject: nb/intel/broadwell: Add an option for where verstage starts
......................................................................
nb/intel/broadwell: Add an option for where verstage starts
Previously broadwell used a romcc bootblock and starting verstage in
romstage was madatory but with C_ENVIRONMENT_BOOTBLOCK it is also
possible to have a separate verstage.
This selects using a separate verstage by default but still keeps the
option around to use verstage in romstage.
Also make sure mrc.bin is only added to the COREBOOT fmap region as it
requires to be run at a specific offset. This means that coreboot will
have to jump from a RW region to the RO region for that binary and
back to that RW region after that binary is done initializing the
memory.
Change-Id: I900233cadb3c76da329fb98f93917570e633365f
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/mainboard/google/auron/Makefile.inc
M src/mainboard/google/jecht/Makefile.inc
M src/mainboard/intel/wtm2/Makefile.inc
M src/soc/intel/broadwell/Kconfig
M src/soc/intel/broadwell/Makefile.inc
M src/soc/intel/broadwell/romstage/raminit.c
6 files changed, 34 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/30384/27
--
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I900233cadb3c76da329fb98f93917570e633365f
Gerrit-Change-Number: 30384
Gerrit-PatchSet: 27
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: newpatchset
Hello Patrick Rudolph, build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/30383
to look at the new patch set (#24).
Change subject: soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK
......................................................................
soc/intel/broadwell: Use C_ENVIRONMENT_BOOTBLOCK
This puts the cache as ram in the bootblock.
Before setting up cache as ram the microcode updates are applied.
This removes the possibility for a normal/fallback setup although
implementing this should be quite easy.
Setting up LPC in the bootblock to output console on SuperIOs is not
done in this patch.
Change-Id: I44eb6d380dea5b82e3f009a46381a0f611bb7935
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/soc/intel/broadwell/Kconfig
M src/soc/intel/broadwell/Makefile.inc
M src/soc/intel/broadwell/bootblock/cpu.c
M src/soc/intel/broadwell/bootblock/pch.c
M src/soc/intel/broadwell/bootblock/systemagent.c
M src/soc/intel/broadwell/romstage/Makefile.inc
M src/soc/intel/broadwell/romstage/romstage.c
7 files changed, 29 insertions(+), 92 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/30383/24
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Gerrit-Change-Id: I44eb6d380dea5b82e3f009a46381a0f611bb7935
Gerrit-Change-Number: 30383
Gerrit-PatchSet: 24
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
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Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org>
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