coreboot-gerrit April 2019

coreboot-gerrit@coreboot.org

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Change in ...coreboot[master]: nb/intel/haswell: Add an option for where verstage starts
by Arthur Heymans (Code Review) 14 Apr '19

14 Apr '19

Hello Aaron Durbin, Patrick Rudolph, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/26926 to look at the new patch set (#40). Change subject: nb/intel/haswell: Add an option for where verstage starts ...................................................................... nb/intel/haswell: Add an option for where verstage starts Previously Haswell used a romcc bootblock and starting verstage in romstage was madatory but with C_ENVIRONMENT_BOOTBLOCK it is also possible to have a separate verstage. This selects using a separate verstage by default but still keeps the option around to use verstage in romstage. Also make sure mrc.bin is only added to the COREBOOT fmap region as it requires to be run at a specific offset. This means that coreboot will have to jump from a RW region to the RO region for that binary and back to that RW region after that binary is done initializing the memory. Change-Id: I3b7b29f4a24c0fb830ff76fe31a35b6afcae4e67 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/beltino/Makefile.inc M src/mainboard/intel/baskingridge/Makefile.inc M src/northbridge/intel/haswell/Kconfig M src/southbridge/intel/common/Makefile.inc M src/southbridge/intel/lynxpoint/Makefile.inc M src/southbridge/intel/lynxpoint/pmutil.c 6 files changed, 34 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/26926/40 -- To view, visit https://review.coreboot.org/c/coreboot/+/26926 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3b7b29f4a24c0fb830ff76fe31a35b6afcae4e67 Gerrit-Change-Number: 26926 Gerrit-PatchSet: 40 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCK
by Arthur Heymans (Code Review) 14 Apr '19

14 Apr '19

Hello Patrick Rudolph, Julius Werner, Matt DeVillier, Paul Menzel, build bot (Jenkins), Patrick Georgi, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/26859 to look at the new patch set (#46). Change subject: cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCK ...................................................................... cpu/intel/haswell: Use C_ENVIRONMENT_BOOTBLOCK This puts the cache as ram in the bootblock. Before setting up cache as ram the microcode updates are applied. This removes the possibility for a normal/fallback setup although implementing this should be quite easy. This adds a linker symbol _car_bist_result to easily share to bist result between stages. Tested on Google peppy (Acer C720). Setting up LPC in the bootblock to output console on SuperIOs is not done in this patch. Change-Id: Ia96499a9d478127f6b9d880883ac41397b58dbea Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/car/non-evict/cache_as_ram.S M src/cpu/intel/haswell/Kconfig M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/haswell/bootblock.c M src/northbridge/intel/haswell/Kconfig M src/northbridge/intel/haswell/Makefile.inc M src/northbridge/intel/haswell/bootblock.c M src/southbridge/intel/lynxpoint/Kconfig M src/southbridge/intel/lynxpoint/Makefile.inc M src/southbridge/intel/lynxpoint/bootblock.c M src/southbridge/intel/lynxpoint/early_pch.c 11 files changed, 49 insertions(+), 77 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/26859/46 -- To view, visit https://review.coreboot.org/c/coreboot/+/26859 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia96499a9d478127f6b9d880883ac41397b58dbea Gerrit-Change-Number: 26859 Gerrit-PatchSet: 46 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newpatchset

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Change in ...coreboot[master]: TESTONLY: add power res device
by Furquan Shaikh (Code Review) 13 Apr '19

13 Apr '19

Furquan Shaikh has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/32186 ) Change subject: TESTONLY: add power res device ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/32186 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia044ef40be9cbafc8a612633151ee636e5f341a2 Gerrit-Change-Number: 32186 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: abandon

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Change in ...coreboot[master]: sb/intel/common: Fix config name in a comment
by Nico Huber (Code Review) 13 Apr '19

13 Apr '19

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32314 Change subject: sb/intel/common: Fix config name in a comment ...................................................................... sb/intel/common: Fix config name in a comment This sneaked in after we made unknown arguments to CONFIG() an error. Change-Id: Ia1de78ce1d3277c7b094c3283455f4b56f3a3fbb Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/southbridge/intel/common/pmclib.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/32314/1 diff --git a/src/southbridge/intel/common/pmclib.h b/src/southbridge/intel/common/pmclib.h index 7de5f97..075f707 100644 --- a/src/southbridge/intel/common/pmclib.h +++ b/src/southbridge/intel/common/pmclib.h @@ -18,7 +18,7 @@ #define INTEL_COMMON_PMCLIB_H /* - * Returns 1 if platform was in ACPI S3 power state and CONFIG(ACPI_RESUME) + * Returns 1 if platform was in ACPI S3 power state and CONFIG(HAVE_ACPI_RESUME) * is enabled else returns 0. */ int southbridge_detect_s3_resume(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/32314 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia1de78ce1d3277c7b094c3283455f4b56f3a3fbb Gerrit-Change-Number: 32314 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: sb/intel/i82801gx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB
by Patrick Rudolph (Code Review) 13 Apr '19

13 Apr '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32041 Change subject: sb/intel/i82801gx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB ...................................................................... sb/intel/i82801gx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB Use common code to detect ACPI S3. Untested. Change-Id: Ia759a9ed141efc8130860300f2a8961f0c084d70 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/asrock/g41c-gs/romstage.c M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/asus/p5qpl-am/romstage.c M src/mainboard/foxconn/g41s-k/romstage.c M src/mainboard/getac/p470/romstage.c M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/intel/dg41wv/romstage.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/lenovo/thinkcentre_a58/romstage.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/lenovo/z61t/romstage.c M src/mainboard/roda/rk886ex/romstage.c M src/northbridge/intel/pineview/romstage.c M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801gx/Makefile.inc D src/southbridge/intel/i82801gx/early_lpc.c M src/southbridge/intel/i82801gx/i82801gx.h 21 files changed, 19 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/32041/1 diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 479ab59..c524446 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -29,6 +29,7 @@ #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> +#include <southbridge/intel/common/pmclib.h> static void ich7_enable_lpc(void) { diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index 8cf3487..de73d01 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -23,6 +23,7 @@ #include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/x4x.h> #include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6776/nct6776.h> diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index ffb3bf9..ae19526 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -32,6 +32,7 @@ #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> +#include <southbridge/intel/common/pmclib.h> #include <cpu/x86/msr.h> #include <cpu/intel/speedstep.h> #include <arch/cpu.h> diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index 6295a53..8ce5979 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -27,6 +27,7 @@ #include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/x4x.h> #include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c index 47a7d40..01c6edd 100644 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ b/src/mainboard/foxconn/g41s-k/romstage.c @@ -22,6 +22,7 @@ #include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/x4x.h> #include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8720f/it8720f.h> diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 423b4e8..cef208a 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -28,6 +28,7 @@ #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> +#include <southbridge/intel/common/pmclib.h> #include "option_table.h" static void setup_special_ich7_gpios(void) diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c index b2d4bb4..fe3a269 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c @@ -28,6 +28,7 @@ #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> +#include <southbridge/intel/common/pmclib.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index 7c03399..e20fb7a 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -20,6 +20,7 @@ #include <console/console.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 1257fa5..eb62548 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -31,6 +31,7 @@ #include <southbridge/intel/i82801gx/i82801gx.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> +#include <southbridge/intel/common/pmclib.h> #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1) #define SUPERIO_DEV PNP_DEV(0x4e, 0) diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 18a7721..ba9a812 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -26,6 +26,7 @@ #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> +#include <southbridge/intel/common/pmclib.h> #define SERIAL_DEV PNP_DEV(0x2e, LPC47M15X_SP1) #define PME_DEV PNP_DEV(0x2e, LPC47M15X_PME) diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c index 345e4b7..2d6e916 100644 --- a/src/mainboard/intel/dg41wv/romstage.c +++ b/src/mainboard/intel/dg41wv/romstage.c @@ -23,6 +23,7 @@ #include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/x4x.h> #include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 52432a0..a419881 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -30,6 +30,7 @@ #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> +#include <southbridge/intel/common/pmclib.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627thg/w83627thg.h> diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c index f377c89..e410351 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c +++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c @@ -18,6 +18,7 @@ #include <console/console.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 39e0ed5..8391343 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -33,6 +33,7 @@ #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/common/pmclib.h> #include "dock.h" static void ich7_enable_lpc(void) diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 45cd9ec..30edfa3 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -33,6 +33,7 @@ #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/common/pmclib.h> #include "dock.h" static void ich7_enable_lpc(void) diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index dbc4b6c..819c666 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -30,6 +30,7 @@ #include <northbridge/intel/i945/i945.h> #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> +#include <southbridge/intel/common/pmclib.h> #include "option_table.h" static void ich7_enable_lpc(void) diff --git a/src/northbridge/intel/pineview/romstage.c b/src/northbridge/intel/pineview/romstage.c index cf1da63..7f4473c 100644 --- a/src/northbridge/intel/pineview/romstage.c +++ b/src/northbridge/intel/pineview/romstage.c @@ -27,6 +27,7 @@ #include <romstage_handoff.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/common/pmclib.h> #include <cpu/intel/romstage.h> #include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index d4615fa..a7d65c5 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -25,6 +25,7 @@ select SOUTHBRIDGE_INTEL_COMMON_GPIO select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI + select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select HAVE_INTEL_CHIPSET_LOCKDOWN select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select INTEL_HAS_TOP_SWAP diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc index 290794b..b72ca23 100644 --- a/src/southbridge/intel/i82801gx/Makefile.inc +++ b/src/southbridge/intel/i82801gx/Makefile.inc @@ -34,6 +34,6 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c -romstage-y += early_smbus.c early_lpc.c +romstage-y += early_smbus.c endif diff --git a/src/southbridge/intel/i82801gx/early_lpc.c b/src/southbridge/intel/i82801gx/early_lpc.c deleted file mode 100644 index a52fb85..0000000 --- a/src/southbridge/intel/i82801gx/early_lpc.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <arch/acpi.h> -#include "i82801gx.h" - -int southbridge_detect_s3_resume(void) -{ - u32 reg32; - - /* Read PM1_CNT */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); - if (((reg32 >> 10) & 7) == 5) { - if (!acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); - } else { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - return 1; - } - } - - return 0; -} diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 1e7dfdb..3db5d49 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -48,7 +48,6 @@ int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf); int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf); -int southbridge_detect_s3_resume(void); #endif #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/32041 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia759a9ed141efc8130860300f2a8961f0c084d70 Gerrit-Change-Number: 32041 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newchange

3 5

Change in ...coreboot[master]: sb/intel/lynxpoint: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB
by Patrick Rudolph (Code Review) 13 Apr '19

13 Apr '19

Patrick Rudolph has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32039 ) Change subject: sb/intel/lynxpoint: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB ...................................................................... sb/intel/lynxpoint: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB Use common code to detect ACPI S3. Untested. Change-Id: I87ac56e4ba1fb83761786d5f32a0fc308ee9718a Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32039 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/southbridge/intel/lynxpoint/Kconfig M src/southbridge/intel/lynxpoint/early_pch.c 2 files changed, 3 insertions(+), 21 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 87e1970..431744f 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -26,6 +26,7 @@ select SOUTHBRIDGE_INTEL_COMMON_SPI select SOUTHBRIDGE_INTEL_COMMON_ACPI_MADT select SOUTHBRIDGE_INTEL_COMMON_FINALIZE + select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select IOAPIC select HAVE_SMI_HANDLER select HAVE_USBDEBUG_OPTIONS diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 994021c..3d2d2c4 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -19,6 +19,7 @@ #include <device/pci_ops.h> #include <device/device.h> #include <device/pci_def.h> +#include <southbridge/intel/common/pmclib.h> #include <elog.h> #include "pch.h" #include "chip.h" @@ -67,26 +68,6 @@ printk(BIOS_DEBUG, " done.\n"); } -static int sleep_type_s3(void) -{ - u32 pm1_cnt; - u16 pm1_sts; - int is_s3 = 0; - - /* Check PM1_STS[15] to see if we are waking from Sx */ - pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); - if (pm1_sts & WAK_STS) { - /* Read PM1_CNT[12:10] to determine which Sx state */ - pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); - if (((pm1_cnt >> 10) & 7) == SLP_TYP_S3) { - /* Clear SLP_TYPE. */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); - is_s3 = 1; - } - } - return is_s3; -} - void pch_enable_lpc(void) { const struct device *dev = pcidev_on_root(0x1f, 0); @@ -148,7 +129,7 @@ /* Mainboard RCBA settings */ pch_config_rcba(rcba_config); - wake_from_s3 = sleep_type_s3(); + wake_from_s3 = southbridge_detect_s3_resume(); #if CONFIG(ELOG_BOOT_COUNT) if (!wake_from_s3) -- To view, visit https://review.coreboot.org/c/coreboot/+/32039 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I87ac56e4ba1fb83761786d5f32a0fc308ee9718a Gerrit-Change-Number: 32039 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...coreboot[master]: sb/intel/i82801jx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB
by Patrick Rudolph (Code Review) 13 Apr '19

13 Apr '19

Patrick Rudolph has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32038 ) Change subject: sb/intel/i82801jx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB ...................................................................... sb/intel/i82801jx: Use SOUTHBRIDGE_INTEL_COMMON_PMCLIB Use common code to detect ACPI S3. Untested. Change-Id: I2264c087b317f70506817b5458295a17e83b1efc Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32038 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/asus/p5qc/romstage.c M src/mainboard/intel/dg43gt/romstage.c M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/i82801jx/Makefile.inc D src/southbridge/intel/i82801jx/early_lpc.c M src/southbridge/intel/i82801jx/i82801jx.h 6 files changed, 3 insertions(+), 45 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/asus/p5qc/romstage.c b/src/mainboard/asus/p5qc/romstage.c index 2161567..a818b74 100644 --- a/src/mainboard/asus/p5qc/romstage.c +++ b/src/mainboard/asus/p5qc/romstage.c @@ -18,6 +18,7 @@ #include <console/console.h> #include <southbridge/intel/i82801jx/i82801jx.h> #include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c index 4e47426..c7ef09d 100644 --- a/src/mainboard/intel/dg43gt/romstage.c +++ b/src/mainboard/intel/dg43gt/romstage.c @@ -18,6 +18,7 @@ #include <console/console.h> #include <southbridge/intel/i82801jx/i82801jx.h> #include <southbridge/intel/common/gpio.h> +#include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index 2bc18fa..be2d289 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -20,6 +20,7 @@ select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ + select SOUTHBRIDGE_INTEL_COMMON_PMCLIB select IOAPIC select HAVE_USBDEBUG select USE_WATCHDOG_ON_BOOT diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc index c21a61a..c333566 100644 --- a/src/southbridge/intel/i82801jx/Makefile.inc +++ b/src/southbridge/intel/i82801jx/Makefile.inc @@ -34,6 +34,5 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c romstage-y += early_smbus.c -romstage-y += early_lpc.c endif diff --git a/src/southbridge/intel/i82801jx/early_lpc.c b/src/southbridge/intel/i82801jx/early_lpc.c deleted file mode 100644 index a59fdcc..0000000 --- a/src/southbridge/intel/i82801jx/early_lpc.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <arch/acpi.h> -#include "i82801jx.h" - -int southbridge_detect_s3_resume(void) -{ - u32 reg32; - - /* Read PM1_CNT */ - reg32 = inl(DEFAULT_PMBASE + 0x04); - printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); - if (((reg32 >> 10) & 7) == 5) { - if (!acpi_s3_resume_allowed()) { - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); - } else { - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); - return 1; - } - } - - return 0; -} diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index 2a85d5a..80d6cbd 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -240,7 +240,6 @@ int smbus_block_read(unsigned int device, unsigned int cmd, u8 bytes, u8 *buf); int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf); -int southbridge_detect_s3_resume(void); #endif #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/32038 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2264c087b317f70506817b5458295a17e83b1efc Gerrit-Change-Number: 32038 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in ...coreboot[master]: sb/intel/common: Add common detect_s3_resume
by Patrick Rudolph (Code Review) 13 Apr '19

13 Apr '19

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32036 Change subject: sb/intel/common: Add common detect_s3_resume ...................................................................... sb/intel/common: Add common detect_s3_resume Add a common detect_s3_resume function. Will be used by other southbridge code. TODO: Merge with soc/intel/common/*/pmclib Change-Id: I88023af522afac8164f068b0fbe0eac601aef702 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/southbridge/intel/common/Kconfig M src/southbridge/intel/common/Makefile.inc A src/southbridge/intel/common/pmclib.c A src/southbridge/intel/common/pmclib.h 4 files changed, 83 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/32036/1 diff --git a/src/southbridge/intel/common/Kconfig b/src/southbridge/intel/common/Kconfig index 6a96277..308c4f4 100644 --- a/src/southbridge/intel/common/Kconfig +++ b/src/southbridge/intel/common/Kconfig @@ -6,6 +6,9 @@ bool select HAVE_CF9_RESET +config SOUTHBRIDGE_INTEL_COMMON_PMCLIB + def_bool n + config SOUTHBRIDGE_INTEL_COMMON_GPIO def_bool n diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 3ad7924..ac339a2 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -25,6 +25,8 @@ romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c ramstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS) += smbus.c +romstage-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB) += pmclib.c + ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_COMMON),y) romstage-y += pmbase.c diff --git a/src/southbridge/intel/common/pmclib.c b/src/southbridge/intel/common/pmclib.c new file mode 100644 index 0000000..198562b --- /dev/null +++ b/src/southbridge/intel/common/pmclib.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <arch/acpi.h> +#include <console/console.h> + +#include "pmclib.h" +#include "pmbase.h" +#include "pmutil.h" + +int southbridge_detect_s3_resume(void) +{ + u32 pm1_cnt; + u16 pm1_sts; + int is_s3 = 0; + + /* Check PM1_STS[15] to see if we are waking from Sx */ + pm1_sts = read_pmbase16(PM1_STS); + if (pm1_sts & WAK_STS) { + /* Read PM1_CNT[12:10] to determine which Sx state */ + pm1_cnt = read_pmbase32(PM1_CNT); + if (((pm1_cnt >> 10) & 7) == SLP_TYP_S3) { + /* Clear SLP_TYPE. */ + write_pmbase32(PM1_CNT, pm1_cnt & ~(7 << 10)); + is_s3 = 1; + } + } + if (is_s3) { + if (!acpi_s3_resume_allowed()) { + printk(BIOS_DEBUG, "SB: Resume from S3 detected, but disabled.\n"); + return 0; + } + + printk(BIOS_DEBUG, "SB: Resume from S3 detected.\n"); + } + + return is_s3; +} diff --git a/src/southbridge/intel/common/pmclib.h b/src/southbridge/intel/common/pmclib.h new file mode 100644 index 0000000..7de5f97 --- /dev/null +++ b/src/southbridge/intel/common/pmclib.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef INTEL_COMMON_PMCLIB_H +#define INTEL_COMMON_PMCLIB_H + +/* + * Returns 1 if platform was in ACPI S3 power state and CONFIG(ACPI_RESUME) + * is enabled else returns 0. + */ +int southbridge_detect_s3_resume(void); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/32036 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88023af522afac8164f068b0fbe0eac601aef702 Gerrit-Change-Number: 32036 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 6

Change in ...coreboot[master]: {drivers,mb,soc/intel/braswell}: Add support for Braswell FSP MR2
by Nico Huber (Code Review) 13 Apr '19

13 Apr '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29661 ) Change subject: {drivers,mb,soc/intel/braswell}: Add support for Braswell FSP MR2 ...................................................................... Patch Set 9: (2 comments) I like the solution with the move of UPDs to the mainboards. But that still leaves the settings in the soc's chip.h, right? https://review.coreboot.org/#/c/29661/9//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29661/9//COMMIT_MSG@16 PS9, Line 16: "../../../3rdparty/fsp/BraswellFspBinPkg" I've been looking through the patch and couldn't find this. I guess, now, you meant to say that this needs to be set per mainboard? IMHO, 3rdparty/fsp/ should be the default, and main- boards that require the lost FSP version, should override it to vendorcode/intel/... Maybe we can reduce the noise of these mainboards by removing intel/strago from the tree? Does anybody care about it? https://review.coreboot.org/#/c/29661/9/src/drivers/intel/fsp1_1/Makefile.i… File src/drivers/intel/fsp1_1/Makefile.inc: https://review.coreboot.org/#/c/29661/9/src/drivers/intel/fsp1_1/Makefile.i… PS9, Line 61: endif This seems redundant with the change to braswell/Makefile.inc and the existing in vendorcode/intel/? -- To view, visit https://review.coreboot.org/c/coreboot/+/29661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id40b5d46ddda93845d9739b56aaf7ad24ee89246 Gerrit-Change-Number: 29661 Gerrit-PatchSet: 9 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Huang Jin <huang.jin(a)intel.com> Gerrit-Reviewer: Lee Leahy <leroy.p.leahy(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 13 Apr 2019 13:39:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: soc/intel/braswell: Remove disabled LPE ACPI code
by Nico Huber (Code Review) 13 Apr '19

13 Apr '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29414 ) Change subject: soc/intel/braswell: Remove disabled LPE ACPI code ...................................................................... Patch Set 8: (1 comment) > > One of these patches where already too many people > > stated their opinion (I'll try anyway). This often > > happens when the problem description is unclear. > > > > Frans, is this a cosmetic issue? that you just want > > to get rid of unneeded code? or do you experience > > any trouble because of the spurious code? > > Experience slow system running Linux. Even reporting _STA disabled, > Linux remains requesting the _STA() of this device. So it's a workaround for a problem that we don't understand? The issue I see here is that this solution adds a lot of redundant code. Usually such code ends up being refactored so it's very likely that such a workaround for an undocumented problem won't survive long. Please state the reason for this change in the commit message (we should do that always, anyway) and provide enough detail to reproduce the issue. Otherwise, future work on the code can't be checked for regressions. https://review.coreboot.org/#/c/29414/8/src/soc/intel/braswell/acpi/southcl… File src/soc/intel/braswell/acpi/southcluster.asl: https://review.coreboot.org/#/c/29414/8/src/soc/intel/braswell/acpi/southcl… PS8, Line 291: Can't we simply move this #include to each mainboard? That would be a -3/+6 patch and we'd have a reasonable place where we could comment why this was done. -- To view, visit https://review.coreboot.org/c/coreboot/+/29414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73 Gerrit-Change-Number: 29414 Gerrit-PatchSet: 8 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 13 Apr 2019 13:11:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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