coreboot-gerrit April 2019

coreboot-gerrit@coreboot.org

1 participants
1219 discussions

Change in ...coreboot[master]: Docs/kconfig: Update to use CONFIG()
by Nico Huber (Code Review) 08 Apr '19

08 Apr '19

Hello HAOUAS Elyes, Julius Werner, Angel Pons, Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32228 to review the following change. Change subject: Docs/kconfig: Update to use CONFIG() ...................................................................... Docs/kconfig: Update to use CONFIG() Change-Id: Ica7b601d1c9c3bcf39b8b805d48e969f8a944927 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M Documentation/getting_started/kconfig.md 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/32228/1 diff --git a/Documentation/getting_started/kconfig.md b/Documentation/getting_started/kconfig.md index 7b436ce..249fd46 100644 --- a/Documentation/getting_started/kconfig.md +++ b/Documentation/getting_started/kconfig.md @@ -1132,7 +1132,7 @@ as false, the symbol STILL gets defined in the config.h file (though not in the .config file). -Use \#if IS_ENABLED(CONFIG_*) to be sure (it returns false for undefined symbols +Use \#if CONFIG(SYMBOL) to be sure (it returns false for undefined symbols and defined-to-0 symbols alike). -- To view, visit https://review.coreboot.org/c/coreboot/+/32228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica7b601d1c9c3bcf39b8b805d48e969f8a944927 Gerrit-Change-Number: 32228 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: nb/amd/pi/agesawrapper: Drop stale comment about IS_ENABLED()
by Nico Huber (Code Review) 08 Apr '19

08 Apr '19

Hello HAOUAS Elyes, Julius Werner, Angel Pons, Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32227 to review the following change. Change subject: nb/amd/pi/agesawrapper: Drop stale comment about IS_ENABLED() ...................................................................... nb/amd/pi/agesawrapper: Drop stale comment about IS_ENABLED() We decided to not care about compile-time errors. So drop the comment, the code was updated already. Change-Id: Ib115fa6e2c48bfde7f67c327d42b3fe0e7af8c1f Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/northbridge/amd/pi/agesawrapper.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/32227/1 diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index 1cc7b7c..cda5e01 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -125,8 +125,6 @@ AmdCreateStruct (&AmdParamStruct); PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; - // Do not use IS_ENABLED here. CONFIG_GFXUMA should always have a value. Allow - // the compiler to flag the error if CONFIG_GFXUMA is not set. PostParams->MemConfig.UmaMode = CONFIG(GFXUMA) ? UMA_AUTO : UMA_NONE; PostParams->MemConfig.UmaSize = 0; PostParams->MemConfig.BottomIo = (UINT16) -- To view, visit https://review.coreboot.org/c/coreboot/+/32227 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib115fa6e2c48bfde7f67c327d42b3fe0e7af8c1f Gerrit-Change-Number: 32227 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 4

Change in ...coreboot[master]: commonlib/cbfs: Check for presence of CONFIG() macro
by Nico Huber (Code Review) 08 Apr '19

08 Apr '19

Hello HAOUAS Elyes, Julius Werner, Angel Pons, Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32226 to review the following change. Change subject: commonlib/cbfs: Check for presence of CONFIG() macro ...................................................................... commonlib/cbfs: Check for presence of CONFIG() macro Check for CONFIG not IS_ENABLED, as we use the former now. Change-Id: I7e1b67bc0894ca6f0149039054449656b58bcdd3 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/commonlib/cbfs.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/32226/1 diff --git a/src/commonlib/cbfs.c b/src/commonlib/cbfs.c index 250a72a..4379099 100644 --- a/src/commonlib/cbfs.c +++ b/src/commonlib/cbfs.c @@ -25,7 +25,7 @@ #if !defined(LOG) #define LOG(x...) printk(BIOS_INFO, "CBFS: " x) #endif -#if defined(IS_ENABLED) +#if defined(CONFIG) #if CONFIG(DEBUG_CBFS) #define DEBUG(x...) printk(BIOS_SPEW, "CBFS: " x) -- To view, visit https://review.coreboot.org/c/coreboot/+/32226 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e1b67bc0894ca6f0149039054449656b58bcdd3 Gerrit-Change-Number: 32226 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 5

Change in ...coreboot[master]: soc/amd/stoney: Don't use IS_ENABLED() for a constant
by Nico Huber (Code Review) 08 Apr '19

08 Apr '19

Hello HAOUAS Elyes, Julius Werner, Angel Pons, Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32225 to review the following change. Change subject: soc/amd/stoney: Don't use IS_ENABLED() for a constant ...................................................................... soc/amd/stoney: Don't use IS_ENABLED() for a constant IS_ENABLED() was supposed for Kconfig options. Change-Id: Ia40d64856cd89586133e54ff6e02c35d6b647059 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/amd/stoneyridge/acpi/lpc.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/32225/1 diff --git a/src/soc/amd/stoneyridge/acpi/lpc.asl b/src/soc/amd/stoneyridge/acpi/lpc.asl index e24514c..93b4056 100644 --- a/src/soc/amd/stoneyridge/acpi/lpc.asl +++ b/src/soc/amd/stoneyridge/acpi/lpc.asl @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#if IS_ENABLED(MAINBOARD_HAS_SPEAKER) +#if MAINBOARD_HAS_SPEAKER #define IO61_HID "PNP0800" /* AT style speaker */ #else #define IO61_HID "PNP0C02" /* reserved resource */ -- To view, visit https://review.coreboot.org/c/coreboot/+/32225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia40d64856cd89586133e54ff6e02c35d6b647059 Gerrit-Change-Number: 32225 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 5

Change in ...coreboot[master]: Replace remaining IS_ENABLED(CONFIG_*) with CONFIG()
by Nico Huber (Code Review) 08 Apr '19

08 Apr '19

Hello HAOUAS Elyes, Julius Werner, Angel Pons, Patrick Georgi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/32224 to review the following change. Change subject: Replace remaining IS_ENABLED(CONFIG_*) with CONFIG() ...................................................................... Replace remaining IS_ENABLED(CONFIG_*) with CONFIG() Another run of find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g' Change-Id: I3243197ab852a3fbc3eb2e2e782966a350b78af2 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- M src/include/symbols.h M src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/cannonlake/include/soc/serialio.h 4 files changed, 5 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/32224/1 diff --git a/src/include/symbols.h b/src/include/symbols.h index c35e191..b67286a 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -71,7 +71,7 @@ * (Does not necessarily mean that the memory is accessible.) */ static inline int preram_symbols_available(void) { - return !IS_ENABLED(CONFIG_CACHE_AS_RAM) || ENV_CACHE_AS_RAM; + return !CONFIG(CACHE_AS_RAM) || ENV_CACHE_AS_RAM; } #endif /* __SYMBOLS_H */ diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c index e345146..ec8f58b 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/gpio.c @@ -264,8 +264,7 @@ /* H21 : GPPC_H_21 */ /* H22 : GPPC_H_22 */ PAD_CFG_GPI(GPP_H22, NONE, DEEP), -#if IS_ENABLED(CONFIG_BOARD_INTEL_WHISKEYLAKE_RVP) || \ - IS_ENABLED(CONFIG_BOARD_INTEL_COMETLAKE_RVP) +#if CONFIG(BOARD_INTEL_WHISKEYLAKE_RVP) || CONFIG(BOARD_INTEL_COMETLAKE_RVP) PAD_CFG_GPO(GPP_H22, 1, PLTRST), #else PAD_CFG_GPI(GPP_H22, NONE, DEEP), diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 2688557..b8dba18 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -64,7 +64,7 @@ return PCH_SERIAL_IO_INDEX(config->SerialIoDevMode[dev_offset]); } -#if IS_ENABLED(CONFIG_SOC_INTEL_COMETLAKE) +#if CONFIG(SOC_INTEL_COMETLAKE) static void parse_devicetree_param(const config_t *config, FSP_S_CONFIG *params) { uint32_t dev_offset = 0; @@ -254,7 +254,7 @@ /* Enable CNVi Wifi if enabled in device tree */ dev = dev_find_slot(0, PCH_DEVFN_CNViWIFI); -#if IS_ENABLED(CONFIG_SOC_INTEL_COMETLAKE) +#if CONFIG(SOC_INTEL_COMETLAKE) params->CnviMode = dev->enabled; #else params->PchCnviMode = dev->enabled; diff --git a/src/soc/intel/cannonlake/include/soc/serialio.h b/src/soc/intel/cannonlake/include/soc/serialio.h index 6c95356..c92bd2d 100644 --- a/src/soc/intel/cannonlake/include/soc/serialio.h +++ b/src/soc/intel/cannonlake/include/soc/serialio.h @@ -17,7 +17,7 @@ #ifndef _SERIALIO_H_ #define _SERIALIO_H_ -#if IS_ENABLED(CONFIG_SOC_INTEL_COMETLAKE) +#if CONFIG(SOC_INTEL_COMETLAKE) typedef enum { PchSerialIoNotInitialized, PchSerialIoDisabled, -- To view, visit https://review.coreboot.org/c/coreboot/+/32224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3243197ab852a3fbc3eb2e2e782966a350b78af2 Gerrit-Change-Number: 32224 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 5

Change in ...coreboot[master]: src/soc/intel/braswell: Remove disabled LPE ACPI code
by Nico Huber (Code Review) 08 Apr '19

08 Apr '19

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29414 ) Change subject: src/soc/intel/braswell: Remove disabled LPE ACPI code ...................................................................... Patch Set 6: One of these patches where already too many people stated their opinion (I'll try anyway). This often happens when the problem description is unclear. Frans, is this a cosmetic issue? that you just want to get rid of unneeded code? or do you experience any trouble because of the spurious code? -- To view, visit https://review.coreboot.org/c/coreboot/+/29414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73 Gerrit-Change-Number: 29414 Gerrit-PatchSet: 6 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 08 Apr 2019 16:04:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in ...coreboot[master]: nb/intel/pineview: Correct unsigned integer check in msbpos
by Jacob Garber (Code Review) 08 Apr '19

08 Apr '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32054 Change subject: nb/intel/pineview: Correct unsigned integer check in msbpos ...................................................................... nb/intel/pineview: Correct unsigned integer check in msbpos The check i >= 0 is always true for an unsigned integer, causing msbpos(0) to hang. We correct it to i != 0. Note this has no material change since the code guards against finding the msb of 0 anyway, but it fixes Coverity CID 1347386. Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Change-Id: Ic5be50846cc545dcd48593e5ed3fd6068a6104cb --- M src/northbridge/intel/pineview/raminit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/32054/1 diff --git a/src/northbridge/intel/pineview/raminit.c b/src/northbridge/intel/pineview/raminit.c index fa5122a..4f9a0b4 100644 --- a/src/northbridge/intel/pineview/raminit.c +++ b/src/northbridge/intel/pineview/raminit.c @@ -336,7 +336,7 @@ static u8 msbpos(u8 val) //Reverse { u8 i; - for (i = 7; (i >= 0) && ((val & (1 << i)) == 0); i--); + for (i = 7; (i != 0) && ((val & (1 << i)) == 0); i--); return i; } -- To view, visit https://review.coreboot.org/c/coreboot/+/32054 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5be50846cc545dcd48593e5ed3fd6068a6104cb Gerrit-Change-Number: 32054 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

5 11

Change in ...coreboot[master]: soc/intel/baytrail: Correct array bounds check
by Jacob Garber (Code Review) 08 Apr '19

08 Apr '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32125 Change subject: soc/intel/baytrail: Correct array bounds check ...................................................................... soc/intel/baytrail: Correct array bounds check If `gms == ARRAY_SIZE(gms_size_map)`, then we will have an out of bounds read. Fix the check to exclude this case. This was partially fixed in 04f68c1 (baytrail: fix range check). Found-by: Coverity Scan, CID 1229677 (OVERRUN) Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Change-Id: I8c8cd59df49beea066b46cde3cf00237816aff33 --- M src/soc/intel/baytrail/gfx.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/32125/1 diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 73c0d15..eaec46b 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -50,7 +50,7 @@ gms = pci_read_config32(dev, GGC) & GGC_GSM_SIZE_MASK; gms >>= 3; - if (gms > ARRAY_SIZE(gms_size_map)) + if (gms >= ARRAY_SIZE(gms_size_map)) return; gmsize = gms_size_map[gms]; -- To view, visit https://review.coreboot.org/c/coreboot/+/32125 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8c8cd59df49beea066b46cde3cf00237816aff33 Gerrit-Change-Number: 32125 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

3 3

Change in ...coreboot[master]: northbridge/amd/pi: Fix null pointer check
by Jacob Garber (Code Review) 08 Apr '19

08 Apr '19

Jacob Garber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32022 Change subject: northbridge/amd/pi: Fix null pointer check ...................................................................... northbridge/amd/pi: Fix null pointer check - The `dev` pointer was being dereferenced before the null check. This fixes Coverity CID 1241851 (REVERSE_INULL) - Apply clang-format whitespace cleanups Signed-off-by: Jacob Garber <jgarber1(a)ualberta.ca> Change-Id: Ie578787c3c26a1f3acb4567c135486667e88a888 --- M src/northbridge/amd/pi/00730F01/dimmSpd.c 1 file changed, 9 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/32022/1 diff --git a/src/northbridge/amd/pi/00730F01/dimmSpd.c b/src/northbridge/amd/pi/00730F01/dimmSpd.c index 79e046e..bdfb074 100644 --- a/src/northbridge/amd/pi/00730F01/dimmSpd.c +++ b/src/northbridge/amd/pi/00730F01/dimmSpd.c @@ -24,13 +24,16 @@ #include <northbridge/amd/pi/dimmSpd.h> -AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PARAMS *info) +AGESA_STATUS AmdMemoryReadSPD(UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PARAMS *info) { - int spdAddress; DEVTREE_CONST struct device *dev = pcidev_on_root(0x18, 2); + + if (dev == 0) + return AGESA_ERROR; + DEVTREE_CONST struct northbridge_amd_pi_00730F01_config *config = dev->chip_info; - if ((dev == 0) || (config == 0)) + if (config == 0) return AGESA_ERROR; if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup)) @@ -40,13 +43,13 @@ if (info->DimmId >= ARRAY_SIZE(config->spdAddrLookup[0][0])) return AGESA_ERROR; - spdAddress = config->spdAddrLookup - [info->SocketId] [info->MemChannelId] [info->DimmId]; + int spdAddress = config->spdAddrLookup + [info->SocketId][info->MemChannelId][info->DimmId]; if (spdAddress == 0) return AGESA_ERROR; - int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 128); + int err = hudson_readSpd(spdAddress, (void *)info->Buffer, 128); if (err) return AGESA_ERROR; return AGESA_SUCCESS; -- To view, visit https://review.coreboot.org/c/coreboot/+/32022 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie578787c3c26a1f3acb4567c135486667e88a888 Gerrit-Change-Number: 32022 Gerrit-PatchSet: 1 Gerrit-Owner: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-MessageType: newchange

6 15

Change in ...coreboot[master]: soc/skl: Update SkipExtGfxScan in UPD from devtree
by Maxim Polyakov (Code Review) 08 Apr '19

08 Apr '19

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32170 Change subject: soc/skl: Update SkipExtGfxScan in UPD from devtree ...................................................................... soc/skl: Update SkipExtGfxScan in UPD from devtree The SkipExtGfxScan option is defined in the device tree, but doesn`t update the value in the UPD. It uses the default value - 0. This means that the FSP will scan all external graphics devices, in spite of the configuration in devicetree.cb for a specific board. Patch updates SkipExtGfxScan options in UPD from devicetree.cb. This change affects all boards with skl/kbl processor. Change-Id: Ie88a41bdf31f7c3e88df6c70c82a1cbf866372c4 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/skylake/romstage/romstage_fsp20.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/32170/1 diff --git a/src/soc/intel/skylake/romstage/romstage_fsp20.c b/src/soc/intel/skylake/romstage/romstage_fsp20.c index b65c9ff..b0bf9bd 100644 --- a/src/soc/intel/skylake/romstage/romstage_fsp20.c +++ b/src/soc/intel/skylake/romstage/romstage_fsp20.c @@ -298,6 +298,7 @@ /* Set primary graphic device */ soc_primary_gfx_config_params(m_cfg, config); + m_t_cfg->SkipExtGfxScan = config->SkipExtGfxScan; mainboard_memory_init_params(mupd); } -- To view, visit https://review.coreboot.org/c/coreboot/+/32170 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie88a41bdf31f7c3e88df6c70c82a1cbf866372c4 Gerrit-Change-Number: 32170 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

3 3

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2019