Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/29321 )
Change subject: {src,util}: Correct typo in comment and debug string
......................................................................
{src,util}: Correct typo in comment and debug string
Correct typo in comment and debug string.
BUG=N/A
TEST=build
Change-Id: I0362bb8d7c883e7fcbc6a2fc2f9918251f0d8d6e
Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29321
Reviewed-by: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/security/tpm/tss.h
M src/security/tpm/tss/tcg-2.0/tss_marshaling.c
M src/soc/intel/braswell/include/soc/irq.h
3 files changed, 4 insertions(+), 4 deletions(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Michał Żygowski: Looks good to me, approved
diff --git a/src/security/tpm/tss.h b/src/security/tpm/tss.h
index 807cb46..548a39a 100644
--- a/src/security/tpm/tss.h
+++ b/src/security/tpm/tss.h
@@ -144,7 +144,7 @@
uint32_t tlcl_physical_presence_cmd_enable(void);
/**
- * Finalize the physical presence settings: sofware PP is enabled, hardware PP
+ * Finalize the physical presence settings: software PP is enabled, hardware PP
* is disabled, and the lifetime lock is set. The TPM error code is returned.
*/
uint32_t tlcl_finalize_physical_presence(void);
diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c
index 62bc6a9..21da73a 100644
--- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c
+++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c
@@ -471,12 +471,12 @@
}
/*
- * Let's ignore the authorisation section. It should be 5 bytes total,
+ * Let's ignore the authorization section. It should be 5 bytes total,
* just confirm that this is the case and report any discrepancy.
*/
if (ibuf_remaining(ib) != 5)
printk(BIOS_ERR,
- "%s:%d - unexpected authorisation seciton size %zd\n",
+ "%s:%d - unexpected authorization section size %zd\n",
__func__, __LINE__, ibuf_remaining(ib));
ibuf_oob_drain(ib, ibuf_remaining(ib));
diff --git a/src/soc/intel/braswell/include/soc/irq.h b/src/soc/intel/braswell/include/soc/irq.h
index f9d3700..b14d0c0 100644
--- a/src/soc/intel/braswell/include/soc/irq.h
+++ b/src/soc/intel/braswell/include/soc/irq.h
@@ -179,7 +179,7 @@
# define SCIS_IRQ23 0x07
/*
- * In each mainbaord directory there should exist a header file irqroute.h that
+ * In each mainboard directory there should exist a header file irqroute.h that
* defines the PCI_DEV_PIRQ_ROUTES and PIRQ_PIC_ROUTES macros which
* consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries.
*/
--
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0362bb8d7c883e7fcbc6a2fc2f9918251f0d8d6e
Gerrit-Change-Number: 29321
Gerrit-PatchSet: 5
Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>
Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com>
Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
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Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org>
Gerrit-MessageType: merged
Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32181
Change subject: mb/mainboard/google/sarien/variants: Set correct tcc_offset value
......................................................................
mb/mainboard/google/sarien/variants: Set correct tcc_offset value
Set new tcc_offset value to 10 degree C. This configures the Thermal
Control Circuit (TCC) activation value to 90 degree C. It prevents
any abrupt thermal shutdown while running heavy workload. This helps
to take early thermal throttling action when CPU temperature goes
above 90 degree C.
Change-Id: Ica77264782b4a3f3e72e73e1b8cb8b2e464fb033
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com>
---
M src/mainboard/google/sarien/variants/arcada/devicetree.cb
M src/mainboard/google/sarien/variants/sarien/devicetree.cb
2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/32181/1
diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
index 4bf3736..1507214 100644
--- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb
@@ -161,7 +161,7 @@
#| I2C4 | H1 TPM |
#+-------------------+---------------------------+
- register "tcc_offset" = "5"
+ register "tcc_offset" = "10"
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index caae79f..79329d5 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -158,7 +158,7 @@
#| I2C4 | H1 TPM |
#+-------------------+---------------------------+
- register "tcc_offset" = "5"
+ register "tcc_offset" = "10"
register "common_soc_config" = "{
.chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
--
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Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com>
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Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29964 )
Change subject: qcs405: Add UART support
......................................................................
Patch Set 19:
(1 comment)
https://review.coreboot.org/#/c/29964/19/src/soc/qualcomm/qcs405/uart.c
File src/soc/qualcomm/qcs405/uart.c:
https://review.coreboot.org/#/c/29964/19/src/soc/qualcomm/qcs405/uart.c@272
PS19, Line 272: IS_ENABLED(CONFIG_DRIVERS_U
We have (and use) CONFIG(DRIVERS_UART) now, see also elsewhere
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Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29957 )
Change subject: libpayload: Add UART for qcs405
......................................................................
Patch Set 20:
(1 comment)
https://review.coreboot.org/#/c/29957/20/payloads/libpayload/configs/config…
File payloads/libpayload/configs/config.mistral:
https://review.coreboot.org/#/c/29957/20/payloads/libpayload/configs/config…
PS20, Line 6: CONFIG_LP_USB=y
: CONFIG_LP_USB_EHCI=y
: CONFIG_LP_USB_XHCI=y
strictly speaking this isn't covered by the commit message
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Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29957 )
Change subject: libpayload: Add UART for qcs405
......................................................................
Patch Set 20: Code-Review+2
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Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29662 )
Change subject: soc/intel/braswell: Add C_ENVIRONMENT_BOOTBLOCK support
......................................................................
Patch Set 8:
> Patch Set 7:
>
> > Patch Set 7:
> >
> > > Patch Set 7:
> > >
> > > > Patch Set 7:
> > > >
> > > > > Patch Set 7:
> > > > >
> > > > > > Patch Set 7: Code-Review-2
> > > > > >
> > > > > > (1 comment)
> > > > > >
> > > > > > select C_ENVIRONMENT_BOOTBLOCK is the braswell Kconfig and drop the romcc bootblock option and add console init in the bootblock.
> > > > > > Also drop things that get unused in drivers/intel/fsp1_1
> > > > > > This patch is not even build tested...
> > > > >
> > > > > This patch is to support C_ENVIRONMENT_BOOTBLOCK for Braswell. To be backward compatible this support has made optional.
> > > >
> > > > Please don't make it optional and remove the 'backwards compatibility', there is really no reason to keep that around.
> > > >
> > > > > This patch has been build and tested. I will check if I made mistake by uploading.
> > > > >
> > > >
> > > > No gerrit has not build-tested it.
> > > >
> > > > > Can you clarify your comment?
> > >
> > > I concur with Arthur. C_ENVIRONMENT_BOOTBLOCK is becoming a standard in coreboot. No reason to keep backward compatibility.
> >
> > Removing backward compatibity in Braswell is no problem. Removing it from drivers/intel/fsp1_1 means also Intel Quark backward compatibility will be removed. I can verify that Intel Quark still build, but how to be sure tree is still working fine?
>
> The quark fsp1.1 option was dropped in master so no need to worry about that.
Did you look into the latest patch?
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Frans Hendriks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29414 )
Change subject: src/soc/intel/braswell: Remove disabled LPE ACPI code
......................................................................
Patch Set 6:
(1 comment)
https://review.coreboot.org/#/c/29414/5/src/soc/intel/braswell/include/soc/…
File src/soc/intel/braswell/include/soc/acpi.h:
https://review.coreboot.org/#/c/29414/5/src/soc/intel/braswell/include/soc/…
PS5, Line 29: unsigned long current,
> Doesn’t this fit on the line above?
Not all of this.
For line below 80 chars only 'unsigned long' fits.
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