Change in ...coreboot[master]: src/soc/intel/braswell/acpi/lpss.asl: Remove SPI1 and PWM asl code

[Michał Żygowski (Code Review)]

Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29417 )

Change subject: src/soc/intel/braswell/acpi/lpss.asl: Remove SPI1 and PWM asl code
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Patch Set 3:
> Patch Set 1:
> > Patch Set 1:
> >
> > Please use runtime detection and ssdt code to achieve the same functionality.
>
> The standard Intel FSP disables both SPI1 and PWM. All system using this FSP will not have the SPI1 and PWM enabled. Adding runtime detection will take boot time, where the result will be constant on these system.
>
> I dont know if Google Cyan use standard FSP binary. If so I suggest removing the SPI1 and PWM ASL code. 
> For Google Cyan the SP1 and PWM ASL code can be added to mainboard directory when required.
>
> I suggest to move this code to Google Cyan?

Since I am not familiar with peripheral usage on Chromebooks, I am adding Matt on CC.

Matt, could You please share Your opinion and possibly review the patch?