Change in ...coreboot[master]: mb/intel/coffeelake_rvp: Configure FSP UPDs of DDI ports for cmlrvp

[V Sowmya (Code Review)]

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32140

Change subject: mb/intel/coffeelake_rvp: Configure FSP UPDs of DDI ports for cmlrvp
......................................................................

mb/intel/coffeelake_rvp: Configure FSP UPDs of DDI ports for cmlrvp

This patch configures FSP UPD values for HPD and DDC of DDI ports for
CMLRVP.

BUG=none
TEST= Tested that eDP works on CMLRVP.

Change-Id: If8c8480eaf2d63cec0b5598b5af3088c630dd78a
Signed-off-by: V Sowmya 
---
M src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb
1 file changed, 13 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/32140/1

diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb
index 6484330..241ac33 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb
@@ -10,6 +10,19 @@
    register "HeciEnabled" = "1"
    register "s0ix_enable" = "1"

+	# Enable eDP device
+	register "DdiPortEdp" = "1"
+	# Enable HPD for DDI ports B/C
+	register "DdiPortBHpd" = "1"
+	register "DdiPortCHpd" = "1"
+	register "DdiPortDHpd" = "1"
+	register "DdiPortFHpd" = "1"
+	# Enable DDC for DDI ports B/C
+	register "DdiPortBDdc" = "1"
+	register "DdiPortCDdc" = "1"
+	register "DdiPortDDdc" = "1"
+	register "DdiPortFDdc" = "1"
+
    register "SerialIoDevMode" = "{
    	[PchSerialIoIndexI2C0]  = PchSerialIoPci,
    	[PchSerialIoIndexI2C1]  = PchSerialIoPci,

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32140 )

Change subject: mb/intel/coffeelake_rvp: Configure FSP UPDs of DDI ports for cmlrvp
......................................................................

Patch Set 1: Code-Review+2

[Maulik V Vaghela (Code Review)]

Maulik V Vaghela has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32140 )

Change subject: mb/intel/coffeelake_rvp: Configure FSP UPDs of DDI ports for cmlrvp
......................................................................

Patch Set 1: Code-Review+1

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32140 )

Change subject: mb/intel/coffeelake_rvp: Configure FSP UPDs of DDI ports for cmlrvp
......................................................................

mb/intel/coffeelake_rvp: Configure FSP UPDs of DDI ports for cmlrvp

This patch configures FSP UPD values for HPD and DDC of DDI ports for
CMLRVP.

BUG=none
TEST= Tested that eDP works on CMLRVP.

Change-Id: If8c8480eaf2d63cec0b5598b5af3088c630dd78a
Signed-off-by: V Sowmya 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32140
Reviewed-by: Furquan Shaikh 
Reviewed-by: Maulik V Vaghela 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb
1 file changed, 13 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Maulik V Vaghela: Looks good to me, but someone else must approve

diff --git a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb
index 6484330..241ac33 100644
--- a/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb
+++ b/src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb
@@ -10,6 +10,19 @@
    register "HeciEnabled" = "1"
    register "s0ix_enable" = "1"

+	# Enable eDP device
+	register "DdiPortEdp" = "1"
+	# Enable HPD for DDI ports B/C
+	register "DdiPortBHpd" = "1"
+	register "DdiPortCHpd" = "1"
+	register "DdiPortDHpd" = "1"
+	register "DdiPortFHpd" = "1"
+	# Enable DDC for DDI ports B/C
+	register "DdiPortBDdc" = "1"
+	register "DdiPortCDdc" = "1"
+	register "DdiPortDDdc" = "1"
+	register "DdiPortFDdc" = "1"
+
    register "SerialIoDevMode" = "{
    	[PchSerialIoIndexI2C0]  = PchSerialIoPci,
    	[PchSerialIoIndexI2C1]  = PchSerialIoPci,