Change in ...coreboot[master]: drivers/intel/gma: Add `new-pch.asl` for Skylake+

[Nico Huber (Code Review)]

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31503

Change subject: drivers/intel/gma: Add `new-pch.asl` for Skylake+
......................................................................

drivers/intel/gma: Add `new-pch.asl` for Skylake+

This should work as `pch.asl` equivalent for Skylake and later
platforms.

Untested.

Change-Id: I0b21d9a0288f0f8d6cb0a4776909bffdae7576f5
Signed-off-by: Nico Huber 
---
A src/drivers/intel/gma/acpi/new-pch.asl
1 file changed, 42 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/31503/1

diff --git a/src/drivers/intel/gma/acpi/new-pch.asl b/src/drivers/intel/gma/acpi/new-pch.asl
new file mode 100644
index 0000000..b24a350
--- /dev/null
+++ b/src/drivers/intel/gma/acpi/new-pch.asl
@@ -0,0 +1,42 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+Device (GFX0)
+{
+	Name (_ADR, 0x00020000)
+
+	OperationRegion (GFXC, PCI_Config, 0x00, 0x0100)
+	Field (GFXC, DWordAcc, NoLock, Preserve)
+	{
+		Offset (0x10),
+		BAR0, 64,
+		Offset (0xe4),
+		ASLE, 32,
+		Offset (0xfc),
+		ASLS, 32,
+	}
+
+	OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000)
+	Field (GFRG, DWordAcc, NoLock, Preserve)
+	{
+		Offset (0xc8254),
+		BCLV, 16,
+		BCLM, 16
+	}
+
+#include "configure_brightness_levels.asl"
+#include "common.asl"
+}

Change in coreboot[master]: drivers/intel/gma: Add `new-pch.asl` for Skylake+

[Benjamin Doron (Code Review)]

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31503 )

Change subject: drivers/intel/gma: Add `new-pch.asl` for Skylake+
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/31503/1/src/drivers/intel/gma/acpi/... 
File src/drivers/intel/gma/acpi/new-pch.asl:

PS1: 
Should src/soc/intel/*lake/acpi/pch.asl be including this file?

Change in coreboot[master]: drivers/intel/gma: Add `new-pch.asl` for Skylake+

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31503 )

Change subject: drivers/intel/gma: Add `new-pch.asl` for Skylake+
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/31503/1/src/drivers/intel/gma/acpi/... 
File src/drivers/intel/gma/acpi/new-pch.asl:

PS1:
> Should src/soc/intel/*lake/acpi/pch. […]

Something like that was the original idea. But people have re-invented
the wheel there, so somebody should look deeper into it.

Change in coreboot[master]: drivers/intel/gma: Add `new-pch.asl` for Skylake+

[Benjamin Doron (Code Review)]

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31503 )

Change subject: drivers/intel/gma: Add `new-pch.asl` for Skylake+
......................................................................

Patch Set 1:

(1 comment)

This change looks to require CSTE (Current Display State), NSTE (Next Display State) and DSEN (Display Output Switching Enable) added to globalnvs and the SMI trap added back to platform (https://github.com/coreboot/coreboot/commit/2e37fdddd5f859b82923485612ec8693...)

https://review.coreboot.org/c/coreboot/+/31503/1/src/drivers/intel/gma/acpi/... 
File src/drivers/intel/gma/acpi/new-pch.asl:

PS1:
> Something like that was the original idea. But people have re-invented […]

Are you referring to CB:32529 and CB:32549?

Change in coreboot[master]: drivers/intel/gma: Add `new-pch.asl` for Skylake+

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31503 )

Change subject: drivers/intel/gma: Add `new-pch.asl` for Skylake+
......................................................................

Patch Set 1:

(1 comment)
> This change looks to require CSTE (Current Display State), NSTE (Next Display State) and DSEN (Display Output Switching Enable) added to globalnvs and the SMI trap added back to platform (https://github.com/coreboot/coreboot/commit/2e37fdddd5f859b82923485612ec8693...)

Hmmm, maybe we should fix the common code first. a) The GNVS variables are never
referenced anywhere else, hence could be local variables in `gma/acpi/common.asl`.
b) The TRAP only makes sense if there is an SMI handler to handle it. Maybe we
should identify the platforms that do that and disable the call on the others.

https://review.coreboot.org/c/coreboot/+/31503/1/src/drivers/intel/gma/acpi/... 
File src/drivers/intel/gma/acpi/new-pch.asl:

PS1:
> Are you referring to CB:32529 and CB:32549?

The former probably. I've seen earlier patches too,not sure if anything was
merged.

Change in coreboot[master]: drivers/intel/gma: Add `new-pch.asl` for Skylake+

[Benjamin Doron (Code Review)]

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31503 )

Change subject: drivers/intel/gma: Add `new-pch.asl` for Skylake+
......................................................................

Patch Set 1:
> b) The TRAP only makes sense if there is an SMI handler to handle it. Maybe we
> should identify the platforms that do that and disable the call on the others.

It's smitraphandler.c and smihandler.c, I presume?

"IOTRAP(1) currently unused" (https://github.com/coreboot/coreboot/blob/master/src/soc/intel/common/block/...).

I looked through the tree and it definitely seems as though this line has only been inherited from prior southbridges and SoCs, but it isn't used anywhere.

Change in coreboot[master]: drivers/intel/gma: Add `new-pch.asl` for Skylake+

[Benjamin Doron (Code Review)]

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31503 )

Change subject: drivers/intel/gma: Add `new-pch.asl` for Skylake+
......................................................................

Patch Set 1: Code-Review+1

Changing brightness is a little buggy (no visual feedback of icons and meter and there's a disconnect between brightness controlled by keys (calling GMA) and a Linux-controlled knob) but it works.

Creating a follow-up to link it up.

Change in coreboot[master]: drivers/intel/gma: Add `new-pch.asl` for Skylake+

[Matt DeVillier (Code Review)]

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31503 )

Change subject: drivers/intel/gma: Add `new-pch.asl` for Skylake+
......................................................................

Patch Set 1:
> Patch Set 1: Code-Review+1
>
> Changing brightness is a little buggy (no visual feedback of icons and meter and there's a disconnect between brightness controlled by keys (calling GMA) and a Linux-controlled knob) but it works.
>
> Creating a follow-up to link it up.

what OS / payload did you test?  Last I check this doesn't work for Windows w/Tianocore, but the other Skylake brightness control patch does

Change in coreboot[master]: drivers/intel/gma: Add `new-pch.asl` for Skylake+

[Benjamin Doron (Code Review)]

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31503 )

Change subject: drivers/intel/gma: Add `new-pch.asl` for Skylake+
......................................................................

Patch Set 1:
> what OS / payload did you test?

TianoCore CorebootPayload booting Fedora 31.
> Last I check this doesn't work for Windows w/Tianocore, but the other Skylake brightness control patch does

Interesting. This patch results in more shared code, but whatever works, I suppose. Do we know what Windows expects in the ACPI table?

Change in coreboot[master]: drivers/intel/gma: Add `new-pch.asl` for Skylake+

[Matt DeVillier (Code Review)]

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31503 )

Change subject: drivers/intel/gma: Add `new-pch.asl` for Skylake+
......................................................................

Patch Set 1:
> Patch Set 1:
> > what OS / payload did you test?
>
> TianoCore CorebootPayload booting Fedora 31.
> > Last I check this doesn't work for Windows w/Tianocore, but the other Skylake brightness control patch does
>
> Interesting. This patch results in more shared code, but whatever works, I suppose. Do we know what Windows expects in the ACPI table?

I should have been more clear: the current GMA ACPI brightness control don't work for any platform for the Tianocore/Windows pairing. I have an ugly patch in my tree to force Windows to fall back on the vendor driver backlight control (vs ACPI) for pre-SKL platforms. IMO, the whole GMA ACPI setup needs reworking and then we can hook up SKL and newer platforms

Change in coreboot[master]: drivers/intel/gma/acpi: Add `new-pch.asl` for Skylake+

[Nico Huber (Code Review)]

Hello build bot (Jenkins), Matt DeVillier, Benjamin Doron, Thomas Heijligen, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/31503

to look at the new patch set (#2).

Change subject: drivers/intel/gma/acpi: Add `new-pch.asl` for Skylake+
......................................................................

drivers/intel/gma/acpi: Add `new-pch.asl` for Skylake+

This should work as `pch.asl` equivalent for Skylake and later
platforms.

Untested.

Change-Id: I0b21d9a0288f0f8d6cb0a4776909bffdae7576f5
Signed-off-by: Nico Huber 
---
A src/drivers/intel/gma/acpi/new-pch.asl
1 file changed, 29 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/31503/2

Change in coreboot[master]: drivers/intel/gma/acpi: Add `new-pch.asl` for Skylake+

[Benjamin Doron (Code Review)]

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31503 )

Change subject: drivers/intel/gma/acpi: Add `new-pch.asl` for Skylake+
......................................................................

Patch Set 3: Code-Review+1

Change in coreboot[master]: drivers/intel/gma/acpi: Add `new-pch.asl` for Skylake+

[Benjamin Doron (Code Review)]

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31503 )

Change subject: drivers/intel/gma/acpi: Add `new-pch.asl` for Skylake+
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/31503/1/src/drivers/intel/gma/acpi/... 
File src/drivers/intel/gma/acpi/new-pch.asl:

PS1:
> The former probably. I've seen earlier patches too,not sure if anything was […]

Does this apply to all of: Apollolake, Cannonlake, Icelake, Skylake and Tigerlake?

Change in coreboot[master]: drivers/intel/gma/acpi: Add `new-pch.asl` for Skylake+

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31503 )

Change subject: drivers/intel/gma/acpi: Add `new-pch.asl` for Skylake+
......................................................................

Patch Set 3:

(1 comment)

https://review.coreboot.org/c/coreboot/+/31503/1/src/drivers/intel/gma/acpi/... 
File src/drivers/intel/gma/acpi/new-pch.asl:

PS1:
> Does this apply to all of: Apollolake, Cannonlake, Icelake, Skylake and Tigerlake?

No, alas not. CFL/WHL/CML should be the same, but APL is definitely
different. It also depends on the board. There is a second set of
controls (from SKL on IIRC) at 0x48254, but I've never seen it used.
It seems this second set is the only one from ICL on, probably the
same for (undocumented) CNL.

So, um, big mess, and in the case of chips with multiple controls,
it might even depend on the board. In the long run, we should probably
replace this with runtime generated code, some function that takes
the position and width of BCLV/BCLM as arguments. Hmmm, or we just
put that into Kconfig? Actually I like the idea, this way even board
code could override.

Change in coreboot[master]: drivers/intel/gma/acpi: Add Kconfigs for backlight registers

[Nico Huber (Code Review)]

Hello build bot (Jenkins), Benjamin Doron, Matt DeVillier, Thomas Heijligen, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/31503

to look at the new patch set (#4).

Change subject: drivers/intel/gma/acpi: Add Kconfigs for backlight registers
......................................................................

drivers/intel/gma/acpi: Add Kconfigs for backlight registers

Instead of adding more versions of the `*pch.asl`, unify the existing
ones and allow to override the register locations via Kconfig. The
current defaults should work for Skylake and some newer platforms.

Change-Id: I0b21d9a0288f0f8d6cb0a4776909bffdae7576f5
Signed-off-by: Nico Huber 
---
M src/drivers/intel/gma/Kconfig
R src/drivers/intel/gma/acpi/gma.asl
D src/drivers/intel/gma/acpi/pch.asl
M src/northbridge/intel/gm45/Kconfig
M src/northbridge/intel/gm45/acpi/gm45.asl
M src/northbridge/intel/haswell/Kconfig
M src/northbridge/intel/haswell/acpi/haswell.asl
M src/northbridge/intel/ironlake/Kconfig
M src/northbridge/intel/ironlake/acpi/ironlake.asl
M src/northbridge/intel/sandybridge/Kconfig
M src/northbridge/intel/sandybridge/acpi/sandybridge.asl
M src/northbridge/intel/x4x/acpi/x4x.asl
12 files changed, 40 insertions(+), 38 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/31503/4

Change in coreboot[master]: drivers/intel/gma/acpi: Add Kconfigs for backlight registers

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31503 )

Change subject: drivers/intel/gma/acpi: Add Kconfigs for backlight registers
......................................................................

Patch Set 4: Code-Review+1

Change in coreboot[master]: drivers/intel/gma/acpi: Add Kconfigs for backlight registers

[Nico Huber (Code Review)]

Hello build bot (Jenkins), Damien Zammit, Benjamin Doron, Matt DeVillier, Thomas Heijligen, Angel Pons, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/31503

to look at the new patch set (#5).

Change subject: drivers/intel/gma/acpi: Add Kconfigs for backlight registers
......................................................................

drivers/intel/gma/acpi: Add Kconfigs for backlight registers

Instead of adding more versions of the `*pch.asl`, unify the existing
ones and allow to override the register locations via Kconfig. The
current defaults should work for Skylake and some newer platforms.

TEST=Booted ThinkPad X201s, backlight control still works.

Change-Id: I0b21d9a0288f0f8d6cb0a4776909bffdae7576f5
Signed-off-by: Nico Huber 
---
M src/drivers/intel/gma/Kconfig
R src/drivers/intel/gma/acpi/gma.asl
D src/drivers/intel/gma/acpi/pch.asl
M src/northbridge/intel/gm45/Kconfig
M src/northbridge/intel/gm45/acpi/gm45.asl
M src/northbridge/intel/haswell/Kconfig
M src/northbridge/intel/haswell/acpi/haswell.asl
M src/northbridge/intel/ironlake/Kconfig
M src/northbridge/intel/ironlake/acpi/ironlake.asl
M src/northbridge/intel/sandybridge/Kconfig
M src/northbridge/intel/sandybridge/acpi/sandybridge.asl
M src/northbridge/intel/x4x/acpi/x4x.asl
12 files changed, 40 insertions(+), 38 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/31503/5

Change in coreboot[master]: drivers/intel/gma/acpi: Add Kconfigs for backlight registers

[Benjamin Doron (Code Review)]

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31503 )

Change subject: drivers/intel/gma/acpi: Add Kconfigs for backlight registers
......................................................................

Patch Set 5: Code-Review+1

Change in coreboot[master]: drivers/intel/gma/acpi: Add Kconfigs for backlight registers

[Benjamin Doron (Code Review)]

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31503 )

Change subject: drivers/intel/gma/acpi: Add Kconfigs for backlight registers
......................................................................

Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/31503/1/src/drivers/intel/gma/acpi/... 
File src/drivers/intel/gma/acpi/new-pch.asl:

PS1:
> No, alas not. CFL/WHL/CML should be the same, but APL is definitely […]

Done

Change in coreboot[master]: drivers/intel/gma/acpi: Add Kconfigs for backlight registers

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31503 )

Change subject: drivers/intel/gma/acpi: Add Kconfigs for backlight registers
......................................................................

Patch Set 7: Code-Review+2

Change in coreboot[master]: drivers/intel/gma/acpi: Add Kconfigs for backlight registers

[Wim Vervoorn (Code Review)]

Wim Vervoorn has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31503 )

Change subject: drivers/intel/gma/acpi: Add Kconfigs for backlight registers
......................................................................

Patch Set 7: Code-Review+1

Change in coreboot[master]: drivers/intel/gma/acpi: Add Kconfigs for backlight registers

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/31503 )

Change subject: drivers/intel/gma/acpi: Add Kconfigs for backlight registers
......................................................................

drivers/intel/gma/acpi: Add Kconfigs for backlight registers

Instead of adding more versions of the `*pch.asl`, unify the existing
ones and allow to override the register locations via Kconfig. The
current defaults should work for Skylake and some newer platforms.

TEST=Booted ThinkPad X201s, backlight control still works.

Change-Id: I0b21d9a0288f0f8d6cb0a4776909bffdae7576f5
Signed-off-by: Nico Huber 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31503
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
Reviewed-by: Wim Vervoorn 
Reviewed-by: Benjamin Doron 
---
M src/drivers/intel/gma/Kconfig
R src/drivers/intel/gma/acpi/gma.asl
D src/drivers/intel/gma/acpi/pch.asl
M src/northbridge/intel/gm45/Kconfig
M src/northbridge/intel/gm45/acpi/gm45.asl
M src/northbridge/intel/haswell/Kconfig
M src/northbridge/intel/haswell/acpi/haswell.asl
M src/northbridge/intel/ironlake/Kconfig
M src/northbridge/intel/ironlake/acpi/ironlake.asl
M src/northbridge/intel/sandybridge/Kconfig
M src/northbridge/intel/sandybridge/acpi/sandybridge.asl
M src/northbridge/intel/x4x/acpi/x4x.asl
12 files changed, 40 insertions(+), 38 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Wim Vervoorn: Looks good to me, but someone else must approve
  Angel Pons: Looks good to me, approved
  Benjamin Doron: Looks good to me, but someone else must approve

diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig
index 68d4edc..acc25fe 100644
--- a/src/drivers/intel/gma/Kconfig
+++ b/src/drivers/intel/gma/Kconfig
@@ -29,6 +29,22 @@
    bool
    default n

+config INTEL_GMA_BCLV_OFFSET
+	hex
+	default 0xc8254
+
+config INTEL_GMA_BCLV_WIDTH
+	int
+	default 16
+
+config INTEL_GMA_BCLM_OFFSET
+	hex
+	default 0xc8256
+
+config INTEL_GMA_BCLM_WIDTH
+	int
+	default 16
+
 config INTEL_GMA_SSC_ALTERNATE_REF
    bool
    default n
diff --git a/src/drivers/intel/gma/acpi/non-pch.asl b/src/drivers/intel/gma/acpi/gma.asl
similarity index 76%
rename from src/drivers/intel/gma/acpi/non-pch.asl
rename to src/drivers/intel/gma/acpi/gma.asl
index b656d48..57563933 100644
--- a/src/drivers/intel/gma/acpi/non-pch.asl
+++ b/src/drivers/intel/gma/acpi/gma.asl
@@ -19,9 +19,10 @@
    OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000)
    Field (GFRG, DWordAcc, NoLock, Preserve)
    {
-		Offset (0x61254),
-		BCLV, 16,
-		BCLM, 16,
+		Offset (CONFIG_INTEL_GMA_BCLV_OFFSET),
+		BCLV, CONFIG_INTEL_GMA_BCLV_WIDTH,
+		Offset (CONFIG_INTEL_GMA_BCLM_OFFSET),
+		BCLM, CONFIG_INTEL_GMA_BCLM_WIDTH
    }

#include "configure_brightness_levels.asl"
diff --git a/src/drivers/intel/gma/acpi/pch.asl b/src/drivers/intel/gma/acpi/pch.asl
deleted file mode 100644
index 942ccf4..0000000
--- a/src/drivers/intel/gma/acpi/pch.asl
+++ /dev/null
@@ -1,30 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/* This file is part of the coreboot project. */
-
-Device (GFX0)
-{
-	Name (_ADR, 0x00020000)
-
-	OperationRegion (GFXC, PCI_Config, 0x00, 0x0100)
-	Field (GFXC, DWordAcc, NoLock, Preserve)
-	{
-		Offset (0x10),
-		BAR0, 64,
-		Offset (0xe4),
-		ASLE, 32,
-		Offset (0xfc),
-		ASLS, 32,
-	}
-
-	OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000)
-	Field (GFRG, DWordAcc, NoLock, Preserve)
-	{
-		Offset (0x48254),
-		BCLV, 16,
-		Offset (0xc8256),
-		BCLM, 16
-	}
-
-#include "configure_brightness_levels.asl"
-#include "common.asl"
-}
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
index 752af43..8857bd4 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -46,4 +46,10 @@
    hex
    default 0x100000

+config INTEL_GMA_BCLV_OFFSET
+	default 0x61254
+
+config INTEL_GMA_BCLM_OFFSET
+	default 0x61256
+
 endif
diff --git a/src/northbridge/intel/gm45/acpi/gm45.asl b/src/northbridge/intel/gm45/acpi/gm45.asl
index 3a7e464..8a30212 100644
--- a/src/northbridge/intel/gm45/acpi/gm45.asl
+++ b/src/northbridge/intel/gm45/acpi/gm45.asl
@@ -75,4 +75,4 @@
 #include "peg.asl"

// Integrated graphics 0:2.0
-#include <drivers/intel/gma/acpi/non-pch.asl>
+#include <drivers/intel/gma/acpi/gma.asl>
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index 5e631cf..06ce371 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -107,4 +107,7 @@
    depends on VBOOT
    default "mrc.bin"

+config INTEL_GMA_BCLV_OFFSET
+	default 0x48254
+
 endif
diff --git a/src/northbridge/intel/haswell/acpi/haswell.asl b/src/northbridge/intel/haswell/acpi/haswell.asl
index c0de853..900c6c3 100644
--- a/src/northbridge/intel/haswell/acpi/haswell.asl
+++ b/src/northbridge/intel/haswell/acpi/haswell.asl
@@ -48,4 +48,4 @@
 }

// Integrated graphics 0:2.0
-#include <drivers/intel/gma/acpi/pch.asl>
+#include <drivers/intel/gma/acpi/gma.asl>
diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig
index 638f295..9d93796 100644
--- a/src/northbridge/intel/ironlake/Kconfig
+++ b/src/northbridge/intel/ironlake/Kconfig
@@ -61,4 +61,7 @@
    hex
    default 0xe0000000

+config INTEL_GMA_BCLV_OFFSET
+	default 0x48254
+
 endif
diff --git a/src/northbridge/intel/ironlake/acpi/ironlake.asl b/src/northbridge/intel/ironlake/acpi/ironlake.asl
index 52fec1e..2997dea 100644
--- a/src/northbridge/intel/ironlake/acpi/ironlake.asl
+++ b/src/northbridge/intel/ironlake/acpi/ironlake.asl
@@ -51,4 +51,4 @@
 }

// Integrated graphics 0:2.0
-#include <drivers/intel/gma/acpi/pch.asl>
+#include <drivers/intel/gma/acpi/gma.asl>
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index a9bbf58..29a6db7 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -121,4 +121,7 @@

endif # !USE_NATIVE_RAMINIT

+config INTEL_GMA_BCLV_OFFSET
+	default 0x48254
+
 endif
diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
index 555058c..202671a 100644
--- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
+++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl
@@ -55,4 +55,4 @@
 }

// Integrated graphics 0:2.0
-#include <drivers/intel/gma/acpi/pch.asl>
+#include <drivers/intel/gma/acpi/gma.asl>
diff --git a/src/northbridge/intel/x4x/acpi/x4x.asl b/src/northbridge/intel/x4x/acpi/x4x.asl
index 5f93b3e..09849e3 100644
--- a/src/northbridge/intel/x4x/acpi/x4x.asl
+++ b/src/northbridge/intel/x4x/acpi/x4x.asl
@@ -45,4 +45,4 @@
 #include "peg.asl"

// Integrated graphics 0:2.0
-#include <drivers/intel/gma/acpi/non-pch.asl>
+#include <drivers/intel/gma/acpi/gma.asl>

Change in coreboot[master]: drivers/intel/gma/acpi: Add Kconfigs for backlight registers

[9elements QA (Code Review)]

9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31503 )

Change subject: drivers/intel/gma/acpi: Add Kconfigs for backlight registers
......................................................................

Patch Set 8:

Automatic boot test returned (PASS/FAIL/TOTAL): 5/0/5
Emulation targets:
EMULATION_QEMU_X86_Q35 using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1712
EMULATION_QEMU_X86_Q35 using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1711
EMULATION_QEMU_X86_I440FX using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1710
Non-emulation targets:
HP_COMPAQ_8200_ELITE_SFF_PC using payload TianoCore : SUCCESS : https://lava.9esec.io/r/1714
HP_COMPAQ_8200_ELITE_SFF_PC using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/1713

Please note: This test is under development and might not be accurate at all!