Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31503
Change subject: drivers/intel/gma: Add `new-pch.asl` for Skylake+ ......................................................................
drivers/intel/gma: Add `new-pch.asl` for Skylake+
This should work as `pch.asl` equivalent for Skylake and later platforms.
Untested.
Change-Id: I0b21d9a0288f0f8d6cb0a4776909bffdae7576f5 Signed-off-by: Nico Huber nico.huber@secunet.com --- A src/drivers/intel/gma/acpi/new-pch.asl 1 file changed, 42 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/31503/1
diff --git a/src/drivers/intel/gma/acpi/new-pch.asl b/src/drivers/intel/gma/acpi/new-pch.asl new file mode 100644 index 0000000..b24a350 --- /dev/null +++ b/src/drivers/intel/gma/acpi/new-pch.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (GFX0) +{ + Name (_ADR, 0x00020000) + + OperationRegion (GFXC, PCI_Config, 0x00, 0x0100) + Field (GFXC, DWordAcc, NoLock, Preserve) + { + Offset (0x10), + BAR0, 64, + Offset (0xe4), + ASLE, 32, + Offset (0xfc), + ASLS, 32, + } + + OperationRegion (GFRG, SystemMemory, And (BAR0, 0xfffffffffffffff0), 0x400000) + Field (GFRG, DWordAcc, NoLock, Preserve) + { + Offset (0xc8254), + BCLV, 16, + BCLM, 16 + } + +#include "configure_brightness_levels.asl" +#include "common.asl" +}