1 comment:
File src/drivers/intel/gma/acpi/new-pch.asl:
Does this apply to all of: Apollolake, Cannonlake, Icelake, Skylake and Tigerlake?
No, alas not. CFL/WHL/CML should be the same, but APL is definitely
different. It also depends on the board. There is a second set of
controls (from SKL on IIRC) at 0x48254, but I've never seen it used.
It seems this second set is the only one from ICL on, probably the
same for (undocumented) CNL.
So, um, big mess, and in the case of chips with multiple controls,
it might even depend on the board. In the long run, we should probably
replace this with runtime generated code, some function that takes
the position and width of BCLV/BCLM as arguments. Hmmm, or we just
put that into Kconfig? Actually I like the idea, this way even board
code could override.
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