coreboot-gerrit March 2022

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Change in coreboot[master]: [UNTESTED] soc/amd/common/block/lpc/lpc: rework resource index handling
by Felix Held (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Fred Reitberger. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62579 ) Change subject: [UNTESTED] soc/amd/common/block/lpc/lpc: rework resource index handling ...................................................................... [UNTESTED] soc/amd/common/block/lpc/lpc: rework resource index handling Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I38b2845c982e01f263e70e9639dc2d8a3a7f6925 --- M src/soc/amd/common/block/lpc/lpc.c 1 file changed, 13 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/62579/1 diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 106ae1e..3cfe6f6 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -85,31 +85,36 @@ setup_serirq(); } +/* pci_dev_read_resources might add up to 7 resources (6 BARs and ROM BAR) */ +#define LPC_FIRST_NONSTANDARD_RESOURCE_IDX 7 + static void lpc_read_resources(struct device *dev) { + unsigned int idx; struct resource *res; /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); + /* Add a memory resource for the SPI BAR with LPC_FIRST_NONSTANDARD_RESOURCE_IDX as + resource index so we can easily find it again in lpc_set_resources below. */ + idx = LPC_FIRST_NONSTANDARD_RESOURCE_IDX; + fixed_mem_resource(dev, idx++, SPI_BASE_ADDRESS / KiB, 1, IORESOURCE_SUBTRACTIVE); + /* Add an extra subtractive resource for both memory and I/O. */ - res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res = new_resource(dev, idx++); res->base = 0; res->size = 0x1000; res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res = new_resource(dev, idx++); res->base = FLASH_BASE_ADDR; res->size = CONFIG_ROM_SIZE; res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; - /* Add a memory resource for the SPI BAR. */ - fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / KiB, 1, - IORESOURCE_SUBTRACTIVE); - - res = new_resource(dev, 3); /* IOAPIC */ + res = new_resource(dev, idx++); /* IOAPIC */ res->base = IO_APIC_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; @@ -123,7 +128,7 @@ u32 spi_enable_bits; /* Special case. The SpiRomEnable and other enables should STAY set. */ - res = find_resource(dev, 2); + res = find_resource(dev, LPC_FIRST_NONSTANDARD_RESOURCE_IDX); spi_enable_bits = pci_read_config32(dev, SPI_BASE_ADDRESS_REGISTER); spi_enable_bits &= SPI_BASE_ALIGNMENT - 1; pci_write_config32(dev, SPI_BASE_ADDRESS_REGISTER, -- To view, visit https://review.coreboot.org/c/coreboot/+/62579 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38b2845c982e01f263e70e9639dc2d8a3a7f6925 Gerrit-Change-Number: 62579 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/*/lpc: rename SPIROM_BASE_ADDRESS_REGISTER
by Felix Held (Code Review) 03 Mar '22

03 Mar '22

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62578 ) Change subject: soc/amd/*/lpc: rename SPIROM_BASE_ADDRESS_REGISTER ...................................................................... soc/amd/*/lpc: rename SPIROM_BASE_ADDRESS_REGISTER Rename SPIROM_BASE_ADDRESS_REGISTER to SPI_BASE_ADDRESS_REGISTER to clarify that this isn't the address the SPI flash gets mapped, but the address of the SPI controller MMIO region. This also aligns the register name with the PPR. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ifd9f98bd01b1c7197b80d642a45657c97f708bcd --- M src/soc/amd/cezanne/include/soc/lpc.h M src/soc/amd/common/block/lpc/lpc.c M src/soc/amd/common/block/lpc/lpc_util.c M src/soc/amd/picasso/include/soc/lpc.h M src/soc/amd/sabrina/include/soc/lpc.h M src/soc/amd/stoneyridge/include/soc/lpc.h 6 files changed, 15 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/62578/1 diff --git a/src/soc/amd/cezanne/include/soc/lpc.h b/src/soc/amd/cezanne/include/soc/lpc.h index 123a13f..084159e 100644 --- a/src/soc/amd/cezanne/include/soc/lpc.h +++ b/src/soc/amd/cezanne/include/soc/lpc.h @@ -9,7 +9,7 @@ #define LPC_LDRQ0_PU_EN BIT(10) #define LPC_LDRQ0_PD_EN BIT(9) -#define SPIROM_BASE_ADDRESS_REGISTER 0xa0 +#define SPI_BASE_ADDRESS_REGISTER 0xa0 #define SPI_BASE_ALIGNMENT BIT(8) #define SPI_BASE_RESERVED (BIT(5) | BIT(6) | BIT(7)) #define PSP_SPI_MMIO_SEL BIT(4) diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index ebded6b..106ae1e 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -124,9 +124,9 @@ /* Special case. The SpiRomEnable and other enables should STAY set. */ res = find_resource(dev, 2); - spi_enable_bits = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER); + spi_enable_bits = pci_read_config32(dev, SPI_BASE_ADDRESS_REGISTER); spi_enable_bits &= SPI_BASE_ALIGNMENT - 1; - pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, + pci_write_config32(dev, SPI_BASE_ADDRESS_REGISTER, res->base | spi_enable_bits); pci_dev_set_resources(dev); diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c index 7291959..53bd090 100644 --- a/src/soc/amd/common/block/lpc/lpc_util.c +++ b/src/soc/amd/common/block/lpc/lpc_util.c @@ -187,13 +187,13 @@ u32 base, enables; /* Make sure the base address is predictable */ - base = pci_read_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER); + base = pci_read_config32(_LPCB_DEV, SPI_BASE_ADDRESS_REGISTER); enables = base & SPI_PRESERVE_BITS; base &= ~(SPI_PRESERVE_BITS | SPI_BASE_RESERVED); if (!base) { base = SPI_BASE_ADDRESS; - pci_write_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER, + pci_write_config32(_LPCB_DEV, SPI_BASE_ADDRESS_REGISTER, base | enables | SPI_ROM_ENABLE); /* PCI_COMMAND_MEMORY is read-only and enabled. */ } @@ -233,8 +233,8 @@ /* Route TPM accesses to SPI */ u32 spibase = pci_read_config32(_LPCB_DEV, - SPIROM_BASE_ADDRESS_REGISTER); - pci_write_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER, spibase + SPI_BASE_ADDRESS_REGISTER); + pci_write_config32(_LPCB_DEV, SPI_BASE_ADDRESS_REGISTER, spibase | ROUTE_TPM_2_SPI); } @@ -310,7 +310,7 @@ { u32 base; - base = pci_read_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER); + base = pci_read_config32(_LPCB_DEV, SPI_BASE_ADDRESS_REGISTER); base = ALIGN_DOWN(base, SPI_BASE_ALIGNMENT); return (uintptr_t)base; } @@ -319,12 +319,12 @@ { uint32_t reg32; - reg32 = pci_read_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER); + reg32 = pci_read_config32(_LPCB_DEV, SPI_BASE_ADDRESS_REGISTER); reg32 &= SPI_BASE_ALIGNMENT - 1; /* preserve only reserved, enables */ reg32 |= ALIGN_DOWN(base, SPI_BASE_ALIGNMENT); - pci_write_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER, reg32); + pci_write_config32(_LPCB_DEV, SPI_BASE_ADDRESS_REGISTER, reg32); } void lpc_enable_spi_rom(uint32_t enable) @@ -334,12 +334,12 @@ /* only two types of CS# enables are allowed */ enable &= SPI_ROM_ENABLE | SPI_ROM_ALT_ENABLE; - reg32 = pci_read_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER); + reg32 = pci_read_config32(_LPCB_DEV, SPI_BASE_ADDRESS_REGISTER); reg32 &= ~(SPI_ROM_ENABLE | SPI_ROM_ALT_ENABLE); reg32 |= enable; - pci_write_config32(_LPCB_DEV, SPIROM_BASE_ADDRESS_REGISTER, reg32); + pci_write_config32(_LPCB_DEV, SPI_BASE_ADDRESS_REGISTER, reg32); } static void lpc_enable_controller(void) diff --git a/src/soc/amd/picasso/include/soc/lpc.h b/src/soc/amd/picasso/include/soc/lpc.h index 2705f2d..24d12b3 100644 --- a/src/soc/amd/picasso/include/soc/lpc.h +++ b/src/soc/amd/picasso/include/soc/lpc.h @@ -3,7 +3,7 @@ #ifndef AMD_PICASSO_LPC_H #define AMD_PICASSO_LPC_H -#define SPIROM_BASE_ADDRESS_REGISTER 0xa0 +#define SPI_BASE_ADDRESS_REGISTER 0xa0 #define SPI_BASE_ALIGNMENT BIT(8) #define SPI_BASE_RESERVED (BIT(5) | BIT(6) | BIT(7)) #define PSP_SPI_MMIO_SEL BIT(4) diff --git a/src/soc/amd/sabrina/include/soc/lpc.h b/src/soc/amd/sabrina/include/soc/lpc.h index d5e5712..f0a9257 100644 --- a/src/soc/amd/sabrina/include/soc/lpc.h +++ b/src/soc/amd/sabrina/include/soc/lpc.h @@ -11,7 +11,7 @@ #define LPC_LDRQ0_PU_EN BIT(10) #define LPC_LDRQ0_PD_EN BIT(9) -#define SPIROM_BASE_ADDRESS_REGISTER 0xa0 +#define SPI_BASE_ADDRESS_REGISTER 0xa0 #define SPI_BASE_ALIGNMENT BIT(8) #define SPI_BASE_RESERVED (BIT(5) | BIT(6) | BIT(7)) #define PSP_SPI_MMIO_SEL BIT(4) diff --git a/src/soc/amd/stoneyridge/include/soc/lpc.h b/src/soc/amd/stoneyridge/include/soc/lpc.h index 55e39cc..7d0ffd4 100644 --- a/src/soc/amd/stoneyridge/include/soc/lpc.h +++ b/src/soc/amd/stoneyridge/include/soc/lpc.h @@ -3,7 +3,7 @@ #ifndef AMD_STONEYRIDGE_LPC_H #define AMD_STONEYRIDGE_LPC_H -#define SPIROM_BASE_ADDRESS_REGISTER 0xa0 +#define SPI_BASE_ADDRESS_REGISTER 0xa0 #define SPI_BASE_ALIGNMENT BIT(6) #define SPI_BASE_RESERVED (BIT(4) | BIT(5)) #define ROUTE_TPM_2_SPI BIT(3) -- To view, visit https://review.coreboot.org/c/coreboot/+/62578 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifd9f98bd01b1c7197b80d642a45657c97f708bcd Gerrit-Change-Number: 62578 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: cbfstool/linux_trampoline: Fill the ACPI RSDP entry
by Arthur Heymans (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: Arthur Heymans, Nico Huber, ron minnich. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62574 ) Change subject: cbfstool/linux_trampoline: Fill the ACPI RSDP entry ...................................................................... Patch Set 4: (1 comment) File util/cbfstool/linux_trampoline.S: https://review.coreboot.org/c/coreboot/+/62574/comment/6922bfd5_895a9682 PS4, Line 100: je .endScan > Why not a simple `jmp`? We know it's right on this path, isn't it? > (and I don't know if `mov` can have an effect on flags ._.) eh copy-pasta. thx -- To view, visit https://review.coreboot.org/c/coreboot/+/62574 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I688b94608b03b0177c42d2834c7e3beb802ae686 Gerrit-Change-Number: 62574 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Mar 2022 22:51:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: coreboot_tables.c: Expose the ACPI RSDP
by Nico Huber (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: Arthur Heymans, Lance Zhao, Tim Wawrzynczak. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62573 ) Change subject: coreboot_tables.c: Expose the ACPI RSDP ...................................................................... Patch Set 2: (1 comment) File src/lib/coreboot_table.c: https://review.coreboot.org/c/coreboot/+/62573/comment/2f92893c_28831e23 PS1, Line 537: lb_add_acpi_rsdp(head); > Done Sorry, I said "something like" because I was too lazy to look it up. It's HAVE_ACPI_TABLES. -- To view, visit https://review.coreboot.org/c/coreboot/+/62573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I591312a2c48f0cbbb03b2787e4b365e9c932afff Gerrit-Change-Number: 62573 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 03 Mar 2022 22:46:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/*/northbridge,root_complex: add comment about PCI BARs
by Felix Held (Code Review) 03 Mar '22

03 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62547 ) Change subject: soc/amd/*/northbridge,root_complex: add comment about PCI BARs ...................................................................... soc/amd/*/northbridge,root_complex: add comment about PCI BARs Add a comment to point out that the read_resources functions aren't missing a pci_dev_read_resources call that would add the resources for the BARs of the PC device. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ie480832e0d7954135d2171dda986e477ef7b6c09 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62547 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/cezanne/root_complex.c M src/soc/amd/picasso/root_complex.c M src/soc/amd/sabrina/root_complex.c M src/soc/amd/stoneyridge/northbridge.c 4 files changed, 12 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index dabfa78..9cb668e 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -114,6 +114,9 @@ early_reserved_dram_start = e->base; early_reserved_dram_end = e->base + e->size; + /* The root complex has no PCI BARs implemented, so there's no need to call + pci_dev_read_resources for it */ + /* 0x0 - 0x9ffff */ ram_resource(dev, idx++, 0, 0xa0000 / KiB); diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index a3a3d4b..d5fd10d 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -114,6 +114,9 @@ early_reserved_dram_start = e->base; early_reserved_dram_end = e->base + e->size; + /* The root complex has no PCI BARs implemented, so there's no need to call + pci_dev_read_resources for it */ + /* 0x0 - 0x9ffff */ ram_resource(dev, idx++, 0, 0xa0000 / KiB); diff --git a/src/soc/amd/sabrina/root_complex.c b/src/soc/amd/sabrina/root_complex.c index 2a3ed6f..ae1b3b9 100644 --- a/src/soc/amd/sabrina/root_complex.c +++ b/src/soc/amd/sabrina/root_complex.c @@ -116,6 +116,9 @@ early_reserved_dram_start = e->base; early_reserved_dram_end = e->base + e->size; + /* The root complex has no PCI BARs implemented, so there's no need to call + pci_dev_read_resources for it */ + /* 0x0 - 0x9ffff */ ram_resource(dev, idx++, 0, 0xa0000 / KiB); diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 0384e00..85ef19e 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -60,6 +60,9 @@ unsigned int idx = 0; struct resource *res; + /* The northbridge has no PCI BARs implemented, so there's no need to call + pci_dev_read_resources for it */ + /* * This MMCONF resource must be reserved in the PCI domain. * It is not honored by the coreboot resource allocator if it is in -- To view, visit https://review.coreboot.org/c/coreboot/+/62547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie480832e0d7954135d2171dda986e477ef7b6c09 Gerrit-Change-Number: 62547 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/*/northbridge,root_complex: simplify GNB IOAPIC resource index
by Felix Held (Code Review) 03 Mar '22

03 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62546 ) Change subject: soc/amd/*/northbridge,root_complex: simplify GNB IOAPIC resource index ...................................................................... soc/amd/*/northbridge,root_complex: simplify GNB IOAPIC resource index In the northbridge's and root complex' read_resources function, the GNB IOAPIC resource used MMIO base address of the GNB IOAPIC as index which might be misleading. Instead use idx++ as a unique index for this resource. TEST=Resource allocator doesn't complain and no related warnings or errors in dmesg. The update_constraints console output changes like expected: Before: PCI: 00:00.0 fec01000 base fec01000 limit fec01fff mem (fixed) After: PCI: 00:00.0 0d base fec01000 limit fec01fff mem (fixed) Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I8061364879d772469882fc060f92676de6f600a9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62546 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/cezanne/root_complex.c M src/soc/amd/picasso/root_complex.c M src/soc/amd/sabrina/root_complex.c M src/soc/amd/stoneyridge/northbridge.c 4 files changed, 4 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index e29b4e0..dabfa78 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -168,7 +168,7 @@ } /* GNB IOAPIC resource */ - gnb_apic = new_resource(dev, GNB_IO_APIC_ADDR); + gnb_apic = new_resource(dev, idx++); gnb_apic->base = GNB_IO_APIC_ADDR; gnb_apic->size = 0x00001000; gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 076588e..a3a3d4b 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -166,7 +166,7 @@ } /* GNB IOAPIC resource */ - gnb_apic = new_resource(dev, GNB_IO_APIC_ADDR); + gnb_apic = new_resource(dev, idx++); gnb_apic->base = GNB_IO_APIC_ADDR; gnb_apic->size = 0x00001000; gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; diff --git a/src/soc/amd/sabrina/root_complex.c b/src/soc/amd/sabrina/root_complex.c index fc49f4f..2a3ed6f 100644 --- a/src/soc/amd/sabrina/root_complex.c +++ b/src/soc/amd/sabrina/root_complex.c @@ -170,7 +170,7 @@ } /* GNB IOAPIC resource */ - gnb_apic = new_resource(dev, GNB_IO_APIC_ADDR); + gnb_apic = new_resource(dev, idx++); gnb_apic->base = GNB_IO_APIC_ADDR; gnb_apic->size = 0x00001000; gnb_apic->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 0a80648..0384e00 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -68,7 +68,7 @@ mmconf_resource(dev, idx++); /* NB IOAPIC2 resource */ - res = new_resource(dev, IO_APIC2_ADDR); /* IOAPIC2 */ + res = new_resource(dev, idx++); /* IOAPIC2 */ res->base = IO_APIC2_ADDR; res->size = 0x00001000; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; -- To view, visit https://review.coreboot.org/c/coreboot/+/62546 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8061364879d772469882fc060f92676de6f600a9 Gerrit-Change-Number: 62546 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/*/northbridge,root_complex: simplify mmconf_resource index
by Felix Held (Code Review) 03 Mar '22

03 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62545 ) Change subject: soc/amd/*/northbridge,root_complex: simplify mmconf_resource index ...................................................................... soc/amd/*/northbridge,root_complex: simplify mmconf_resource index In the northbridge's and root complex' read_resources function, the mmconf resource used the number of the MMIO_CONF_BASE MSR as index which might be misleading. Instead use idx++ as a unique index for this resource. TEST=Resource allocator doesn't complain and no related warnings or errors in dmesg. The update_constraints console output changes like expected: Before: PCI: 00:00.0 c0010058 base f8000000 limit fbffffff mem (fixed) After: PCI: 00:00.0 06 base f8000000 limit fbffffff mem (fixed) Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Id66c6153fad86bed36db7bd2455075f4a0850750 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62545 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/soc/amd/cezanne/root_complex.c M src/soc/amd/picasso/root_complex.c M src/soc/amd/sabrina/root_complex.c M src/soc/amd/stoneyridge/northbridge.c 4 files changed, 5 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index dde59d4..e29b4e0 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -138,7 +138,7 @@ ram_resource(dev, idx++, early_reserved_dram_end / KiB, (mem_usable - early_reserved_dram_end) / KiB); - mmconf_resource(dev, MMIO_CONF_BASE); + mmconf_resource(dev, idx++); if (!hob) { printk(BIOS_ERR, "%s incomplete because no HOB list was found\n", diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 4ea8bc2..076588e 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -136,7 +136,7 @@ ram_resource(dev, idx++, early_reserved_dram_end / KiB, (mem_usable - early_reserved_dram_end) / KiB); - mmconf_resource(dev, MMIO_CONF_BASE); + mmconf_resource(dev, idx++); if (!hob) { printk(BIOS_ERR, "%s incomplete because no HOB list was found\n", diff --git a/src/soc/amd/sabrina/root_complex.c b/src/soc/amd/sabrina/root_complex.c index e73c30e..fc49f4f 100644 --- a/src/soc/amd/sabrina/root_complex.c +++ b/src/soc/amd/sabrina/root_complex.c @@ -140,7 +140,7 @@ ram_resource(dev, idx++, early_reserved_dram_end / KiB, (mem_usable - early_reserved_dram_end) / KiB); - mmconf_resource(dev, MMIO_CONF_BASE); + mmconf_resource(dev, idx++); if (!hob) { printk(BIOS_ERR, "Error: %s incomplete because no HOB list was found\n", diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 04472dc..0a80648 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -57,6 +57,7 @@ static void read_resources(struct device *dev) { + unsigned int idx = 0; struct resource *res; /* @@ -64,7 +65,7 @@ * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - mmconf_resource(dev, MMIO_CONF_BASE); + mmconf_resource(dev, idx++); /* NB IOAPIC2 resource */ res = new_resource(dev, IO_APIC2_ADDR); /* IOAPIC2 */ -- To view, visit https://review.coreboot.org/c/coreboot/+/62545 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id66c6153fad86bed36db7bd2455075f4a0850750 Gerrit-Change-Number: 62545 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: coreboot_tables.c: Expose the ACPI RSDP
by Nico Huber (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: Arthur Heymans, Lance Zhao, Tim Wawrzynczak. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62573 ) Change subject: coreboot_tables.c: Expose the ACPI RSDP ...................................................................... Patch Set 2: (1 comment) File src/commonlib/include/commonlib/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/62573/comment/8a326101_5d6f4b4f PS1, Line 586: uint64_t > > > (in C pointers are aligned, right?) […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I591312a2c48f0cbbb03b2787e4b365e9c932afff Gerrit-Change-Number: 62573 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 03 Mar 2022 22:43:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: coreboot_tables.c: Expose the ACPI RSDP
by Nico Huber (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: Arthur Heymans, Lance Zhao, Tim Wawrzynczak. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62573 ) Change subject: coreboot_tables.c: Expose the ACPI RSDP ...................................................................... Patch Set 2: (1 comment) File src/commonlib/include/commonlib/coreboot_tables.h: https://review.coreboot.org/c/coreboot/+/62573/comment/5fe7c811_6d8c10e9 PS1, Line 586: uint64_t > > (in C pointers are aligned, right?) > > Says who? x86 supports misaligned everything by design! The compilers just keep trying to shave off every possible bit everywhere making every assumption they possibly can.... that is so frustrating... The spec says so, I think, at least indirectly, and the warnings that we disable ^^ ``` Among the invalid values for dereferencing a pointer by the unary * operator are a null pointer, an address inappropriately aligned for the type of object pointed to, and the address of an object after the end of its lifetime. ``` So strictly speaking pointers don't have to be aligned but the objects. IMO, beside the GNU extensions, it's sound and save. If this is really becoming an issue it's our fault. -- To view, visit https://review.coreboot.org/c/coreboot/+/62573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I591312a2c48f0cbbb03b2787e4b365e9c932afff Gerrit-Change-Number: 62573 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 03 Mar 2022 22:42:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: libpayload/bin/lpgcc: Make lpgcc provide TPM configuration for vboot
by Julius Werner (Code Review) 03 Mar '22

03 Mar '22

Julius Werner has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62516 ) Change subject: libpayload/bin/lpgcc: Make lpgcc provide TPM configuration for vboot ...................................................................... libpayload/bin/lpgcc: Make lpgcc provide TPM configuration for vboot TPM1_MODE and TPM2_MODE defines have to be added to vboot and payload cflags to make them build correctly without requiring payloads to provide defines. Signed-off-by: Jakub Czapiga <jacz(a)semihalf.com> Change-Id: I567a9f04d7089699840dc7e0a063cf3030fb934b Reviewed-on: https://review.coreboot.org/c/coreboot/+/62516 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M payloads/libpayload/bin/lpgcc 1 file changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/payloads/libpayload/bin/lpgcc b/payloads/libpayload/bin/lpgcc index 8bc46a6..77ceda3 100755 --- a/payloads/libpayload/bin/lpgcc +++ b/payloads/libpayload/bin/lpgcc @@ -182,6 +182,14 @@ _CFLAGS="$_CFLAGS -include $BASE/../include/kconfig.h -include $BASE/../include/compiler.h" _CFLAGS="$_CFLAGS -I`$DEFAULT_CC $_ARCHEXTRA -print-search-dirs | head -n 1 | cut -d' ' -f2`include" +if [ "$CONFIG_LP_VBOOT_LIB" = y ]; then + if [ "$CONFIG_LP_VBOOT_TPM2_MODE" = y ]; then + _CFLAGS="$_CFLAGS -DTPM2_MODE" + else + _CFLAGS="$_CFLAGS -DTPM1_MODE" + fi +fi + _LDFLAGS="-L$_LIBDIR $_LDSCRIPT -static -Wl,--gc-sections" if [ $DOLINK -eq 0 ]; then -- To view, visit https://review.coreboot.org/c/coreboot/+/62516 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I567a9f04d7089699840dc7e0a063cf3030fb934b Gerrit-Change-Number: 62516 Gerrit-PatchSet: 4 Gerrit-Owner: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Joey Madafferi <joeymadafferi(a)gmail.com> Gerrit-MessageType: merged

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coreboot-gerrit March 2022