Change in coreboot[master]: soc/amd/*/northbridge,root_complex: add comment about PCI BARs

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62547 )

Change subject: soc/amd/*/northbridge,root_complex: add comment about PCI BARs
......................................................................

soc/amd/*/northbridge,root_complex: add comment about PCI BARs

Add a comment to point out that the read_resources functions aren't
missing a pci_dev_read_resources call that would add the resources for
the BARs of the PC device.

Signed-off-by: Felix Held <[e-mail]>
Change-Id: Ie480832e0d7954135d2171dda986e477ef7b6c09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62547
Tested-by: build bot (Jenkins) <[e-mail]>
Reviewed-by: Raul Rangel <[e-mail]>
---
M src/soc/amd/cezanne/root_complex.c
M src/soc/amd/picasso/root_complex.c
M src/soc/amd/sabrina/root_complex.c
M src/soc/amd/stoneyridge/northbridge.c
4 files changed, 12 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Raul Rangel: Looks good to me, approved



diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c
index dabfa78..9cb668e 100644
--- a/src/soc/amd/cezanne/root_complex.c
+++ b/src/soc/amd/cezanne/root_complex.c
@@ -114,6 +114,9 @@
 	early_reserved_dram_start = e->base;
 	early_reserved_dram_end = e->base + e->size;
 
+	/* The root complex has no PCI BARs implemented, so there's no need to call
+	   pci_dev_read_resources for it */
+
 	/* 0x0 - 0x9ffff */
 	ram_resource(dev, idx++, 0, 0xa0000 / KiB);
 
diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c
index a3a3d4b..d5fd10d 100644
--- a/src/soc/amd/picasso/root_complex.c
+++ b/src/soc/amd/picasso/root_complex.c
@@ -114,6 +114,9 @@
 	early_reserved_dram_start = e->base;
 	early_reserved_dram_end = e->base + e->size;
 
+	/* The root complex has no PCI BARs implemented, so there's no need to call
+	   pci_dev_read_resources for it */
+
 	/* 0x0 - 0x9ffff */
 	ram_resource(dev, idx++, 0, 0xa0000 / KiB);
 
diff --git a/src/soc/amd/sabrina/root_complex.c b/src/soc/amd/sabrina/root_complex.c
index 2a3ed6f..ae1b3b9 100644
--- a/src/soc/amd/sabrina/root_complex.c
+++ b/src/soc/amd/sabrina/root_complex.c
@@ -116,6 +116,9 @@
 	early_reserved_dram_start = e->base;
 	early_reserved_dram_end = e->base + e->size;
 
+	/* The root complex has no PCI BARs implemented, so there's no need to call
+	   pci_dev_read_resources for it */
+
 	/* 0x0 - 0x9ffff */
 	ram_resource(dev, idx++, 0, 0xa0000 / KiB);
 
diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c
index 0384e00..85ef19e 100644
--- a/src/soc/amd/stoneyridge/northbridge.c
+++ b/src/soc/amd/stoneyridge/northbridge.c
@@ -60,6 +60,9 @@
 	unsigned int idx = 0;
 	struct resource *res;
 
+	/* The northbridge has no PCI BARs implemented, so there's no need to call
+	   pci_dev_read_resources for it */
+
 	/*
 	 * This MMCONF resource must be reserved in the PCI domain.
 	 * It is not honored by the coreboot resource allocator if it is in

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ie480832e0d7954135d2171dda986e477ef7b6c09
Gerrit-Change-Number: 62547
Gerrit-PatchSet: 2
Gerrit-Owner: Felix Held <[e-mail]>
Gerrit-Reviewer: Felix Held <[e-mail]>
Gerrit-Reviewer: Fred Reitberger <[e-mail]>
Gerrit-Reviewer: Jason Glenesk <[e-mail]>
Gerrit-Reviewer: Marshall Dawson <[e-mail]>
Gerrit-Reviewer: Raul Rangel <[e-mail]>
Gerrit-Reviewer: build bot (Jenkins) <[e-mail]>
Gerrit-MessageType: merged