coreboot-gerrit March 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/mediatek/mt8195: Add driver to configure PCIe
by Jianjun Wang (Code Review) 04 Mar '22

04 Mar '22

Attention is currently required from: Hung-Te Lin, Paul Menzel, Angel Pons, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56792 ) Change subject: soc/mediatek/mt8195: Add driver to configure PCIe ...................................................................... Patch Set 14: (1 comment) File src/soc/mediatek/mt8195/pcie.c: https://review.coreboot.org/c/coreboot/+/56792/comment/24a55305_36ebec0f PS11, Line 26: > Remove extra indentation. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6799c53b03a33be91157ea088d829beb4272976 Gerrit-Change-Number: 56792 Gerrit-PatchSet: 14 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 04 Mar 2022 02:32:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Add PCIe support
by Jianjun Wang (Code Review) 04 Mar '22

04 Mar '22

Attention is currently required from: Hung-Te Lin, Arthur Heymans, Shelley Chen, Nico Huber, Furquan Shaikh, Paul Menzel, Angel Pons, Yu-Ping Wu. Jianjun Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56791 ) Change subject: soc/mediatek: Add PCIe support ...................................................................... Patch Set 13: (4 comments) File src/soc/mediatek/common/include/soc/pcie_common.h: https://review.coreboot.org/c/coreboot/+/56791/comment/3aef196b_364eb74c PS11, Line 19: void (*reset)( uintptr_t base, bool enable); > > space prohibited after that open parenthesis '(' […] Done https://review.coreboot.org/c/coreboot/+/56791/comment/2c2fc3c1_d474ef94 PS11, Line 25: domain > dev […] Done File src/soc/mediatek/common/pcie.c: https://review.coreboot.org/c/coreboot/+/56791/comment/3f20abd6_16911e23 PS11, Line 3: arch > device […] No need, removed https://review.coreboot.org/c/coreboot/+/56791/comment/fc92963a_df3ba5f5 PS11, Line 197: mtk_pcie_domain_set_resources > Maybe put this below mtk_pcie_domain_read_resources() to follow the calling order. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/56791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0 Gerrit-Change-Number: 56791 Gerrit-PatchSet: 13 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 04 Mar 2022 02:31:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek: Add PCIe support
by Jianjun Wang (Code Review) 04 Mar '22

04 Mar '22

Attention is currently required from: Hung-Te Lin, Arthur Heymans, Shelley Chen, Nico Huber, Furquan Shaikh, Paul Menzel, Angel Pons, Jianjun Wang. Hello Shelley Chen, Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56791 to look at the new patch set (#13). Change subject: soc/mediatek: Add PCIe support ...................................................................... soc/mediatek: Add PCIe support Add PCIe support for MediaTek platform. Reference: - MT8195 Register Map V0.3-2, Chapter 3.18 PCIe controller (Page 1250) - linux/drivers/pci/controller/pcie-mediatek-gen3.c This code is based on MT8195 platform, but it should be common in each platform with the same PCIe IP in the future. TEST=Build pass and boot up to kernel successfully via SSD on Cherry board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x1987 PCI SSVID : 0x1987 SN : 28F40713077B0012602 MN : Phison ESE1A043-X28 RAB : 0x1 AERL : 0x3 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model Phison ESE1A043-X28 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0 --- M src/soc/mediatek/common/Kconfig A src/soc/mediatek/common/include/soc/pcie_common.h A src/soc/mediatek/common/pcie.c 3 files changed, 279 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/56791/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/56791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0 Gerrit-Change-Number: 56791 Gerrit-PatchSet: 13 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8195: Enable PCIe support for mt8195
by Jianjun Wang (Code Review) 04 Mar '22

04 Mar '22

Attention is currently required from: Hung-Te Lin, Arthur Heymans, Paul Menzel. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56793 to look at the new patch set (#15). Change subject: soc/mediatek/mt8195: Enable PCIe support for mt8195 ...................................................................... soc/mediatek/mt8195: Enable PCIe support for mt8195 Enable PCIe support for mt8195. TEST=Build pass and boot up to kernel successfully via SSD on Cherry board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x1987 PCI SSVID : 0x1987 SN : 28F40713077B0012602 MN : Phison ESE1A043-X28 RAB : 0x1 AERL : 0x3 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model Phison ESE1A043-X28 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: I314572955f1021abe9f2f0f4635670135ed08fff --- M src/soc/mediatek/mt8195/Kconfig M src/soc/mediatek/mt8195/soc.c 2 files changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/56793/15 -- To view, visit https://review.coreboot.org/c/coreboot/+/56793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I314572955f1021abe9f2f0f4635670135ed08fff Gerrit-Change-Number: 56793 Gerrit-PatchSet: 15 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8195: Add driver to configure PCIe
by Jianjun Wang (Code Review) 04 Mar '22

04 Mar '22

Attention is currently required from: Hung-Te Lin, Paul Menzel, Angel Pons. Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/56792 to look at the new patch set (#14). Change subject: soc/mediatek/mt8195: Add driver to configure PCIe ...................................................................... soc/mediatek/mt8195: Add driver to configure PCIe Add a new function 'mtk_pcie_pre_init' to assert the PCIe reset at early stage to reduce the impact of 100ms delay. TEST=Build pass and boot up to kernel successfully via SSD on Cherry board, here is the SSD information in boot log: == NVME IDENTIFY CONTROLLER DATA == PCI VID : 0x1987 PCI SSVID : 0x1987 SN : 28F40713077B0012602 MN : Phison ESE1A043-X28 RAB : 0x1 AERL : 0x3 SQES : 0x66 CQES : 0x44 NN : 0x1 Identified NVMe model Phison ESE1A043-X28 BUG=b:178565024 Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: If6799c53b03a33be91157ea088d829beb4272976 --- M src/soc/mediatek/mt8195/Makefile.inc A src/soc/mediatek/mt8195/include/soc/pcie.h A src/soc/mediatek/mt8195/pcie.c 3 files changed, 112 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/56792/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/56792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6799c53b03a33be91157ea088d829beb4272976 Gerrit-Change-Number: 56792 Gerrit-PatchSet: 14 Gerrit-Owner: Jianjun Wang <jianjun.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cbfstool/linux_trampoline: Fill the ACPI RSDP entry
by Julius Werner (Code Review) 04 Mar '22

04 Mar '22

Attention is currently required from: Arthur Heymans, ron minnich. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62574 ) Change subject: cbfstool/linux_trampoline: Fill the ACPI RSDP entry ...................................................................... Patch Set 5: (1 comment) File util/cbfstool/linux_trampoline.c: https://review.coreboot.org/c/coreboot/+/62574/comment/5db01126_f983f907 PS4, Line 1: /* This file is automatically generated. Do not manually change */ > > Totally off-topic, but should we automate this a bit better (so that we no longer have to check in […] We could, yeah. Although I think the difference there is that not everyone might have flex/bison installed and we don't want to make it unnecessarily complicated for them. This here just needs the toolchain parts we already have anyway. Also, flex/bison compiled files are ugly but they are still somewhat readable (at least you could tell if there was malware hidden in it or something), a hex array is completely opaque. -- To view, visit https://review.coreboot.org/c/coreboot/+/62574 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I688b94608b03b0177c42d2834c7e3beb802ae686 Gerrit-Change-Number: 62574 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Fri, 04 Mar 2022 02:21:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/var/kinox: update overridetree
by Dtrain Hsu (Code Review) 04 Mar '22

04 Mar '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro, Zhuohao Lee. Hello build bot (Jenkins), Tim Wawrzynczak, Nick Vaccaro, Zhuohao Lee, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62553 to look at the new patch set (#3). Change subject: mb/google/brya/var/kinox: update overridetree ...................................................................... mb/google/brya/var/kinox: update overridetree 1. Update override devicetree based on schematics. 2. ALC5682I-VS is for audio codec. 3. Update 15W SOC default PL2/PL4(39W/100W). 4. Update DPTF table. BUG=b:218786363, b:212183045, b:213417026, b:221180425 TEST=emerge-brya coreboot Signed-off-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Change-Id: I08a1c2f784175b208ccdc562668041f432618dfc --- M src/mainboard/google/brya/variants/kinox/Makefile.inc M src/mainboard/google/brya/variants/kinox/overridetree.cb A src/mainboard/google/brya/variants/kinox/ramstage.c 3 files changed, 409 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/62553/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/62553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08a1c2f784175b208ccdc562668041f432618dfc Gerrit-Change-Number: 62553 Gerrit-PatchSet: 3 Gerrit-Owner: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Zhuohao Lee <zhuohao(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [RFC] Intel IIO split stack - multidomain approach
by Mariusz Szafrański (Code Review) 04 Mar '22

04 Mar '22

Attention is currently required from: Arthur Heymans, Furquan Shaikh, Jonathan Zhang, Paul Menzel, Angel Pons, Aaron Durbin, Lance Zhao, Anjaneya "Reddy" Chagam, David Guckian, Martin Roth, Daocheng Bu, Suresh Bellampalli, Peter Tsung Ho Wu. Mariusz Szafrański has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56263 ) Change subject: [RFC] Intel IIO split stack - multidomain approach ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > > Working code is ready but ... […] Our current PoC evolved also to some kind of mix of dynamic/static due to need to support SoCs variants with different configurations. So basically we start from static multidomain devicetree then it is dynamically updated in early ramstage based on data returned from FSP and standard PCI bus probing. Resource allocation works correctly for below and above 4G with only small tweaks to current resource allocator. -- To view, visit https://review.coreboot.org/c/coreboot/+/56263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38ac830ee05866a09c5661ec48fab96af8135f44 Gerrit-Change-Number: 56263 Gerrit-PatchSet: 1 Gerrit-Owner: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Peter Tsung Ho Wu <tsung(a)amazon.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: David Guckian <david.guckian(a)intel.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Peter Tsung Ho Wu <tsung(a)amazon.com> Gerrit-Comment-Date: Fri, 04 Mar 2022 02:03:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur.heymans(a)9elements.com> Comment-In-Reply-To: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Include Meteorlake device IDs
by Wonkyu Kim (Code Review) 04 Mar '22

04 Mar '22

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62581 ) Change subject: soc/intel/common: Include Meteorlake device IDs ...................................................................... soc/intel/common: Include Meteorlake device IDs Reference: chapter2 in Meteorlake EDS vol1(640228) Signed-off-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Change-Id: Ie71abb70b88db0acec8a320c3e2c20c54bbb4a8a --- M src/drivers/intel/ish/ish.c M src/include/cpu/intel/cpu_ids.h M src/include/device/pci_ids.h M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/dsp/dsp.c M src/soc/intel/common/block/dtt/dtt.c M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/common/block/hda/hda.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/lpc/lpc.c M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/pmc/pmc.c M src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/sram/sram.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/usb4/usb4.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c 23 files changed, 168 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/62581/1 diff --git a/src/drivers/intel/ish/ish.c b/src/drivers/intel/ish/ish.c index 9ab4f2d..0cd8094 100644 --- a/src/drivers/intel/ish/ish.c +++ b/src/drivers/intel/ish/ish.c @@ -51,6 +51,7 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_MTL_ISHB, PCI_DEVICE_ID_INTEL_CNL_ISHB, PCI_DEVICE_ID_INTEL_CML_ISHB, PCI_DEVICE_ID_INTEL_TGL_ISHB, diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h index 0f7c5c1..ce86839 100644 --- a/src/include/cpu/intel/cpu_ids.h +++ b/src/include/cpu/intel/cpu_ids.h @@ -56,5 +56,6 @@ #define CPUID_ALDERLAKE_A2 0x906a2 #define CPUID_ALDERLAKE_A3 0x906a4 #define CPUID_ALDERLAKE_N_A0 0xb06e0 - +#define CPUID_METEORLAKE_1_A0 0xa06a0 +#define CPUID_METEORLAKE_2_A0 0xa06a1 #endif /* CPU_INTEL_CPU_IDS_H */ diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 43dbe5b..fb70ddc 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2180,6 +2180,7 @@ #define PCI_DEVICE_ID_INTEL_CML_ISHB 0x02fc #define PCI_DEVICE_ID_INTEL_TGL_ISHB 0xa0fc #define PCI_DEVICE_ID_INTEL_TGL_H_ISHB 0x43fc +#define PCI_DEVICE_ID_INTEL_MTL_ISHB 0x7e45 /* Intel 82371FB (PIIX) */ #define PCI_DEVICE_ID_INTEL_82371FB_ISA 0x122e @@ -3074,6 +3075,14 @@ #define PCI_DEVICE_ID_INTEL_ADP_M_N_ESPI_31 0x549f #define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_32 0x5186 #define PCI_DEVICE_ID_INTEL_SPR_ESPI_1 0x1b80 +#define PCI_DEVICE_ID_INTEL_MTL_ESPI_0 0x7e00 +#define PCI_DEVICE_ID_INTEL_MTL_ESPI_1 0x7e01 +#define PCI_DEVICE_ID_INTEL_MTL_ESPI_2 0x7e02 +#define PCI_DEVICE_ID_INTEL_MTL_ESPI_3 0x7e03 +#define PCI_DEVICE_ID_INTEL_MTL_ESPI_4 0x7e04 +#define PCI_DEVICE_ID_INTEL_MTL_ESPI_5 0x7e05 +#define PCI_DEVICE_ID_INTEL_MTL_ESPI_6 0x7e06 +#define PCI_DEVICE_ID_INTEL_MTL_ESPI_7 0x7e07 /* Intel PCIE device ids */ #define PCI_DEVICE_ID_INTEL_LPT_H_PCIE_RP1 0x8c10 @@ -3411,6 +3420,19 @@ #define PCI_DEVICE_ID_INTEL_ADP_N_PCIE_RP11 0x54b2 #define PCI_DEVICE_ID_INTEL_ADP_N_PCIE_RP12 0x54b3 +#define PCI_DEVICE_ID_INTEL_MTL_PCIE_RP1 0x7e38 +#define PCI_DEVICE_ID_INTEL_MTL_PCIE_RP2 0x7e39 +#define PCI_DEVICE_ID_INTEL_MTL_PCIE_RP3 0x7e3a +#define PCI_DEVICE_ID_INTEL_MTL_PCIE_RP4 0x7e3b +#define PCI_DEVICE_ID_INTEL_MTL_PCIE_RP5 0x7e3c +#define PCI_DEVICE_ID_INTEL_MTL_PCIE_RP6 0x7e3d +#define PCI_DEVICE_ID_INTEL_MTL_PCIE_RP7 0x7e3e +#define PCI_DEVICE_ID_INTEL_MTL_PCIE_RP8 0x7e3f +#define PCI_DEVICE_ID_INTEL_MTL_PCIE_RP9 0x7e4d +#define PCI_DEVICE_ID_INTEL_MTL_PCIE_RP10 0x7eca +#define PCI_DEVICE_ID_INTEL_MTL_PCIE_RP11 0x7ecb +#define PCI_DEVICE_ID_INTEL_MTL_PCIE_RP12 0x7ecc + /* Intel SATA device Ids */ #define PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_IDE 0x8c00 #define PCI_DEVICE_ID_INTEL_LPT_H_DESKTOP_SATA_AHCI 0x8c02 @@ -3482,6 +3504,9 @@ #define PCI_DEVICE_ID_INTEL_ADP_M_SATA_1 0x54d3 #define PCI_DEVICE_ID_INTEL_ADP_M_SATA_2 0x54d7 #define PCI_DEVICE_ID_INTEL_ADP_M_SATA_3 0x282a +#define PCI_DEVICE_ID_INTEL_MTL_SATA_1 0x7e63 +#define PCI_DEVICE_ID_INTEL_MTL_SATA_2 0x7e67 +#define PCI_DEVICE_ID_INTEL_MTL_SATA_3 0x282a /* Intel PMC device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PMC 0x9d21 @@ -3503,6 +3528,9 @@ #define PCI_DEVICE_ID_INTEL_ADP_P_PMC 0x7a21 #define PCI_DEVICE_ID_INTEL_ADP_S_PMC 0x7aa1 #define PCI_DEVICE_ID_INTEL_ADP_M_N_PMC 0x54a1 +#define PCI_DEVICE_ID_INTEL_MTL_PMC 0x7e21 +#define PCI_DEVICE_ID_INTEL_MTL_M_PMC 0x7ebe +#define PCI_DEVICE_ID_INTEL_MTL_P_PMC 0x7ece /* Intel I2C device Ids */ #define PCI_DEVICE_ID_INTEL_LPT_LP_I2C0 0x9c61 @@ -3613,6 +3641,13 @@ #define PCI_DEVICE_ID_INTEL_ADP_M_N_I2C4 0x54c5 #define PCI_DEVICE_ID_INTEL_ADP_M_N_I2C5 0x54c6 +#define PCI_DEVICE_ID_INTEL_MTL_I2C0 0x7e78 +#define PCI_DEVICE_ID_INTEL_MTL_I2C1 0x7e79 +#define PCI_DEVICE_ID_INTEL_MTL_I2C2 0x7e7a +#define PCI_DEVICE_ID_INTEL_MTL_I2C3 0x7e7b +#define PCI_DEVICE_ID_INTEL_MTL_I2C4 0x7e50 +#define PCI_DEVICE_ID_INTEL_MTL_I2C5 0x7e51 + /* Intel UART device Ids */ #define PCI_DEVICE_ID_INTEL_LPT_LP_UART0 0x9c63 #define PCI_DEVICE_ID_INTEL_LPT_LP_UART1 0x9c64 @@ -3683,6 +3718,10 @@ #define PCI_DEVICE_ID_INTEL_ADP_M_N_UART2 0x54c7 #define PCI_DEVICE_ID_INTEL_ADP_M_N_UART3 0x54da +#define PCI_DEVICE_ID_INTEL_MTL_UART0 0x7e25 +#define PCI_DEVICE_ID_INTEL_MTL_UART1 0x7e26 +#define PCI_DEVICE_ID_INTEL_MTL_UART2 0x7e52 + /* Intel SPI device Ids */ #define PCI_DEVICE_ID_INTEL_LPT_LP_GSPI0 0x9c65 #define PCI_DEVICE_ID_INTEL_LPT_LP_GSPI1 0x9c66 @@ -3765,6 +3804,11 @@ #define PCI_DEVICE_ID_INTEL_SPR_HWSEQ_SPI 0x1bca +#define PCI_DEVICE_ID_INTEL_MTL_SPI0 0x7e23 +#define PCI_DEVICE_ID_INTEL_MTL_GSPI0 0x7e27 +#define PCI_DEVICE_ID_INTEL_MTL_GSPI1 0x7e30 +#define PCI_DEVICE_ID_INTEL_MTL_GSPI2 0x7e46 + /* Intel IGD device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_GT1F_DT2 0x1902 #define PCI_DEVICE_ID_INTEL_SKL_GT1_SULTM 0x1906 @@ -3915,6 +3959,11 @@ #define PCI_DEVICE_ID_INTEL_ADL_N_GT3 0x46D2 +#define PCI_DEVICE_ID_INTEL_SIMICS_GT0 0xffff +#define PCI_DEVICE_ID_INTEL_MTL_M_GT2 0x7d40 +#define PCI_DEVICE_ID_INTEL_MTL_P_GT2_1 0x7d50 +#define PCI_DEVICE_ID_INTEL_MTL_P_GT2_2 0x7d60 + /* Intel Northbridge Ids */ #define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 #define PCI_DEVICE_ID_INTEL_GLK_NB 0x31f0 @@ -4030,6 +4079,9 @@ #define PCI_DEVICE_ID_INTEL_ADL_N_ID_2 0x461B #define PCI_DEVICE_ID_INTEL_ADL_N_ID_3 0x461c #define PCI_DEVICE_ID_INTEL_ADL_N_ID_4 0x4614 +#define PCI_DEVICE_ID_INTEL_MTL_M_ID 0x7D00 +#define PCI_DEVICE_ID_INTEL_MTL_P_ID_1 0x7D01 +#define PCI_DEVICE_ID_INTEL_MTL_P_ID_2 0x7D02 /* Intel SMBUS device Ids */ #define PCI_DEVICE_ID_INTEL_LPT_H_SMBUS 0x8c22 @@ -4052,6 +4104,7 @@ #define PCI_DEVICE_ID_INTEL_ADP_P_SMBUS 0xa0a3 #define PCI_DEVICE_ID_INTEL_ADP_S_SMBUS 0x7aa3 #define PCI_DEVICE_ID_INTEL_ADP_M_N_SMBUS 0x54a3 +#define PCI_DEVICE_ID_INTEL_MTL_SMBUS 0x7e22 /* Intel EHCI device IDs */ #define PCI_DEVICE_ID_INTEL_LPT_H_EHCI_1 0x8c26 @@ -4083,6 +4136,9 @@ #define PCI_DEVICE_ID_INTEL_ADP_S_XHCI 0x7ae0 #define PCI_DEVICE_ID_INTEL_ADP_TCSS_XHCI 0x461e #define PCI_DEVICE_ID_INTEL_ADP_M_XHCI 0x54ed +#define PCI_DEVICE_ID_INTEL_MTL_XHCI 0x7e7d +#define PCI_DEVICE_ID_INTEL_MTL_M_XHCI 0x7eb0 +#define PCI_DEVICE_ID_INTEL_MTL_P_XHCI 0x7ec0 /* Intel P2SB device Ids */ #define PCI_DEVICE_ID_INTEL_APL_P2SB 0x5a92 @@ -4104,6 +4160,9 @@ #define PCI_DEVICE_ID_INTEL_ADP_P_P2SB 0x7a20 #define PCI_DEVICE_ID_INTEL_ADP_S_P2SB 0x7aa0 #define PCI_DEVICE_ID_INTEL_ADP_M_P2SB 0x54a0 +#define PCI_DEVICE_ID_INTEL_MTL_P2SB 0x7e20 +#define PCI_DEVICE_ID_INTEL_MTL_M_P2SB 0x7eb8 +#define PCI_DEVICE_ID_INTEL_MTL_P_P2SB 0x7ec8 /* Intel SRAM device Ids */ #define PCI_DEVICE_ID_INTEL_APL_SRAM 0x5aec @@ -4116,6 +4175,9 @@ #define PCI_DEVICE_ID_INTEL_TGL_H_SRAM 0x43ef #define PCI_DEVICE_ID_INTEL_MCC_SRAM 0x4b7f #define PCI_DEVICE_ID_INTEL_JSP_SRAM 0x4def +#define PCI_DEVICE_ID_INTEL_MTL_SRAM 0x7e7f +#define PCI_DEVICE_ID_INTEL_MTL_M_SRAM 0x7ebf +#define PCI_DEVICE_ID_INTEL_MTL_P_SRAM 0x7ecf /* Intel AUDIO device Ids */ #define PCI_DEVICE_ID_INTEL_LPT_H_AUDIO 0x8c20 @@ -4155,6 +4217,15 @@ #define PCI_DEVICE_ID_INTEL_ADP_M_N_AUDIO_6 0x54cd #define PCI_DEVICE_ID_INTEL_ADP_M_N_AUDIO_7 0x54ce +#define PCI_DEVICE_ID_INTEL_MTL_AUDIO_1 0x7e28 +#define PCI_DEVICE_ID_INTEL_MTL_AUDIO_2 0x7e29 +#define PCI_DEVICE_ID_INTEL_MTL_AUDIO_3 0x7e2a +#define PCI_DEVICE_ID_INTEL_MTL_AUDIO_4 0x7e2b +#define PCI_DEVICE_ID_INTEL_MTL_AUDIO_5 0x7e2c +#define PCI_DEVICE_ID_INTEL_MTL_AUDIO_6 0x7e2d +#define PCI_DEVICE_ID_INTEL_MTL_AUDIO_7 0x7e2e +#define PCI_DEVICE_ID_INTEL_MTL_AUDIO_8 0x7e2f + /* Intel HECI/ME device Ids */ #define PCI_DEVICE_ID_INTEL_LPT_H_MEI 0x8c3a #define PCI_DEVICE_ID_INTEL_LPT_LP_MEI 0x9c3a @@ -4194,6 +4265,10 @@ #define PCI_DEVICE_ID_INTEL_ADP_M_CSE1 0x54e1 #define PCI_DEVICE_ID_INTEL_ADP_M_CSE2 0x54e4 #define PCI_DEVICE_ID_INTEL_ADP_M_CSE3 0x54e5 +#define PCI_DEVICE_ID_INTEL_MTL_CSE0 0x7e70 +#define PCI_DEVICE_ID_INTEL_MTL_CSE1 0x7e71 +#define PCI_DEVICE_ID_INTEL_MTL_CSE2 0x7e74 +#define PCI_DEVICE_ID_INTEL_MTL_CSE3 0x7e75 /* Intel XDCI device Ids */ #define PCI_DEVICE_ID_INTEL_APL_XDCI 0x5aaa @@ -4213,6 +4288,9 @@ #define PCI_DEVICE_ID_INTEL_ADP_S_XDCI 0x7ae1 #define PCI_DEVICE_ID_INTEL_ADP_TCSS_XDCI 0x460e #define PCI_DEVICE_ID_INTEL_ADP_M_XDCI 0x54ee +#define PCI_DEVICE_ID_INTEL_MTL_XDCI 0x7e7e +#define PCI_DEVICE_ID_INTEL_MTL_M_XDCI 0x7eb1 +#define PCI_DEVICE_ID_INTEL_MTL_P_XDCI 0x7ec1 /* Intel SD device Ids */ #define PCI_DEVICE_ID_INTEL_LPT_LP_SD 0x9c35 @@ -4255,6 +4333,9 @@ #define PCI_DEVICE_ID_INTEL_TGL_H_TBT_DMA1 0x9a21 #define PCI_DEVICE_ID_INTEL_ADL_TBT_DMA0 0x463e #define PCI_DEVICE_ID_INTEL_ADL_TBT_DMA1 0x466d +#define PCI_DEVICE_ID_INTEL_MTL_M_TBT_DMA0 0x7eb2 +#define PCI_DEVICE_ID_INTEL_MTL_P_TBT_DMA0 0x7ec2 +#define PCI_DEVICE_ID_INTEL_MTL_P_TBT_DMA1 0x7ec3 /* Intel WIFI Ids */ #define PCI_DEVICE_ID_1000_SERIES_WIFI 0x0084 @@ -4293,12 +4374,14 @@ #define PCI_DEVICE_ID_INTEL_JSL_IPU 0x4e19 #define PCI_DEVICE_ID_INTEL_ADL_IPU 0x465d #define PCI_DEVICE_ID_INTEL_ADL_N_IPU 0x462e +#define PCI_DEVICE_ID_INTEL_MTL_IPU 0x7d19 /* Intel Dynamic Tuning Technology Device */ #define PCI_DEVICE_ID_INTEL_CML_DTT 0x1903 #define PCI_DEVICE_ID_INTEL_TGL_DTT 0x9A03 #define PCI_DEVICE_ID_INTEL_JSL_DTT 0x4E03 #define PCI_DEVICE_ID_INTEL_ADL_DTT 0x461d +#define PCI_DEVICE_ID_INTEL_MTL_DTT 0x7d03 /* Intel CNVi WiFi/BT device IDs */ #define PCI_DEVICE_ID_INTEL_CML_LP_CNVI_WIFI 0x02f0 diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 8f220a8..d831670 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -28,6 +28,8 @@ }; static const struct cpu_device_id cpu_table[] = { + { X86_VENDOR_INTEL, CPUID_METEORLAKE_1_A0}, + { X86_VENDOR_INTEL, CPUID_METEORLAKE_2_A0}, { X86_VENDOR_INTEL, CPUID_SKYLAKE_C0 }, { X86_VENDOR_INTEL, CPUID_SKYLAKE_D0 }, { X86_VENDOR_INTEL, CPUID_SKYLAKE_HQ0 }, diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 19d7336..2753a04 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -1257,6 +1257,10 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_MTL_CSE0, + PCI_DEVICE_ID_INTEL_MTL_CSE1, + PCI_DEVICE_ID_INTEL_MTL_CSE2, + PCI_DEVICE_ID_INTEL_MTL_CSE3, PCI_DEVICE_ID_INTEL_APL_CSE0, PCI_DEVICE_ID_INTEL_GLK_CSE0, PCI_DEVICE_ID_INTEL_CNL_CSE0, diff --git a/src/soc/intel/common/block/dsp/dsp.c b/src/soc/intel/common/block/dsp/dsp.c index 35e1670..6b2c619 100644 --- a/src/soc/intel/common/block/dsp/dsp.c +++ b/src/soc/intel/common/block/dsp/dsp.c @@ -13,6 +13,14 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_MTL_AUDIO_1, + PCI_DEVICE_ID_INTEL_MTL_AUDIO_2, + PCI_DEVICE_ID_INTEL_MTL_AUDIO_3, + PCI_DEVICE_ID_INTEL_MTL_AUDIO_4, + PCI_DEVICE_ID_INTEL_MTL_AUDIO_5, + PCI_DEVICE_ID_INTEL_MTL_AUDIO_6, + PCI_DEVICE_ID_INTEL_MTL_AUDIO_7, + PCI_DEVICE_ID_INTEL_MTL_AUDIO_8, PCI_DEVICE_ID_INTEL_APL_AUDIO, PCI_DEVICE_ID_INTEL_CNL_AUDIO, PCI_DEVICE_ID_INTEL_GLK_AUDIO, diff --git a/src/soc/intel/common/block/dtt/dtt.c b/src/soc/intel/common/block/dtt/dtt.c index 58afd74..6f1e5d3 100644 --- a/src/soc/intel/common/block/dtt/dtt.c +++ b/src/soc/intel/common/block/dtt/dtt.c @@ -5,6 +5,7 @@ #include <device/pci_ids.h> static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_MTL_DTT, PCI_DEVICE_ID_INTEL_CML_DTT, PCI_DEVICE_ID_INTEL_TGL_DTT, PCI_DEVICE_ID_INTEL_JSL_DTT, diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 6118f99..fa8e2fc8 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -177,6 +177,9 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_MTL_M_GT2, + PCI_DEVICE_ID_INTEL_MTL_P_GT2_1, + PCI_DEVICE_ID_INTEL_MTL_P_GT2_2, PCI_DEVICE_ID_INTEL_APL_IGD_HD_505, PCI_DEVICE_ID_INTEL_APL_IGD_HD_500, PCI_DEVICE_ID_INTEL_CNL_GT2_ULX_1, diff --git a/src/soc/intel/common/block/hda/hda.c b/src/soc/intel/common/block/hda/hda.c index 1afc16c..4eb2b0f 100644 --- a/src/soc/intel/common/block/hda/hda.c +++ b/src/soc/intel/common/block/hda/hda.c @@ -21,6 +21,14 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_MTL_AUDIO_1, + PCI_DEVICE_ID_INTEL_MTL_AUDIO_2, + PCI_DEVICE_ID_INTEL_MTL_AUDIO_3, + PCI_DEVICE_ID_INTEL_MTL_AUDIO_4, + PCI_DEVICE_ID_INTEL_MTL_AUDIO_5, + PCI_DEVICE_ID_INTEL_MTL_AUDIO_6, + PCI_DEVICE_ID_INTEL_MTL_AUDIO_7, + PCI_DEVICE_ID_INTEL_MTL_AUDIO_8, PCI_DEVICE_ID_INTEL_SKL_AUDIO, PCI_DEVICE_ID_INTEL_SKL_H_AUDIO, PCI_DEVICE_ID_INTEL_LWB_AUDIO, diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index c1d75e0..3a4d2e6 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -175,6 +175,12 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_MTL_I2C0, + PCI_DEVICE_ID_INTEL_MTL_I2C1, + PCI_DEVICE_ID_INTEL_MTL_I2C2, + PCI_DEVICE_ID_INTEL_MTL_I2C3, + PCI_DEVICE_ID_INTEL_MTL_I2C4, + PCI_DEVICE_ID_INTEL_MTL_I2C5, PCI_DEVICE_ID_INTEL_SPT_I2C0, PCI_DEVICE_ID_INTEL_SPT_I2C1, PCI_DEVICE_ID_INTEL_SPT_I2C2, diff --git a/src/soc/intel/common/block/lpc/lpc.c b/src/soc/intel/common/block/lpc/lpc.c index 9706f92..835f9b1 100644 --- a/src/soc/intel/common/block/lpc/lpc.c +++ b/src/soc/intel/common/block/lpc/lpc.c @@ -106,6 +106,14 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_MTL_ESPI_0, + PCI_DEVICE_ID_INTEL_MTL_ESPI_1, + PCI_DEVICE_ID_INTEL_MTL_ESPI_2, + PCI_DEVICE_ID_INTEL_MTL_ESPI_3, + PCI_DEVICE_ID_INTEL_MTL_ESPI_4, + PCI_DEVICE_ID_INTEL_MTL_ESPI_5, + PCI_DEVICE_ID_INTEL_MTL_ESPI_6, + PCI_DEVICE_ID_INTEL_MTL_ESPI_7, PCI_DEVICE_ID_INTEL_SPT_LP_SAMPLE, PCI_DEVICE_ID_INTEL_SPT_LP_U_BASE, PCI_DEVICE_ID_INTEL_SPT_LP_U_PREMIUM, diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index 16da691..ac9f74b 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -144,6 +144,7 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_MTL_P2SB, PCI_DEVICE_ID_INTEL_APL_P2SB, PCI_DEVICE_ID_INTEL_GLK_P2SB, PCI_DEVICE_ID_INTEL_LWB_P2SB, diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index b17a1f3..50053c8 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -66,6 +66,18 @@ }; static const unsigned short pcie_device_ids[] = { + PCI_DEVICE_ID_INTEL_MTL_PCIE_RP1, + PCI_DEVICE_ID_INTEL_MTL_PCIE_RP2, + PCI_DEVICE_ID_INTEL_MTL_PCIE_RP3, + PCI_DEVICE_ID_INTEL_MTL_PCIE_RP4, + PCI_DEVICE_ID_INTEL_MTL_PCIE_RP5, + PCI_DEVICE_ID_INTEL_MTL_PCIE_RP6, + PCI_DEVICE_ID_INTEL_MTL_PCIE_RP7, + PCI_DEVICE_ID_INTEL_MTL_PCIE_RP8, + PCI_DEVICE_ID_INTEL_MTL_PCIE_RP9, + PCI_DEVICE_ID_INTEL_MTL_PCIE_RP10, + PCI_DEVICE_ID_INTEL_MTL_PCIE_RP11, + PCI_DEVICE_ID_INTEL_MTL_PCIE_RP12, PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1, PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP2, PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP3, diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index b64841d..d7c9d61 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -111,6 +111,9 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_MTL_PMC, + PCI_DEVICE_ID_INTEL_MTL_M_PMC, + PCI_DEVICE_ID_INTEL_MTL_P_PMC, PCI_DEVICE_ID_INTEL_DNV_PMC, PCI_DEVICE_ID_INTEL_SPT_LP_PMC, PCI_DEVICE_ID_INTEL_SPT_H_PMC, diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c index 08c1bbb..8b24a04 100644 --- a/src/soc/intel/common/block/sata/sata.c +++ b/src/soc/intel/common/block/sata/sata.c @@ -13,6 +13,9 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_MTL_SATA_1, + PCI_DEVICE_ID_INTEL_MTL_SATA_2, + PCI_DEVICE_ID_INTEL_MTL_SATA_3, PCI_DEVICE_ID_INTEL_SPT_U_SATA, PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA, PCI_DEVICE_ID_INTEL_SPT_KBL_SATA, diff --git a/src/soc/intel/common/block/smbus/smbus.c b/src/soc/intel/common/block/smbus/smbus.c index 94a54b7..2a3ca53 100644 --- a/src/soc/intel/common/block/smbus/smbus.c +++ b/src/soc/intel/common/block/smbus/smbus.c @@ -74,6 +74,7 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_MTL_SMBUS, PCI_DEVICE_ID_INTEL_APL_SMBUS, PCI_DEVICE_ID_INTEL_CNL_SMBUS, PCI_DEVICE_ID_INTEL_CNP_H_SMBUS, diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index 33d62c1..1d09063 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -39,6 +39,10 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_MTL_SPI0, + PCI_DEVICE_ID_INTEL_MTL_GSPI0, + PCI_DEVICE_ID_INTEL_MTL_GSPI1, + PCI_DEVICE_ID_INTEL_MTL_GSPI2, PCI_DEVICE_ID_INTEL_SPT_SPI1, PCI_DEVICE_ID_INTEL_SPT_SPI2, PCI_DEVICE_ID_INTEL_SPT_SPI3, diff --git a/src/soc/intel/common/block/sram/sram.c b/src/soc/intel/common/block/sram/sram.c index 1badb83..f6d834b 100644 --- a/src/soc/intel/common/block/sram/sram.c +++ b/src/soc/intel/common/block/sram/sram.c @@ -33,6 +33,9 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_MTL_SRAM, + PCI_DEVICE_ID_INTEL_MTL_M_SRAM, + PCI_DEVICE_ID_INTEL_MTL_P_SRAM, PCI_DEVICE_ID_INTEL_APL_SRAM, PCI_DEVICE_ID_INTEL_GLK_SRAM, PCI_DEVICE_ID_INTEL_ICL_SRAM, diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index f50690e..3baeb1e 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -327,6 +327,9 @@ }; static const unsigned short systemagent_ids[] = { + PCI_DEVICE_ID_INTEL_MTL_M_ID, + PCI_DEVICE_ID_INTEL_MTL_P_ID_1, + PCI_DEVICE_ID_INTEL_MTL_P_ID_2, PCI_DEVICE_ID_INTEL_GLK_NB, PCI_DEVICE_ID_INTEL_APL_NB, PCI_DEVICE_ID_INTEL_CNL_ID_U, diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 2e70d05..4f534ac 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -344,6 +344,9 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_MTL_UART0, + PCI_DEVICE_ID_INTEL_MTL_UART1, + PCI_DEVICE_ID_INTEL_MTL_UART2, PCI_DEVICE_ID_INTEL_SPT_UART0, PCI_DEVICE_ID_INTEL_SPT_UART1, PCI_DEVICE_ID_INTEL_SPT_UART2, diff --git a/src/soc/intel/common/block/usb4/usb4.c b/src/soc/intel/common/block/usb4/usb4.c index 0ec4d5f..f67e2d9 100644 --- a/src/soc/intel/common/block/usb4/usb4.c +++ b/src/soc/intel/common/block/usb4/usb4.c @@ -53,6 +53,9 @@ #endif static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_MTL_M_TBT_DMA0, + PCI_DEVICE_ID_INTEL_MTL_P_TBT_DMA0, + PCI_DEVICE_ID_INTEL_MTL_P_TBT_DMA1, PCI_DEVICE_ID_INTEL_TGL_TBT_DMA0, PCI_DEVICE_ID_INTEL_TGL_TBT_DMA1, PCI_DEVICE_ID_INTEL_TGL_H_TBT_DMA0, diff --git a/src/soc/intel/common/block/xdci/xdci.c b/src/soc/intel/common/block/xdci/xdci.c index 5322075..282da0b 100644 --- a/src/soc/intel/common/block/xdci/xdci.c +++ b/src/soc/intel/common/block/xdci/xdci.c @@ -27,6 +27,9 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_MTL_XDCI, + PCI_DEVICE_ID_INTEL_MTL_M_XDCI, + PCI_DEVICE_ID_INTEL_MTL_P_XDCI, PCI_DEVICE_ID_INTEL_APL_XDCI, PCI_DEVICE_ID_INTEL_CNL_LP_XDCI, PCI_DEVICE_ID_INTEL_GLK_XDCI, diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c index 5b19fc9..c2c5723 100644 --- a/src/soc/intel/common/block/xhci/xhci.c +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -106,6 +106,9 @@ }; static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_MTL_XHCI, + PCI_DEVICE_ID_INTEL_MTL_M_XHCI, + PCI_DEVICE_ID_INTEL_MTL_P_XHCI, PCI_DEVICE_ID_INTEL_APL_XHCI, PCI_DEVICE_ID_INTEL_CNL_LP_XHCI, PCI_DEVICE_ID_INTEL_GLK_XHCI, -- To view, visit https://review.coreboot.org/c/coreboot/+/62581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie71abb70b88db0acec8a320c3e2c20c54bbb4a8a Gerrit-Change-Number: 62581 Gerrit-PatchSet: 1 Gerrit-Owner: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/wwan/fm: Include option to add ACPI _DSD for DmaProperty
by EricR Lai (Code Review) 04 Mar '22

04 Mar '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Nick Vaccaro. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62436 ) Change subject: drivers/wwan/fm: Include option to add ACPI _DSD for DmaProperty ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62436 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If485ac5314fae6e6faefac43fcfcea4f4cdd02c0 Gerrit-Change-Number: 62436 Gerrit-PatchSet: 3 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Fri, 04 Mar 2022 00:01:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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