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Change subject: device/mmio.h: Move readXp/writeXp helpers to device/mmio.h
......................................................................
Patch Set 2: Code-Review+1
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Change subject: libpayload/pci: Add PCIe interfaces for MediaTek platform
......................................................................
Patch Set 7:
(4 comments)
File payloads/libpayload/Kconfig:
https://review.coreboot.org/c/coreboot/+/56794/comment/fb01d84e_e62d5a95
PS3, Line 408: in
> on
Done
https://review.coreboot.org/c/coreboot/+/56794/comment/70193082_7b6fc672
PS3, Line 408: PCI
> PCI or PCIE? […]
Use PCIe instead, thanks.
File payloads/libpayload/drivers/pcie_mediatek.c:
https://review.coreboot.org/c/coreboot/+/56794/comment/71a62403_c92dd1da
PS3, Line 50: ((1 << (size * 8)) - 1)
> This mask shouldn't be necessary, as the return type of the `pci_read_configX()` functions already t […]
Done, use pci_map_bus() instead, thanks.
File payloads/libpayload/include/pci.h:
https://review.coreboot.org/c/coreboot/+/56794/comment/13f8887f_343ca316
PS3, Line 116: void pci_update_hw_base(uintptr_t base);
> Please extend the commit message, why this is useful to have, or add a comment here.
Added introduction to commit message, thanks.
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Change subject: amdfwtool: Clear struct match before regular expression matching
......................................................................
Patch Set 7:
(1 comment)
File util/amdfwtool/data_parse.c:
https://review.coreboot.org/c/coreboot/+/62482/comment/d8466c0a_d6c6365c
PS7, Line 483: regmatch_t match[N_MATCHES] = {0};
> should all elements be initialized to -1 here too? is_valid_entry will overwrite all before those ge […]
Done
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Zheng Bao, Nikolai Vyssotski, Fred Reitberger, Rob Barnes, Karthik Ramasubramanian, Karthikeyan Ramasubramanian, Karthikeyan Ramasubramanian, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: amdfwtool: Clear struct match before regular expression matching
......................................................................
amdfwtool: Clear struct match before regular expression matching
If it is not cleared and the number of strings is fewer than last
iteration, the match[3] will keep the last value, which actually
should be empty.
Add assert to make sure the level is a legal value.
BUG=b:222038278
Change-Id: If14e0923fbb1648d83784eb5dc1411c93227db5a
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/data_parse.c
1 file changed, 13 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/62482/8
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Change subject: soc/mediatek/mt8195: Enable PCIe support for mt8195
......................................................................
Patch Set 15:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56793/comment/9e428586_0d941099
PS14, Line 7: soc/mediatek
> soc/mediatek/mt8195
Done
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Change subject: soc/mediatek/mt8195: Enable PCIe support for mt8195
......................................................................
Patch Set 15:
(1 comment)
File src/soc/mediatek/mt8195/Kconfig:
https://review.coreboot.org/c/coreboot/+/56793/comment/8d4cfdae_ad9908ba
PS14, Line 58:
> Unrelated change.
Done
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Hello Shelley Chen, Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/56791
to look at the new patch set (#13).
Change subject: soc/mediatek: Add PCIe support
......................................................................
soc/mediatek: Add PCIe support
Add PCIe support for MediaTek platform.
Reference:
- MT8195 Register Map V0.3-2, Chapter 3.18 PCIe controller (Page 1250)
- linux/drivers/pci/controller/pcie-mediatek-gen3.c
This code is based on MT8195 platform, but it should be common in each
platform with the same PCIe IP in the future.
TEST=Build pass and boot up to kernel successfully via SSD on Cherry
board, here is the SSD information in boot log:
== NVME IDENTIFY CONTROLLER DATA ==
PCI VID : 0x1987
PCI SSVID : 0x1987
SN : 28F40713077B0012602
MN : Phison ESE1A043-X28
RAB : 0x1
AERL : 0x3
SQES : 0x66
CQES : 0x44
NN : 0x1
Identified NVMe model Phison ESE1A043-X28
BUG=b:178565024
Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com>
Change-Id: Ib9b6adaafa20aeee136372ec9564273f86776da0
---
M src/soc/mediatek/common/Kconfig
A src/soc/mediatek/common/include/soc/pcie_common.h
A src/soc/mediatek/common/pcie.c
3 files changed, 279 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/56791/13
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