Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62545 )
Change subject: soc/amd/*/northbridge,root_complex: simplify mmconf_resource index ......................................................................
soc/amd/*/northbridge,root_complex: simplify mmconf_resource index
In the northbridge's and root complex' read_resources function, the mmconf resource used the number of the MMIO_CONF_BASE MSR as index which might be misleading. Instead use idx++ as a unique index for this resource.
TEST=Resource allocator doesn't complain and no related warnings or errors in dmesg. The update_constraints console output changes like expected:
Before: PCI: 00:00.0 c0010058 base f8000000 limit fbffffff mem (fixed) After: PCI: 00:00.0 06 base f8000000 limit fbffffff mem (fixed)
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: Id66c6153fad86bed36db7bd2455075f4a0850750 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62545 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Raul Rangel rrangel@chromium.org --- M src/soc/amd/cezanne/root_complex.c M src/soc/amd/picasso/root_complex.c M src/soc/amd/sabrina/root_complex.c M src/soc/amd/stoneyridge/northbridge.c 4 files changed, 5 insertions(+), 4 deletions(-)
Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved
diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index dde59d4..e29b4e0 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -138,7 +138,7 @@ ram_resource(dev, idx++, early_reserved_dram_end / KiB, (mem_usable - early_reserved_dram_end) / KiB);
- mmconf_resource(dev, MMIO_CONF_BASE); + mmconf_resource(dev, idx++);
if (!hob) { printk(BIOS_ERR, "%s incomplete because no HOB list was found\n", diff --git a/src/soc/amd/picasso/root_complex.c b/src/soc/amd/picasso/root_complex.c index 4ea8bc2..076588e 100644 --- a/src/soc/amd/picasso/root_complex.c +++ b/src/soc/amd/picasso/root_complex.c @@ -136,7 +136,7 @@ ram_resource(dev, idx++, early_reserved_dram_end / KiB, (mem_usable - early_reserved_dram_end) / KiB);
- mmconf_resource(dev, MMIO_CONF_BASE); + mmconf_resource(dev, idx++);
if (!hob) { printk(BIOS_ERR, "%s incomplete because no HOB list was found\n", diff --git a/src/soc/amd/sabrina/root_complex.c b/src/soc/amd/sabrina/root_complex.c index e73c30e..fc49f4f 100644 --- a/src/soc/amd/sabrina/root_complex.c +++ b/src/soc/amd/sabrina/root_complex.c @@ -140,7 +140,7 @@ ram_resource(dev, idx++, early_reserved_dram_end / KiB, (mem_usable - early_reserved_dram_end) / KiB);
- mmconf_resource(dev, MMIO_CONF_BASE); + mmconf_resource(dev, idx++);
if (!hob) { printk(BIOS_ERR, "Error: %s incomplete because no HOB list was found\n", diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 04472dc..0a80648 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -57,6 +57,7 @@
static void read_resources(struct device *dev) { + unsigned int idx = 0; struct resource *res;
/* @@ -64,7 +65,7 @@ * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - mmconf_resource(dev, MMIO_CONF_BASE); + mmconf_resource(dev, idx++);
/* NB IOAPIC2 resource */ res = new_resource(dev, IO_APIC2_ADDR); /* IOAPIC2 */