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Change subject: coreboot_tables.c: Expose the ACPI RSDP
......................................................................
Patch Set 2:
(1 comment)
File src/commonlib/include/commonlib/coreboot_tables.h:
https://review.coreboot.org/c/coreboot/+/62573/comment/7229f0b2_bd4fc002
PS1, Line 586: uint64_t
> (in C pointers are aligned, right?)
Says who? x86 supports misaligned everything by design! The compilers just keep trying to shave off every possible bit everywhere making every assumption they possibly can.... that is so frustrating...
> But I think that deserves a broader discussion.
Agreed, maybe that would be an interesting topic for upcoming GSoC...
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Change subject: cbfstool/linux_trampoline: Fill the ACPI RSDP entry
......................................................................
Patch Set 4: Code-Review+1
(1 comment)
File util/cbfstool/linux_trampoline.S:
https://review.coreboot.org/c/coreboot/+/62574/comment/5d26f2fc_a57a8257
PS4, Line 100: je .endScan
Why not a simple `jmp`? We know it's right on this path, isn't it?
(and I don't know if `mov` can have an effect on flags ._.)
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Change subject: util/spd_tools: Encode SDRAM min cycle time (TCKMinPs)
......................................................................
Patch Set 2: Code-Review+1
(3 comments)
Patchset:
PS2:
(+1 only because I don't have +2 permissions yet)
File util/spd_tools/src/spd_gen/lp5.go:
https://review.coreboot.org/c/coreboot/+/62387/comment/4eedc969_0c02dab0
PS1, Line 587: if ok == false || tCKMinPs == 0 {
: return LP5GetDefaultTCKMinPs(memAttribs)
: }
> I defined the default speed to TCKMinPs mapping inside the earlier table. […]
Thanks! This is nicer than what I suggested :)
File util/spd_tools/src/spd_gen/lp5.go:
https://review.coreboot.org/c/coreboot/+/62387/comment/df9f7606_6f4095e0
PS2, Line 573: Println
nit: Println() doesn't support format specifiers. Can you change it to Printf() and add a \n
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Change subject: coreboot_tables.c: Expose the ACPI RSDP
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
File src/commonlib/include/commonlib/coreboot_tables.h:
https://review.coreboot.org/c/coreboot/+/62573/comment/8d051498_471addd5
PS1, Line 586: uint64_t
> Could start now.... […]
Endianess is not the only concern. We had a bug recently that looked
(I didn't look close) like GCC generated instructions that didn't care
about the LBSs in pointers (in C pointers are aligned, right?). So
best option we have are the read/write functions in `commonlib/endian.h`,
IMHO.
But I think that deserves a broader discussion.
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Change subject: cbfstool/linux_trampoline: Fill the ACPI RSDP entry
......................................................................
Patch Set 4:
(15 comments)
File util/cbfstool/linux_trampoline.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143065):
https://review.coreboot.org/c/coreboot/+/62574/comment/c4d21478_03568cdc
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Change subject: cbfstool/linux_trampoline: Fill the ACPI RSDP entry
......................................................................
Patch Set 4:
(2 comments)
File util/cbfstool/linux_trampoline.S:
https://review.coreboot.org/c/coreboot/+/62574/comment/3ae853f4_729401e8
PS2, Line 97: ACPI_RSDP_ADDR
> Was this location unused in earlier zero page versions? i.e. no
> version check needed?
Right it was unused so version checks should not be needed.
https://review.coreboot.org/c/coreboot/+/62574/comment/779b03b4_d5c63f85
PS2, Line 100:
> `jmp .endScan` I guess? This is a path where we know the next `cmp` will […]
Done
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Hello build bot (Jenkins), Nico Huber, Arthur Heymans, ron minnich,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62574
to look at the new patch set (#4).
Change subject: cbfstool/linux_trampoline: Fill the ACPI RSDP entry
......................................................................
cbfstool/linux_trampoline: Fill the ACPI RSDP entry
With LinuxBoot Linux relied on the legacy method of fetching the RSDP
pointer to get ACPI. This uses a more modern approach available since
2018 on the Linux kernel, which involves filling in the zero page.
This method takes precedence over any other method of fetching the
RSDP in Linux (UEFI, Kexec, Legacy/BIOS). Some UEFI zealots are
threatening that legacy code will be removed from Linux so it's best
to already adapt to that possibility.
Tested on Qemu:
- With qemu the RSDP always is in the EBDA
- With a fake pointer Linux correctly does not find RDSP
Change-Id: I688b94608b03b0177c42d2834c7e3beb802ae686
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M util/cbfstool/linux_trampoline.S
M util/cbfstool/linux_trampoline.c
2 files changed, 22 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/62574/4
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Change subject: coreboot_tables.c: Expose the ACPI RSDP
......................................................................
Patch Set 1:
(1 comment)
File src/commonlib/include/commonlib/coreboot_tables.h:
https://review.coreboot.org/c/coreboot/+/62573/comment/5b6dc6b6_84850b71
PS1, Line 586: uint64_t
> Usually `lb_uint64` and no `__packed`. I don't like either way actually […]
Could start now....
hto{bl}e64() is available here, and libpayload has {bl}etoh functions....
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Change subject: cbfstool/linux_trampoline: Fill the ACPI RSDP entry
......................................................................
Patch Set 3: Verified-1
(15 comments)
File util/cbfstool/linux_trampoline.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143063):
https://review.coreboot.org/c/coreboot/+/62574/comment/f4f10eef_6f96751a
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https://review.coreboot.org/c/coreboot/+/62574/comment/455e8a49_5f9b517a
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line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143063):
https://review.coreboot.org/c/coreboot/+/62574/comment/1ec9133e_6d61e775
PS3, Line 13: 0xe8, 0x83, 0x3b, 0x43, 0x75, 0x10, 0x8b, 0x43, 0x08, 0xa3, 0x70, 0x00, 0x09, 0x00, 0x8b, 0x43,
please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143063):
https://review.coreboot.org/c/coreboot/+/62574/comment/b207731e_47b8ad7c
PS3, Line 14: 0x0c, 0xa3, 0x74, 0x00, 0x09, 0x00, 0x83, 0x3b, 0x12, 0x75, 0x00, 0x03, 0x5b, 0x04, 0x49, 0x0f,
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143063):
https://review.coreboot.org/c/coreboot/+/62574/comment/05dea68b_d5831df7
PS3, Line 14: 0x0c, 0xa3, 0x74, 0x00, 0x09, 0x00, 0x83, 0x3b, 0x12, 0x75, 0x00, 0x03, 0x5b, 0x04, 0x49, 0x0f,
please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143063):
https://review.coreboot.org/c/coreboot/+/62574/comment/662d0009_eb22ae67
PS3, Line 15: 0x85, 0x7a, 0xff, 0xff, 0xff, 0xb8, 0x00, 0x00, 0x04, 0x00, 0xc7, 0x40, 0x10, 0xff, 0xff, 0x00,
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143063):
https://review.coreboot.org/c/coreboot/+/62574/comment/d0540152_8fcfa3bd
PS3, Line 15: 0x85, 0x7a, 0xff, 0xff, 0xff, 0xb8, 0x00, 0x00, 0x04, 0x00, 0xc7, 0x40, 0x10, 0xff, 0xff, 0x00,
please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143063):
https://review.coreboot.org/c/coreboot/+/62574/comment/b41651aa_4352a001
PS3, Line 16: 0x00, 0xc7, 0x40, 0x14, 0x00, 0x9b, 0xcf, 0x00, 0xc7, 0x40, 0x18, 0xff, 0xff, 0x00, 0x00, 0xc7,
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143063):
https://review.coreboot.org/c/coreboot/+/62574/comment/2dbcd216_bf56015c
PS3, Line 16: 0x00, 0xc7, 0x40, 0x14, 0x00, 0x9b, 0xcf, 0x00, 0xc7, 0x40, 0x18, 0xff, 0xff, 0x00, 0x00, 0xc7,
please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143063):
https://review.coreboot.org/c/coreboot/+/62574/comment/84b3b3ff_2cf1d525
PS3, Line 17: 0x40, 0x1c, 0x00, 0x93, 0xcf, 0x00, 0xc6, 0x00, 0x2b, 0x89, 0x40, 0x02, 0x0f, 0x01, 0x10, 0xbe,
line over 96 characters
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143063):
https://review.coreboot.org/c/coreboot/+/62574/comment/77df8895_a7488978
PS3, Line 17: 0x40, 0x1c, 0x00, 0x93, 0xcf, 0x00, 0xc6, 0x00, 0x2b, 0x89, 0x40, 0x02, 0x0f, 0x01, 0x10, 0xbe,
please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143063):
https://review.coreboot.org/c/coreboot/+/62574/comment/5465a572_b5ce2dee
PS3, Line 18: 0x00, 0x00, 0x09, 0x00, 0xff, 0x25, 0x14, 0x02, 0x09, 0x00, 0xf4, 0xeb, 0xfd
please, no spaces at the start of a line
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