March 2022 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: coreboot_tables.c: Expose the ACPI RSDP
by Nico Huber (Code Review) March 3, 2022

March 3, 2022

Attention is currently required from: Arthur Heymans, Lance Zhao, Tim Wawrzynczak. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62573 ) Change subject: coreboot_tables.c: Expose the ACPI RSDP ...................................................................... Patch Set 1: Code-Review+1 (3 comments) File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/62573/comment/5441552a_eeced963 PS1, Line 1591: uintptr_t coreboot_rsdp; um, static? File src/include/acpi/acpi.h: https://review.coreboot.org/c/coreboot/+/62573/comment/c4757c80_3535bbc6 PS1, Line 57: uintptr_t get_coreboot_rsdp(void); Maybe don't mix this with #defines, or add some blank lines. Looks a bit odd this way. File src/lib/coreboot_table.c: https://review.coreboot.org/c/coreboot/+/62573/comment/4d16e669_b8145bd9 PS1, Line 537: lb_add_acpi_rsdp(head); I guess this will need something like `if (CONFIG(ACPI))`. -- To view, visit https://review.coreboot.org/c/coreboot/+/62573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I591312a2c48f0cbbb03b2787e4b365e9c932afff Gerrit-Change-Number: 62573 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Lance Zhao Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 03 Mar 2022 21:58:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: payloads/seabios: Update stable version to 1.16.0
by Felix Singer (Code Review) March 3, 2022

March 3, 2022

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62575 ) Change subject: payloads/seabios: Update stable version to 1.16.0 ...................................................................... payloads/seabios: Update stable version to 1.16.0 SeaBIOS 1.16.0 was released on March 2nd. Thus, update the stable version from 1.14.0 to 1.16.0. Change-Id: I475a9be47171bfbe3b3c2d4d1d14bb753d8575a8 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M payloads/external/SeaBIOS/Kconfig M payloads/external/SeaBIOS/Makefile 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/62575/1 diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index 9aea2d0..d7dd165 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -5,7 +5,7 @@ default SEABIOS_STABLE config SEABIOS_STABLE - bool "1.14.0" + bool "1.16.0" help Stable SeaBIOS version config SEABIOS_MASTER diff --git a/payloads/external/SeaBIOS/Makefile b/payloads/external/SeaBIOS/Makefile index cdcd426..502f4ea 100644 --- a/payloads/external/SeaBIOS/Makefile +++ b/payloads/external/SeaBIOS/Makefile @@ -1,5 +1,5 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master -TAG-$(CONFIG_SEABIOS_STABLE)=155821a1990b6de78dde5f98fa5ab90e802021e0 +TAG-$(CONFIG_SEABIOS_STABLE)=d239552ce7220e448ae81f41515138f7b9e3c4db TAG-$(CONFIG_SEABIOS_REVISION)=$(CONFIG_SEABIOS_REVISION_ID) project_git_repo=https://review.coreboot.org/seabios.git -- To view, visit https://review.coreboot.org/c/coreboot/+/62575 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I475a9be47171bfbe3b3c2d4d1d14bb753d8575a8 Gerrit-Change-Number: 62575 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya: Move ACPI MPTS method from DSDT to SSDT for Brya and ...
by Cliff Huang (Code Review) March 3, 2022

March 3, 2022

Attention is currently required from: Bora Guvendik, Selma Bensaid, Tim Wawrzynczak, Paul Menzel. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61887 ) Change subject: mb/google/brya: Move ACPI MPTS method from DSDT to SSDT for Brya and Redrix ...................................................................... Patch Set 12: (1 comment) File src/mainboard/google/brya/mainboard.c: https://review.coreboot.org/c/coreboot/+/61887/comment/19690f66_cb865f6c PS12, Line 71: cpi_device_path_join(parent, "RTD3._STA") > I think this could be […] The returned rtd3 dev path is with PXSX instead: static const char *pcie_rtd3_acpi_name(const struct device *dev) { /* Attached device name must be "PXSX" for the Linux Kernel to recognize it. */ return "PXSX"; } -- To view, visit https://review.coreboot.org/c/coreboot/+/61887 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f0b7638e90a7862173fca99305398bb250373e9 Gerrit-Change-Number: 61887 Gerrit-PatchSet: 12 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Cliff Huang <cliff.huang(a)intel.corp-partner.google.com> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 03 Mar 2022 21:42:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/nissa: Select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW Kconfig
by Reka Norman (Code Review) March 3, 2022

March 3, 2022

Attention is currently required from: Kangheui Won, Rizwan Qureshi, Tim Wawrzynczak, Krishna P Bhat D, Balaji Manigandan. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62570 ) Change subject: mb/google/nissa: Select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW Kconfig ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/Kconfig: https://review.coreboot.org/c/coreboot/+/62570/comment/89a5ab79_14f26055 PS1, Line 67: select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW Please move this up by one to keep them in alphabetical order. -- To view, visit https://review.coreboot.org/c/coreboot/+/62570 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib27149c527015bd54f839994e047f815e8922dc4 Gerrit-Change-Number: 62570 Gerrit-PatchSet: 1 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Comment-Date: Thu, 03 Mar 2022 21:41:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: drivers/gfx/nvidia: Add Optimus driver based on Intel PCIe RTD3
by Michael Niewöhner (Code Review) March 3, 2022

March 3, 2022

Attention is currently required from: Tim Crawford, Tim Wawrzynczak, Michał Kopeć. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62496 ) Change subject: drivers/gfx/nvidia: Add Optimus driver based on Intel PCIe RTD3 ...................................................................... Patch Set 3: (1 comment) Patchset: PS1: > Not sure if Tim was still able to work on that or not... […] Well then, I found six... I know there's some board/vendor-related stuff but IMHO there should be a single generic driver (if possible) that allows hooking up vendor/board-related setup functions if needed. CB:23041 CB:28380 CB:43615 CB:57034 CB:62381 CB:62496 (this one) -- To view, visit https://review.coreboot.org/c/coreboot/+/62496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bc6ec7a6a3e18417537b1f092a29972e9875282 Gerrit-Change-Number: 62496 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Thu, 03 Mar 2022 21:40:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common: Add Kconfig to enable compression on ME_RW blobs
by Reka Norman (Code Review) March 3, 2022

March 3, 2022

Attention is currently required from: Wonkyu Kim, Kangheui Won, Ravishankar Sarawadi, Rizwan Qureshi, Krishna P Bhat D, Balaji Manigandan, Patrick Rudolph, Reka Norman, Jamie Ryu, Subrata Banik, Tim Wawrzynczak, Nick Vaccaro, EricR Lai. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62358 ) Change subject: soc/intel/common: Add Kconfig to enable compression on ME_RW blobs ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62358/comment/ad4979d6_e81ac91f PS3, Line 13: This helps in savings of ~665KB Could you please specify that this data is from ADL-N, since there's now no other mention of ADL-N in this CL. -- To view, visit https://review.coreboot.org/c/coreboot/+/62358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e31c358b4969b077d65ce6369a877914d573aed Gerrit-Change-Number: 62358 Gerrit-PatchSet: 3 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Reka Norman <rekanorman(a)chromium.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Thu, 03 Mar 2022 21:40:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cbfstool/linux_trampoline: Fill the ACPI RSDP entry
by Arthur Heymans (Code Review) March 3, 2022

March 3, 2022

Hello Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62574 to look at the new patch set (#2). Change subject: cbfstool/linux_trampoline: Fill the ACPI RSDP entry ...................................................................... cbfstool/linux_trampoline: Fill the ACPI RSDP entry With LinuxBoot Linux relied on the legacy method of fetching the RSDP pointer to get ACPI. This uses a more modern approach available since 2018 on the Linux kernel, which involves filling in the zero page. This method takes precedence over any other method of fetching the RSDP in Linux (UEFI, Kexec, Legacy/BIOS). Some UEFI zealots are threatening that legacy code will be removed from Linux so it's best to already adapt to that possibility. Tested on Qemu: - With qemu the RSDP always is in the EBDA - With a fake pointer Linux correctly does not find RDSP Change-Id: I688b94608b03b0177c42d2834c7e3beb802ae686 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/cbfstool/linux_trampoline.S M util/cbfstool/linux_trampoline.c 2 files changed, 21 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/62574/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62574 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I688b94608b03b0177c42d2834c7e3beb802ae686 Gerrit-Change-Number: 62574 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: cbfstool/linux_trampoline: Fill the ACPI RSDP entry
by build bot (Jenkins) (Code Review) March 3, 2022

March 3, 2022

Attention is currently required from: Arthur Heymans. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62574 ) Change subject: cbfstool/linux_trampoline: Fill the ACPI RSDP entry ...................................................................... Patch Set 1: (15 comments) File util/cbfstool/linux_trampoline.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143059): https://review.coreboot.org/c/coreboot/+/62574/comment/78ef916b_70c38093 PS1, Line 6: 0xcb, 0x0f, 0x84, 0xc3, 0x00, 0x00, 0x00, 0x8b, 0x59, 0x04, 0x01, 0xcb, 0x8b, 0x49, 0x14, 0x83, line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143059): https://review.coreboot.org/c/coreboot/+/62574/comment/aeb15b3e_c5fb258d PS1, Line 6: 0xcb, 0x0f, 0x84, 0xc3, 0x00, 0x00, 0x00, 0x8b, 0x59, 0x04, 0x01, 0xcb, 0x8b, 0x49, 0x14, 0x83, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143059): https://review.coreboot.org/c/coreboot/+/62574/comment/57c028ec_e256def1 PS1, Line 11: 0xe8, 0x01, 0x09, 0x00, 0xbf, 0xd0, 0x02, 0x09, 0x00, 0x83, 0xf8, 0x00, 0x74, 0x2d, 0x83, 0x7f, line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143059): https://review.coreboot.org/c/coreboot/+/62574/comment/72c119c2_54a0034c PS1, Line 11: 0xe8, 0x01, 0x09, 0x00, 0xbf, 0xd0, 0x02, 0x09, 0x00, 0x83, 0xf8, 0x00, 0x74, 0x2d, 0x83, 0x7f, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143059): https://review.coreboot.org/c/coreboot/+/62574/comment/f2d12064_2870690e PS1, Line 13: 0xe8, 0x83, 0x3b, 0x43, 0x75, 0x10, 0x8b, 0x43, 0x08, 0xa3, 0x70, 0x00, 0x09, 0x00, 0x8b, 0x43, line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143059): https://review.coreboot.org/c/coreboot/+/62574/comment/0a4e64d5_631fae89 PS1, Line 13: 0xe8, 0x83, 0x3b, 0x43, 0x75, 0x10, 0x8b, 0x43, 0x08, 0xa3, 0x70, 0x00, 0x09, 0x00, 0x8b, 0x43, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143059): https://review.coreboot.org/c/coreboot/+/62574/comment/a1b352ff_86740266 PS1, Line 14: 0x0c, 0xa3, 0x74, 0x00, 0x09, 0x00, 0x83, 0x3b, 0x12, 0x75, 0x00, 0x03, 0x5b, 0x04, 0x49, 0x0f, line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143059): https://review.coreboot.org/c/coreboot/+/62574/comment/b847269d_d3b30e87 PS1, Line 14: 0x0c, 0xa3, 0x74, 0x00, 0x09, 0x00, 0x83, 0x3b, 0x12, 0x75, 0x00, 0x03, 0x5b, 0x04, 0x49, 0x0f, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143059): https://review.coreboot.org/c/coreboot/+/62574/comment/6f93658d_7568ac69 PS1, Line 15: 0x85, 0x7a, 0xff, 0xff, 0xff, 0xb8, 0x00, 0x00, 0x04, 0x00, 0xc7, 0x40, 0x10, 0xff, 0xff, 0x00, line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143059): https://review.coreboot.org/c/coreboot/+/62574/comment/9b5f96e9_2a8f2354 PS1, Line 15: 0x85, 0x7a, 0xff, 0xff, 0xff, 0xb8, 0x00, 0x00, 0x04, 0x00, 0xc7, 0x40, 0x10, 0xff, 0xff, 0x00, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143059): https://review.coreboot.org/c/coreboot/+/62574/comment/060e551c_131fbbaa PS1, Line 16: 0x00, 0xc7, 0x40, 0x14, 0x00, 0x9b, 0xcf, 0x00, 0xc7, 0x40, 0x18, 0xff, 0xff, 0x00, 0x00, 0xc7, line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143059): https://review.coreboot.org/c/coreboot/+/62574/comment/88054008_d03bcb6c PS1, Line 16: 0x00, 0xc7, 0x40, 0x14, 0x00, 0x9b, 0xcf, 0x00, 0xc7, 0x40, 0x18, 0xff, 0xff, 0x00, 0x00, 0xc7, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143059): https://review.coreboot.org/c/coreboot/+/62574/comment/17ddc381_cfcc2a13 PS1, Line 17: 0x40, 0x1c, 0x00, 0x93, 0xcf, 0x00, 0xc6, 0x00, 0x2b, 0x89, 0x40, 0x02, 0x0f, 0x01, 0x10, 0xbe, line over 96 characters Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143059): https://review.coreboot.org/c/coreboot/+/62574/comment/23568865_e753b138 PS1, Line 17: 0x40, 0x1c, 0x00, 0x93, 0xcf, 0x00, 0xc6, 0x00, 0x2b, 0x89, 0x40, 0x02, 0x0f, 0x01, 0x10, 0xbe, please, no spaces at the start of a line Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143059): https://review.coreboot.org/c/coreboot/+/62574/comment/7dc3ee34_e95df07f PS1, Line 18: 0x00, 0x00, 0x09, 0x00, 0xff, 0x25, 0x14, 0x02, 0x09, 0x00, 0xf4, 0xeb, 0xfd please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/62574 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I688b94608b03b0177c42d2834c7e3beb802ae686 Gerrit-Change-Number: 62574 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 03 Mar 2022 21:36:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cbfstool/linux_trampoline: Fill the ACPI RSDP entry
by Arthur Heymans (Code Review) March 3, 2022

March 3, 2022

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/62574 to review the following change. Change subject: cbfstool/linux_trampoline: Fill the ACPI RSDP entry ...................................................................... cbfstool/linux_trampoline: Fill the ACPI RSDP entry With LinuxBoot Linux relied on the legacy method of fetching the RSDP pointer to get ACPI. This uses a more modern approach available since 2018 on the Linux kernel, which involves filling in the zero page. This method takes precedence over any other method of fetching the RSDP in Linux (UEFI, Kexec, Legacy/BIOS). Some UEFI zealots are threatening that legacy code will be removed from Linux so it's best to already adapt to that possibility. Change-Id: I688b94608b03b0177c42d2834c7e3beb802ae686 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M util/cbfstool/linux_trampoline.S M util/cbfstool/linux_trampoline.c 2 files changed, 21 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/62574/1 diff --git a/util/cbfstool/linux_trampoline.S b/util/cbfstool/linux_trampoline.S index 7268528..454fb0d 100644 --- a/util/cbfstool/linux_trampoline.S +++ b/util/cbfstool/linux_trampoline.S @@ -13,7 +13,9 @@ #define CB_TAG_FORWARD 0x11 #define CB_TAG_MEMORY 0x1 #define CB_TAG_FRAMEBUFFER 0x12 +#define CB_TAG_ACPI_RSDP 0x43 +#define ACPI_RSDP_ADDR 0x70 #define E820_NR_OFFSET 0x1e8 #define LINUX_ENTRY_OFFSET 0x214 #define E820_OFFSET 0x2d0 @@ -52,7 +54,7 @@ .testMemory: cmp $CB_TAG_MEMORY, (%ebx) -jne .testFramebuffer +jne .testAcpiRsdp /* memory tag: copy e820 map and entry count. also determine alt_mem_k */ mov 4(%ebx), %eax @@ -87,6 +89,15 @@ add $20, %edi jmp .test_e820_entry +.testAcpiRsdp: +cmp $CB_TAG_ACPI_RSDP, (%ebx) +jne .testFramebuffer + +mov 8(%ebx), %eax +mov %eax, (LINUX_PARAM_LOC + ACPI_RSDP_ADDR) +mov 12(%ebx), %eax +mov %eax, (LINUX_PARAM_LOC + ACPI_RSDP_ADDR + 4) + .testFramebuffer: cmp $CB_TAG_FRAMEBUFFER, (%ebx) jne .endScan diff --git a/util/cbfstool/linux_trampoline.c b/util/cbfstool/linux_trampoline.c index b804c80..0e43ab6 100644 --- a/util/cbfstool/linux_trampoline.c +++ b/util/cbfstool/linux_trampoline.c @@ -3,17 +3,18 @@ unsigned char trampoline[] = { 0xfc, 0x31, 0xd2, 0xb9, 0x00, 0x00, 0x00, 0x00, 0xbb, 0x00, 0x00, 0x01, 0x00, 0x01, 0xcb, 0x8b, 0x01, 0x3d, 0x4c, 0x42, 0x49, 0x4f, 0x74, 0x07, 0x83, 0xc1, 0x10, 0x39, 0xcb, 0x75, 0xe9, 0x39, - 0xcb, 0x0f, 0x84, 0xaa, 0x00, 0x00, 0x00, 0x8b, 0x59, 0x04, 0x01, 0xcb, 0x8b, 0x49, 0x14, 0x83, + 0xcb, 0x0f, 0x84, 0xc3, 0x00, 0x00, 0x00, 0x8b, 0x59, 0x04, 0x01, 0xcb, 0x8b, 0x49, 0x14, 0x83, 0x3b, 0x11, 0x75, 0x05, 0x8b, 0x4b, 0x08, 0xeb, 0xcf, 0x83, 0x3b, 0x01, 0x75, 0x53, 0x8b, 0x43, 0x04, 0x83, 0xe8, 0x08, 0xc1, 0xe8, 0x02, 0x3d, 0xa0, 0x00, 0x00, 0x00, 0x7e, 0x05, 0xb8, 0xa0, 0x00, 0x00, 0x00, 0x89, 0xc6, 0xbf, 0x05, 0x00, 0x00, 0x00, 0xf7, 0xf7, 0xa3, 0xe8, 0x01, 0x09, 0x00, 0x89, 0xf0, 0x91, 0x8d, 0x73, 0x08, 0xbf, 0xd0, 0x02, 0x09, 0x00, 0xf3, 0xa5, 0x91, 0xa1, - 0xe8, 0x01, 0x09, 0x00, 0xbf, 0xd0, 0x02, 0x09, 0x00, 0x83, 0xf8, 0x00, 0x74, 0x18, 0x83, 0x7f, + 0xe8, 0x01, 0x09, 0x00, 0xbf, 0xd0, 0x02, 0x09, 0x00, 0x83, 0xf8, 0x00, 0x74, 0x2d, 0x83, 0x7f, 0x10, 0x0c, 0x7e, 0x07, 0xc7, 0x47, 0x10, 0x02, 0x00, 0x00, 0x00, 0x48, 0x83, 0xc7, 0x14, 0xeb, - 0xe8, 0x83, 0x3b, 0x12, 0x75, 0x00, 0x03, 0x5b, 0x04, 0x49, 0x75, 0x93, 0xb8, 0x00, 0x00, 0x04, - 0x00, 0xc7, 0x40, 0x10, 0xff, 0xff, 0x00, 0x00, 0xc7, 0x40, 0x14, 0x00, 0x9b, 0xcf, 0x00, 0xc7, - 0x40, 0x18, 0xff, 0xff, 0x00, 0x00, 0xc7, 0x40, 0x1c, 0x00, 0x93, 0xcf, 0x00, 0xc6, 0x00, 0x2b, - 0x89, 0x40, 0x02, 0x0f, 0x01, 0x10, 0xbe, 0x00, 0x00, 0x09, 0x00, 0xff, 0x25, 0x14, 0x02, 0x09, - 0x00, 0xf4, 0xeb, 0xfd + 0xe8, 0x83, 0x3b, 0x43, 0x75, 0x10, 0x8b, 0x43, 0x08, 0xa3, 0x70, 0x00, 0x09, 0x00, 0x8b, 0x43, + 0x0c, 0xa3, 0x74, 0x00, 0x09, 0x00, 0x83, 0x3b, 0x12, 0x75, 0x00, 0x03, 0x5b, 0x04, 0x49, 0x0f, + 0x85, 0x7a, 0xff, 0xff, 0xff, 0xb8, 0x00, 0x00, 0x04, 0x00, 0xc7, 0x40, 0x10, 0xff, 0xff, 0x00, + 0x00, 0xc7, 0x40, 0x14, 0x00, 0x9b, 0xcf, 0x00, 0xc7, 0x40, 0x18, 0xff, 0xff, 0x00, 0x00, 0xc7, + 0x40, 0x1c, 0x00, 0x93, 0xcf, 0x00, 0xc6, 0x00, 0x2b, 0x89, 0x40, 0x02, 0x0f, 0x01, 0x10, 0xbe, + 0x00, 0x00, 0x09, 0x00, 0xff, 0x25, 0x14, 0x02, 0x09, 0x00, 0xf4, 0xeb, 0xfd }; -unsigned int trampoline_len = 212; +unsigned int trampoline_len = 237; -- To view, visit https://review.coreboot.org/c/coreboot/+/62574 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I688b94608b03b0177c42d2834c7e3beb802ae686 Gerrit-Change-Number: 62574 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: coreboot_tables.c: Expose the ACPI RSDP
by Arthur Heymans (Code Review) March 3, 2022

March 3, 2022

Attention is currently required from: Arthur Heymans. Hello Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/62573 to review the following change. Change subject: coreboot_tables.c: Expose the ACPI RSDP ...................................................................... coreboot_tables.c: Expose the ACPI RSDP The ACPI RSDP can only be found in: - legacy BIOS region - via UEFI service On some systems like ARM that legacy BIOS region is not an option, so to avoid needing UEFI it makes sense to expose the RSDP via a coreboot table entry. Change-Id: I591312a2c48f0cbbb03b2787e4b365e9c932afff Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/acpi/acpi.c M src/commonlib/include/commonlib/coreboot_tables.h M src/include/acpi/acpi.h M src/lib/coreboot_table.c 4 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/62573/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 3bf57c6..390c727 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1588,6 +1588,13 @@ cbfs_preload(file); } +uintptr_t coreboot_rsdp; + +uintptr_t get_coreboot_rsdp(void) +{ + return coreboot_rsdp; +} + unsigned long write_acpi_tables(unsigned long start) { unsigned long current; @@ -1695,6 +1702,7 @@ /* We need at least an RSDP and an RSDT Table */ rsdp = (acpi_rsdp_t *) current; + coreboot_rsdp = (uintptr_t)rsdp; current += sizeof(acpi_rsdp_t); current = acpi_align_current(current); rsdt = (acpi_rsdt_t *) current; diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 91da8e0..3b215bf 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -85,6 +85,7 @@ LB_TAG_BOARD_CONFIG = 0x0040, LB_TAG_ACPI_CNVS = 0x0041, LB_TAG_TYPE_C_INFO = 0x0042, + LB_TAG_ACPI_RSDP = 0x0043, /* The following options are CMOS-related */ LB_TAG_CMOS_OPTION_TABLE = 0x00c8, LB_TAG_OPTION = 0x00c9, @@ -574,4 +575,15 @@ uint8_t tpm_version; /* 1: TPM1.2, 2: TPM2.0 */ uint8_t ppi_version; /* BCD encoded */ } __packed; + + +/* + * Handoff the ACPI RSDP + */ +struct lb_acpi_rsdp { + uint32_t tag; + uint32_t size; + uint64_t rsdp_pointer; /* Address of the ACPI RSDP */ +} __packed; + #endif diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index dade92d..0ba8767 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -54,6 +54,7 @@ }; #define RSDP_SIG "RSD PTR " /* RSDT pointer signature */ +uintptr_t get_coreboot_rsdp(void); #define ASLC "CORE" /* Must be exactly 4 bytes long! */ #define ACPI_NAME_BUFFER_SIZE 5 /* 4 chars + 1 NUL */ diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index d0cba80..ec10ff2 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <acpi/acpi.h> #include <arch/cbconfig.h> #include <console/console.h> #include <console/uart.h> @@ -420,6 +421,16 @@ return (unsigned long)rec + rec->size; } +static void lb_add_acpi_rsdp(struct lb_header *head) +{ + struct lb_acpi_rsdp *acpi_rsdp; + struct lb_record *rec = lb_new_record(head); + acpi_rsdp = (struct lb_acpi_rsdp *)rec; + acpi_rsdp->tag = LB_TAG_ACPI_RSDP; + acpi_rsdp->size = sizeof(*acpi_rsdp); + acpi_rsdp->rsdp_pointer = get_coreboot_rsdp(); +} + size_t write_coreboot_forwarding_table(uintptr_t entry, uintptr_t target) { struct lb_header *head; @@ -523,6 +534,8 @@ /* Add all cbmem entries into the coreboot tables. */ cbmem_add_records_to_cbtable(head); + lb_add_acpi_rsdp(head); + /* Remember where my valid memory ranges are */ return lb_table_fini(head); } -- To view, visit https://review.coreboot.org/c/coreboot/+/62573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I591312a2c48f0cbbb03b2787e4b365e9c932afff Gerrit-Change-Number: 62573 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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