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Change subject: payload/tianocore: Add option to build 9elements's UefiPayloadPkg fork
......................................................................
Patch Set 3: Code-Review-1
(1 comment)
Patchset:
PS3:
I'd personally prefer to not encourage using forks; the build options wont match up, the patches aren't properlly reviewed and everything should (ideally) live in upstream.
Most of the patches in the 9elements branch have been or are being upstreamed anyway.
You can always just set TIANOCORE_REPOSITORY and TIANOCORE_TAG_OR_REV locally to use a fork.
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Change subject: mb/google/brya: Move ACPI MPTS method from DSDT to SSDT for Brya and Redrix
......................................................................
Patch Set 12:
(1 comment)
File src/mainboard/google/brya/mainboard.c:
https://review.coreboot.org/c/coreboot/+/61887/comment/6788b673_2ddfa92e
PS12, Line 71: cpi_device_path_join(parent, "RTD3._STA")
I think this could be
`acpi_device_path_join(config->rtd3dev, "_STA")`
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Name of user not set #1004172 has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62418 )
Change subject: payload/tianocore: Add option to build 9elements's UefiPayloadPkg fork
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62418/comment/bda6a16c_c92d408e
PS1, Line 7: payloads/tianocore Makefile: Kconfig: Add option to build 9elements's UefiPayloadPkg fork
> payload/tianocore: Add option to build 9elements’ UefiPayloadPkg fork
Done
https://review.coreboot.org/c/coreboot/+/62418/comment/2cfd2937_5e032d14
PS1, Line 9: Signed-off-by: Ratatouilledummie <ratatouillemorde(a)gmail.com>
> Please put that at the end.
Done
Patchset:
PS3:
commit issues done
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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62505 )
Change subject: Vell: Enable USB2 port for KBD MCU
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62505/comment/f5b91a2c_c4fd6efc
PS1, Line 7: Vell: Enable USB2 port for KBD MCU
mb/google/brya/vell: Enable USB2 port for KBD MCU
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62571 )
Change subject: mb/amd/chausie/devicetree: enable GFX HDA, ACP and XHCI2 devices
......................................................................
mb/amd/chausie/devicetree: enable GFX HDA, ACP and XHCI2 devices
GFX HDA is the audio controller that provides audio output via the
external display connection, ACP is the audio coporcessor for the on-
board audio codec and XHCI2 is the third XHCI controller that provides
one USB 2.0 port. All those devices are used, so enable them in the
board's devicetree.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I186797a832470eb17752e06aa2fcc0b5c9db0398
---
M src/mainboard/amd/chausie/devicetree.cb
1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/62571/1
diff --git a/src/mainboard/amd/chausie/devicetree.cb b/src/mainboard/amd/chausie/devicetree.cb
index 1d4d9da..fa4555e 100644
--- a/src/mainboard/amd/chausie/devicetree.cb
+++ b/src/mainboard/amd/chausie/devicetree.cb
@@ -36,6 +36,7 @@
device ref gpp_bridge_5 on end
device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
device ref gfx on end # Internal GPU (GFX)
+ device ref gfx_hda on end # Display HD Audio Controller (GFXAZ)
device ref crypto on end # Crypto Coprocessor
device ref xhci_0 on # USB 3.1 (USB0)
chip drivers/usb/acpi
@@ -73,6 +74,10 @@
end
end
end
+ device ref acp on end # Audio Processor (ACP)
+ end
+ device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C
+ device ref xhci_2 on end
end
end
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Change subject: Vell: Enable USB2 port for KBD MCU
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/intel/common: Implement error codes for for heci_send_receive()
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/62299/comment/752954e9_16e65032
PS5, Line 461: printk(BIOS_DEBUG, "HECI: Trigger HECI reset\n");
: heci_reset();
I think maybe this should be a separate change apart from just changing the error codes
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62540 )
Change subject: soc/amd/stoneyridge/acpi: rename cpu.asl to pnot.asl
......................................................................
soc/amd/stoneyridge/acpi: rename cpu.asl to pnot.asl
After the patch that moved the generation of the PPKG object to
Stoneyridge's acpi.c, only the PNOT object remained in its cpu.asl, so
rename it to pnot.asl.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I0deb2d75cae98b8fcd31297d7fac5f27525efe65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62540
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Raul Rangel <rrangel(a)chromium.org>
---
M src/mainboard/amd/gardenia/dsdt.asl
M src/mainboard/amd/padmelon/dsdt.asl
M src/mainboard/google/kahlee/dsdt.asl
R src/soc/amd/stoneyridge/acpi/pnot.asl
4 files changed, 6 insertions(+), 6 deletions(-)
Approvals:
build bot (Jenkins): Verified
Raul Rangel: Looks good to me, approved
diff --git a/src/mainboard/amd/gardenia/dsdt.asl b/src/mainboard/amd/gardenia/dsdt.asl
index 6c275a0..3759384 100644
--- a/src/mainboard/amd/gardenia/dsdt.asl
+++ b/src/mainboard/amd/gardenia/dsdt.asl
@@ -24,8 +24,8 @@
/* PCI IRQ mapping for the Southbridge */
#include <pcie.asl>
- /* Describe the processor tree (\_SB) */
- #include <cpu.asl>
+ /* Power state notification */
+ #include <pnot.asl>
/* Contains the supported sleep states for this chipset */
#include <soc/amd/common/acpi/sleepstates.asl>
diff --git a/src/mainboard/amd/padmelon/dsdt.asl b/src/mainboard/amd/padmelon/dsdt.asl
index 026acf4..6104597 100644
--- a/src/mainboard/amd/padmelon/dsdt.asl
+++ b/src/mainboard/amd/padmelon/dsdt.asl
@@ -22,8 +22,8 @@
/* PCI IRQ mapping for the Southbridge */
#include <pcie.asl>
- /* Describe the processor tree (\_SB) */
- #include <cpu.asl>
+ /* Power state notification */
+ #include <pnot.asl>
/* Contains the supported sleep states for this chipset */
#include <soc/amd/common/acpi/sleepstates.asl>
diff --git a/src/mainboard/google/kahlee/dsdt.asl b/src/mainboard/google/kahlee/dsdt.asl
index 4820306..be4033b 100644
--- a/src/mainboard/google/kahlee/dsdt.asl
+++ b/src/mainboard/google/kahlee/dsdt.asl
@@ -24,8 +24,8 @@
/* PCI IRQ mapping for the Southbridge */
#include <pcie.asl>
- /* Describe the processor tree (\_SB) */
- #include <cpu.asl>
+ /* Power state notification */
+ #include <pnot.asl>
/* Contains the supported sleep states for this chipset */
#include <soc/amd/common/acpi/sleepstates.asl>
diff --git a/src/soc/amd/stoneyridge/acpi/cpu.asl b/src/soc/amd/stoneyridge/acpi/pnot.asl
similarity index 100%
rename from src/soc/amd/stoneyridge/acpi/cpu.asl
rename to src/soc/amd/stoneyridge/acpi/pnot.asl
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