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Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62505 )
Change subject: Vell: Enable USB2 port for KBD MCU
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62505/comment/f5b91a2c_c4fd6efc
PS1, Line 7: Vell: Enable USB2 port for KBD MCU
mb/google/brya/vell: Enable USB2 port for KBD MCU
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62571 )
Change subject: mb/amd/chausie/devicetree: enable GFX HDA, ACP and XHCI2 devices
......................................................................
mb/amd/chausie/devicetree: enable GFX HDA, ACP and XHCI2 devices
GFX HDA is the audio controller that provides audio output via the
external display connection, ACP is the audio coporcessor for the on-
board audio codec and XHCI2 is the third XHCI controller that provides
one USB 2.0 port. All those devices are used, so enable them in the
board's devicetree.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I186797a832470eb17752e06aa2fcc0b5c9db0398
---
M src/mainboard/amd/chausie/devicetree.cb
1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/62571/1
diff --git a/src/mainboard/amd/chausie/devicetree.cb b/src/mainboard/amd/chausie/devicetree.cb
index 1d4d9da..fa4555e 100644
--- a/src/mainboard/amd/chausie/devicetree.cb
+++ b/src/mainboard/amd/chausie/devicetree.cb
@@ -36,6 +36,7 @@
device ref gpp_bridge_5 on end
device ref gpp_bridge_a on # Internal GPP Bridge 0 to Bus A
device ref gfx on end # Internal GPU (GFX)
+ device ref gfx_hda on end # Display HD Audio Controller (GFXAZ)
device ref crypto on end # Crypto Coprocessor
device ref xhci_0 on # USB 3.1 (USB0)
chip drivers/usb/acpi
@@ -73,6 +74,10 @@
end
end
end
+ device ref acp on end # Audio Processor (ACP)
+ end
+ device ref gpp_bridge_c on # Internal GPP Bridge 2 to Bus C
+ device ref xhci_2 on end
end
end
--
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62505 )
Change subject: Vell: Enable USB2 port for KBD MCU
......................................................................
Patch Set 1: Code-Review+2
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62299 )
Change subject: soc/intel/common: Implement error codes for for heci_send_receive()
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/common/block/cse/cse.c:
https://review.coreboot.org/c/coreboot/+/62299/comment/752954e9_16e65032
PS5, Line 461: printk(BIOS_DEBUG, "HECI: Trigger HECI reset\n");
: heci_reset();
I think maybe this should be a separate change apart from just changing the error codes
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62540 )
Change subject: soc/amd/stoneyridge/acpi: rename cpu.asl to pnot.asl
......................................................................
soc/amd/stoneyridge/acpi: rename cpu.asl to pnot.asl
After the patch that moved the generation of the PPKG object to
Stoneyridge's acpi.c, only the PNOT object remained in its cpu.asl, so
rename it to pnot.asl.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I0deb2d75cae98b8fcd31297d7fac5f27525efe65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62540
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Raul Rangel <rrangel(a)chromium.org>
---
M src/mainboard/amd/gardenia/dsdt.asl
M src/mainboard/amd/padmelon/dsdt.asl
M src/mainboard/google/kahlee/dsdt.asl
R src/soc/amd/stoneyridge/acpi/pnot.asl
4 files changed, 6 insertions(+), 6 deletions(-)
Approvals:
build bot (Jenkins): Verified
Raul Rangel: Looks good to me, approved
diff --git a/src/mainboard/amd/gardenia/dsdt.asl b/src/mainboard/amd/gardenia/dsdt.asl
index 6c275a0..3759384 100644
--- a/src/mainboard/amd/gardenia/dsdt.asl
+++ b/src/mainboard/amd/gardenia/dsdt.asl
@@ -24,8 +24,8 @@
/* PCI IRQ mapping for the Southbridge */
#include <pcie.asl>
- /* Describe the processor tree (\_SB) */
- #include <cpu.asl>
+ /* Power state notification */
+ #include <pnot.asl>
/* Contains the supported sleep states for this chipset */
#include <soc/amd/common/acpi/sleepstates.asl>
diff --git a/src/mainboard/amd/padmelon/dsdt.asl b/src/mainboard/amd/padmelon/dsdt.asl
index 026acf4..6104597 100644
--- a/src/mainboard/amd/padmelon/dsdt.asl
+++ b/src/mainboard/amd/padmelon/dsdt.asl
@@ -22,8 +22,8 @@
/* PCI IRQ mapping for the Southbridge */
#include <pcie.asl>
- /* Describe the processor tree (\_SB) */
- #include <cpu.asl>
+ /* Power state notification */
+ #include <pnot.asl>
/* Contains the supported sleep states for this chipset */
#include <soc/amd/common/acpi/sleepstates.asl>
diff --git a/src/mainboard/google/kahlee/dsdt.asl b/src/mainboard/google/kahlee/dsdt.asl
index 4820306..be4033b 100644
--- a/src/mainboard/google/kahlee/dsdt.asl
+++ b/src/mainboard/google/kahlee/dsdt.asl
@@ -24,8 +24,8 @@
/* PCI IRQ mapping for the Southbridge */
#include <pcie.asl>
- /* Describe the processor tree (\_SB) */
- #include <cpu.asl>
+ /* Power state notification */
+ #include <pnot.asl>
/* Contains the supported sleep states for this chipset */
#include <soc/amd/common/acpi/sleepstates.asl>
diff --git a/src/soc/amd/stoneyridge/acpi/cpu.asl b/src/soc/amd/stoneyridge/acpi/pnot.asl
similarity index 100%
rename from src/soc/amd/stoneyridge/acpi/cpu.asl
rename to src/soc/amd/stoneyridge/acpi/pnot.asl
--
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Gerrit-Change-Number: 62540
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Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62539 )
Change subject: soc/amd/stoneyridge/acpi: generate PPKG object in generate_cpu_entries
......................................................................
soc/amd/stoneyridge/acpi: generate PPKG object in generate_cpu_entries
Generate the PPKG object in the generate_cpu_entries function instead of
generating the PCNT object that is the used in the PPKG method in
cpu.asl to provide the PPKG object. This both simplifies the code and
aligns Stoneyridge with the other AMD SoCs. This will also make the code
behave correctly in a case where the number of CPU cores/threads isn't a
power of two.
TEST=None, but equivalent change on Picasso was verified to not break
anything on Mandolin.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ib42d718102151a72a5fe812e83eb2eb4f9e7b611
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62539
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Raul Rangel <rrangel(a)chromium.org>
---
M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/thermal.asl
M src/soc/amd/stoneyridge/acpi.c
M src/soc/amd/stoneyridge/acpi/cpu.asl
3 files changed, 3 insertions(+), 42 deletions(-)
Approvals:
build bot (Jenkins): Verified
Raul Rangel: Looks good to me, approved
diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/thermal.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/thermal.asl
index 2930def..6f62aef 100644
--- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/thermal.asl
+++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/thermal.asl
@@ -2,6 +2,8 @@
#include <variant/thermal.h>
+External (\PPKG, MethodObj)
+
/* Thermal Zone */
Scope (\_TZ)
diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c
index 4c3b625..0a67088 100644
--- a/src/soc/amd/stoneyridge/acpi.c
+++ b/src/soc/amd/stoneyridge/acpi.c
@@ -151,7 +151,5 @@
acpigen_pop_len();
}
- acpigen_write_scope("\\");
- acpigen_write_name_integer("PCNT", cores);
- acpigen_pop_len();
+ acpigen_write_processor_package("PPKG", 0, cores);
}
diff --git a/src/soc/amd/stoneyridge/acpi/cpu.asl b/src/soc/amd/stoneyridge/acpi/cpu.asl
index 24b81a1..818bcdb 100644
--- a/src/soc/amd/stoneyridge/acpi/cpu.asl
+++ b/src/soc/amd/stoneyridge/acpi/cpu.asl
@@ -4,42 +4,3 @@
Method (PNOT)
{
}
-
-/*
- * Processor Object
- */
-/* These devices are created at runtime */
-External (\PCNT, IntObj)
-External (\_SB.P000, DeviceObj)
-External (\_SB.P001, DeviceObj)
-External (\_SB.P002, DeviceObj)
-External (\_SB.P003, DeviceObj)
-External (\_SB.P004, DeviceObj)
-External (\_SB.P005, DeviceObj)
-External (\_SB.P006, DeviceObj)
-External (\_SB.P007, DeviceObj)
-
-/* Return a package containing enabled processor entries */
-Method (PPKG)
-{
- If (\PCNT >= 4) {
- Return (Package ()
- {
- \_SB.P000,
- \_SB.P001,
- \_SB.P002,
- \_SB.P003
- })
- } ElseIf (\PCNT>= 2) {
- Return (Package ()
- {
- \_SB.P000,
- \_SB.P001
- })
- } Else {
- Return (Package ()
- {
- \_SB.P000
- })
- }
-}
--
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62538 )
Change subject: soc/amd/picasso/acpi: rename cpu.asl to pnot.asl
......................................................................
soc/amd/picasso/acpi: rename cpu.asl to pnot.asl
After the patch that moved the generation of the PPKG object to
Picasso's acpi.c, only the PNOT object remained in its cpu.asl, so
rename it to pnot.asl.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ic77dacb146aa823fc99f779f465fff28b2aead68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62538
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Raul Rangel <rrangel(a)chromium.org>
---
M src/mainboard/amd/bilby/dsdt.asl
M src/mainboard/amd/mandolin/dsdt.asl
M src/mainboard/google/zork/dsdt.asl
R src/soc/amd/picasso/acpi/pnot.asl
4 files changed, 6 insertions(+), 6 deletions(-)
Approvals:
build bot (Jenkins): Verified
Raul Rangel: Looks good to me, approved
diff --git a/src/mainboard/amd/bilby/dsdt.asl b/src/mainboard/amd/bilby/dsdt.asl
index 3b33adc..f1f0fd9 100644
--- a/src/mainboard/amd/bilby/dsdt.asl
+++ b/src/mainboard/amd/bilby/dsdt.asl
@@ -21,8 +21,8 @@
/* PCI IRQ mapping for the Southbridge */
#include <pcie.asl>
- /* Describe the processor tree (\_PR) */
- #include <cpu.asl>
+ /* Power state notification to ALIB */
+ #include <pnot.asl>
/* Contains the supported sleep states for this chipset */
#include <soc/amd/common/acpi/sleepstates.asl>
diff --git a/src/mainboard/amd/mandolin/dsdt.asl b/src/mainboard/amd/mandolin/dsdt.asl
index 3b33adc..f1f0fd9 100644
--- a/src/mainboard/amd/mandolin/dsdt.asl
+++ b/src/mainboard/amd/mandolin/dsdt.asl
@@ -21,8 +21,8 @@
/* PCI IRQ mapping for the Southbridge */
#include <pcie.asl>
- /* Describe the processor tree (\_PR) */
- #include <cpu.asl>
+ /* Power state notification to ALIB */
+ #include <pnot.asl>
/* Contains the supported sleep states for this chipset */
#include <soc/amd/common/acpi/sleepstates.asl>
diff --git a/src/mainboard/google/zork/dsdt.asl b/src/mainboard/google/zork/dsdt.asl
index c11052a..c2df9b7 100644
--- a/src/mainboard/google/zork/dsdt.asl
+++ b/src/mainboard/google/zork/dsdt.asl
@@ -22,8 +22,8 @@
/* PCI IRQ mapping for the Southbridge */
#include <pcie.asl>
- /* Describe the processor tree (\_PR) */
- #include <cpu.asl>
+ /* Power state notification to ALIB */
+ #include <pnot.asl>
/* Contains the supported sleep states for this chipset */
#include <soc/amd/common/acpi/sleepstates.asl>
diff --git a/src/soc/amd/picasso/acpi/cpu.asl b/src/soc/amd/picasso/acpi/pnot.asl
similarity index 100%
rename from src/soc/amd/picasso/acpi/cpu.asl
rename to src/soc/amd/picasso/acpi/pnot.asl
--
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56263 )
Change subject: [RFC] Intel IIO split stack - multidomain approach
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Working code is ready but ... due to a priority change this effort has been paused for the moment unfortunately 😞
https://review.coreboot.org/c/coreboot/+/62353/3 actually implements what this document attempted, although still by adding devicetree structures at runtime instead of in the static devicetree. Feel free to review it ;-)
I think it's a good entermediate to eventually move it to the static devicetree.
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