coreboot-gerrit March 2022

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Change in coreboot[master]: soc/amd/stoneyridge/acpi: generate PPKG object in generate_cpu_entries
by Felix Held (Code Review) 03 Mar '22

03 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62539 ) Change subject: soc/amd/stoneyridge/acpi: generate PPKG object in generate_cpu_entries ...................................................................... soc/amd/stoneyridge/acpi: generate PPKG object in generate_cpu_entries Generate the PPKG object in the generate_cpu_entries function instead of generating the PCNT object that is the used in the PPKG method in cpu.asl to provide the PPKG object. This both simplifies the code and aligns Stoneyridge with the other AMD SoCs. This will also make the code behave correctly in a case where the number of CPU cores/threads isn't a power of two. TEST=None, but equivalent change on Picasso was verified to not break anything on Mandolin. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ib42d718102151a72a5fe812e83eb2eb4f9e7b611 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62539 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/thermal.asl M src/soc/amd/stoneyridge/acpi.c M src/soc/amd/stoneyridge/acpi/cpu.asl 3 files changed, 3 insertions(+), 42 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/thermal.asl b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/thermal.asl index 2930def..6f62aef 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/thermal.asl +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/thermal.asl @@ -2,6 +2,8 @@ #include <variant/thermal.h> +External (\PPKG, MethodObj) + /* Thermal Zone */ Scope (\_TZ) diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index 4c3b625..0a67088 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -151,7 +151,5 @@ acpigen_pop_len(); } - acpigen_write_scope("\\"); - acpigen_write_name_integer("PCNT", cores); - acpigen_pop_len(); + acpigen_write_processor_package("PPKG", 0, cores); } diff --git a/src/soc/amd/stoneyridge/acpi/cpu.asl b/src/soc/amd/stoneyridge/acpi/cpu.asl index 24b81a1..818bcdb 100644 --- a/src/soc/amd/stoneyridge/acpi/cpu.asl +++ b/src/soc/amd/stoneyridge/acpi/cpu.asl @@ -4,42 +4,3 @@ Method (PNOT) { } - -/* - * Processor Object - */ -/* These devices are created at runtime */ -External (\PCNT, IntObj) -External (\_SB.P000, DeviceObj) -External (\_SB.P001, DeviceObj) -External (\_SB.P002, DeviceObj) -External (\_SB.P003, DeviceObj) -External (\_SB.P004, DeviceObj) -External (\_SB.P005, DeviceObj) -External (\_SB.P006, DeviceObj) -External (\_SB.P007, DeviceObj) - -/* Return a package containing enabled processor entries */ -Method (PPKG) -{ - If (\PCNT >= 4) { - Return (Package () - { - \_SB.P000, - \_SB.P001, - \_SB.P002, - \_SB.P003 - }) - } ElseIf (\PCNT>= 2) { - Return (Package () - { - \_SB.P000, - \_SB.P001 - }) - } Else { - Return (Package () - { - \_SB.P000 - }) - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/62539 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib42d718102151a72a5fe812e83eb2eb4f9e7b611 Gerrit-Change-Number: 62539 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/picasso/acpi: rename cpu.asl to pnot.asl
by Felix Held (Code Review) 03 Mar '22

03 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62538 ) Change subject: soc/amd/picasso/acpi: rename cpu.asl to pnot.asl ...................................................................... soc/amd/picasso/acpi: rename cpu.asl to pnot.asl After the patch that moved the generation of the PPKG object to Picasso's acpi.c, only the PNOT object remained in its cpu.asl, so rename it to pnot.asl. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ic77dacb146aa823fc99f779f465fff28b2aead68 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62538 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/amd/bilby/dsdt.asl M src/mainboard/amd/mandolin/dsdt.asl M src/mainboard/google/zork/dsdt.asl R src/soc/amd/picasso/acpi/pnot.asl 4 files changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/amd/bilby/dsdt.asl b/src/mainboard/amd/bilby/dsdt.asl index 3b33adc..f1f0fd9 100644 --- a/src/mainboard/amd/bilby/dsdt.asl +++ b/src/mainboard/amd/bilby/dsdt.asl @@ -21,8 +21,8 @@ /* PCI IRQ mapping for the Southbridge */ #include <pcie.asl> - /* Describe the processor tree (\_PR) */ - #include <cpu.asl> + /* Power state notification to ALIB */ + #include <pnot.asl> /* Contains the supported sleep states for this chipset */ #include <soc/amd/common/acpi/sleepstates.asl> diff --git a/src/mainboard/amd/mandolin/dsdt.asl b/src/mainboard/amd/mandolin/dsdt.asl index 3b33adc..f1f0fd9 100644 --- a/src/mainboard/amd/mandolin/dsdt.asl +++ b/src/mainboard/amd/mandolin/dsdt.asl @@ -21,8 +21,8 @@ /* PCI IRQ mapping for the Southbridge */ #include <pcie.asl> - /* Describe the processor tree (\_PR) */ - #include <cpu.asl> + /* Power state notification to ALIB */ + #include <pnot.asl> /* Contains the supported sleep states for this chipset */ #include <soc/amd/common/acpi/sleepstates.asl> diff --git a/src/mainboard/google/zork/dsdt.asl b/src/mainboard/google/zork/dsdt.asl index c11052a..c2df9b7 100644 --- a/src/mainboard/google/zork/dsdt.asl +++ b/src/mainboard/google/zork/dsdt.asl @@ -22,8 +22,8 @@ /* PCI IRQ mapping for the Southbridge */ #include <pcie.asl> - /* Describe the processor tree (\_PR) */ - #include <cpu.asl> + /* Power state notification to ALIB */ + #include <pnot.asl> /* Contains the supported sleep states for this chipset */ #include <soc/amd/common/acpi/sleepstates.asl> diff --git a/src/soc/amd/picasso/acpi/cpu.asl b/src/soc/amd/picasso/acpi/pnot.asl similarity index 100% rename from src/soc/amd/picasso/acpi/cpu.asl rename to src/soc/amd/picasso/acpi/pnot.asl -- To view, visit https://review.coreboot.org/c/coreboot/+/62538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic77dacb146aa823fc99f779f465fff28b2aead68 Gerrit-Change-Number: 62538 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/picasso/acpi: generate PPKG object in generate_cpu_entries call
by Felix Held (Code Review) 03 Mar '22

03 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62517 ) Change subject: soc/amd/picasso/acpi: generate PPKG object in generate_cpu_entries call ...................................................................... soc/amd/picasso/acpi: generate PPKG object in generate_cpu_entries call Generate the PPKG object in the generate_cpu_entries function instead of generating the PCNT object that is the used in the PPKG method in cpu.asl to provide the PPKG object. This both simplifies the code and aligns Picasso with Cezanne and Sabrina. This will also make the code behave correctly in a case where the number of CPU cores/threads isn't a power of two. TEST=Mandolin still boots successfully to Linux desktop and dmesg doesn't show any any possibly related problems. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ifb84435345c6d8c5d11a8b42e5538cfb86432780 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62517 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> --- M src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/thermal.asl M src/soc/amd/picasso/acpi.c M src/soc/amd/picasso/acpi/cpu.asl 3 files changed, 3 insertions(+), 54 deletions(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/thermal.asl b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/thermal.asl index 5667248..1bcadd6 100644 --- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/thermal.asl +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/thermal.asl @@ -2,6 +2,8 @@ #include <variant/thermal.h> +External (\PPKG, MethodObj) + /* Thermal Zone */ Scope (\_TZ) diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index cd8a0a0..9c798ca 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -355,7 +355,5 @@ acpigen_pop_len(); } - acpigen_write_scope("\\"); - acpigen_write_name_integer("PCNT", logical_cores); - acpigen_pop_len(); + acpigen_write_processor_package("PPKG", 0, logical_cores); } diff --git a/src/soc/amd/picasso/acpi/cpu.asl b/src/soc/amd/picasso/acpi/cpu.asl index b7395fc..29b5b5a 100644 --- a/src/soc/amd/picasso/acpi/cpu.asl +++ b/src/soc/amd/picasso/acpi/cpu.asl @@ -7,54 +7,3 @@ /* Report AC/DC state to ALIB using WAL1() */ \WAL1 () } - -/* - * Processor Object - */ -/* These devices are created at runtime */ -External (\PCNT, IntObj) -External (\_SB.C000, DeviceObj) -External (\_SB.C001, DeviceObj) -External (\_SB.C002, DeviceObj) -External (\_SB.C003, DeviceObj) -External (\_SB.C004, DeviceObj) -External (\_SB.C005, DeviceObj) -External (\_SB.C006, DeviceObj) -External (\_SB.C007, DeviceObj) - -/* Return a package containing enabled processor entries */ -Method (PPKG) -{ - If (\PCNT >= 8) { - Return (Package () - { - \_SB.C000, - \_SB.C001, - \_SB.C002, - \_SB.C003, - \_SB.C004, - \_SB.C005, - \_SB.C006, - \_SB.C007 - }) - } ElseIf (\PCNT >= 4) { - Return (Package () - { - \_SB.C000, - \_SB.C001, - \_SB.C002, - \_SB.C003 - }) - } ElseIf (\PCNT >= 2) { - Return (Package () - { - \_SB.C000, - \_SB.C001 - }) - } Else { - Return (Package () - { - \_SB.C000 - }) - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/62517 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb84435345c6d8c5d11a8b42e5538cfb86432780 Gerrit-Change-Number: 62517 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: [RFC] Intel IIO split stack - multidomain approach
by Arthur Heymans (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: Furquan Shaikh, Mariusz Szafrański, Jonathan Zhang, Paul Menzel, Angel Pons, Arthur Heymans, Aaron Durbin, Lance Zhao, Anjaneya "Reddy" Chagam, David Guckian, Martin Roth, Daocheng Bu, Suresh Bellampalli, Peter Tsung Ho Wu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56263 ) Change subject: [RFC] Intel IIO split stack - multidomain approach ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Working code is ready but ... due to a priority change this effort has been paused for the moment unfortunately 😞 https://review.coreboot.org/c/coreboot/+/62353/3 actually implements what this document attempted, although still by adding devicetree structures at runtime instead of in the static devicetree. Feel free to review it ;-) I think it's a good entermediate to eventually move it to the static devicetree. -- To view, visit https://review.coreboot.org/c/coreboot/+/56263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38ac830ee05866a09c5661ec48fab96af8135f44 Gerrit-Change-Number: 56263 Gerrit-PatchSet: 1 Gerrit-Owner: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Peter Tsung Ho Wu <tsung(a)amazon.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: David Guckian <david.guckian(a)intel.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Peter Tsung Ho Wu <tsung(a)amazon.com> Gerrit-Comment-Date: Thu, 03 Mar 2022 18:23:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: [RFC] Intel IIO split stack - multidomain approach
by Mariusz Szafrański (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: Arthur Heymans, Furquan Shaikh, Jonathan Zhang, Paul Menzel, Angel Pons, Aaron Durbin, Lance Zhao, Anjaneya "Reddy" Chagam, David Guckian, Martin Roth, Daocheng Bu, Suresh Bellampalli, Peter Tsung Ho Wu. Mariusz Szafrański has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/56263 ) Change subject: [RFC] Intel IIO split stack - multidomain approach ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > What is the state of this? It says a POC worked on the next gen hardware. Working code is ready but ... due to a priority change this effort has been paused for the moment unfortunately 😞 -- To view, visit https://review.coreboot.org/c/coreboot/+/56263 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38ac830ee05866a09c5661ec48fab96af8135f44 Gerrit-Change-Number: 56263 Gerrit-PatchSet: 1 Gerrit-Owner: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Peter Tsung Ho Wu <tsung(a)amazon.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Furquan Shaikh <furquan.m.shaikh(a)gmail.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: David Guckian <david.guckian(a)intel.com> Gerrit-Attention: Martin Roth <martinroth(a)google.com> Gerrit-Attention: Daocheng Bu <daocheng.bu(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Peter Tsung Ho Wu <tsung(a)amazon.com> Gerrit-Comment-Date: Thu, 03 Mar 2022 18:20:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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Change in coreboot[master]: include/device/pci_ids.h: Group DNV ids with similar IP blocks
by Jeff Daly (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph. Hello build bot (Jenkins), Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61185 to look at the new patch set (#6). Change subject: include/device/pci_ids.h: Group DNV ids with similar IP blocks ...................................................................... include/device/pci_ids.h: Group DNV ids with similar IP blocks Grouping Denverton ids in the same IP blocks as other SoC IP. Also, rename ids to be consistent with naming conventions of other Intel SoC IP ids. Signed-off-by: Jeff Daly <jeffd(a)silicom-usa.com> Change-Id: I1741333dcbe366019b733567f03f64c8ab227dbd --- M src/include/device/pci_ids.h M src/soc/intel/common/block/smbus/smbus.c M src/soc/intel/denverton_ns/sata.c 3 files changed, 36 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/61185/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/61185 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1741333dcbe366019b733567f03f64c8ab227dbd Gerrit-Change-Number: 61185 Gerrit-PatchSet: 6 Gerrit-Owner: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Add Kconfig to enable compression on ME_RW blobs
by Krishna P Bhat D (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: Reka Norman, Jamie Ryu, Wonkyu Kim, Subrata Banik, Kangheui Won, Ravishankar Sarawadi, Rizwan Qureshi, Tim Wawrzynczak, Balaji Manigandan, Nick Vaccaro, Patrick Rudolph, EricR Lai. Krishna P Bhat D has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62358 ) Change subject: soc/intel/common: Add Kconfig to enable compression on ME_RW blobs ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/62358/comment/4c2967e0_0b7abc2c PS1, Line 8: > Please elaborate, and share your testing details (boards, flash ROM chips, …). […] Done File src/soc/intel/common/block/cse/Makefile.inc: https://review.coreboot.org/c/coreboot/+/62358/comment/0bbafbb8_81316071 PS2, Line 88: ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_N),y) > Agreed, would rather add a kconfig like […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e31c358b4969b077d65ce6369a877914d573aed Gerrit-Change-Number: 62358 Gerrit-PatchSet: 3 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Thu, 03 Mar 2022 17:34:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Wonkyu Kim <wonkyu.kim(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Balaji Manigandan <balaji.manigandan(a)intel.com> Comment-In-Reply-To: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/nissa: Select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW Kconfig
by Krishna P Bhat D (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: Tim Wawrzynczak. Krishna P Bhat D has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62570 ) Change subject: mb/google/nissa: Select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW Kconfig ...................................................................... mb/google/nissa: Select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW Kconfig Change-Id: Ib27149c527015bd54f839994e047f815e8922dc4 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/mainboard/google/brya/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/62570/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 00e8bc9..7742bbf 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -64,6 +64,7 @@ select MEMORY_SOLDERDOWN select SOC_INTEL_ALDERLAKE_PCH_N select SYSTEM_TYPE_LAPTOP + select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW if BOARD_GOOGLE_BRYA_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/62570 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib27149c527015bd54f839994e047f815e8922dc4 Gerrit-Change-Number: 62570 Gerrit-PatchSet: 1 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common: Add Kconfig to enable compression on ME_RW blobs
by Krishna P Bhat D (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: Reka Norman, Jamie Ryu, Wonkyu Kim, Subrata Banik, Kangheui Won, Ravishankar Sarawadi, Rizwan Qureshi, Balaji Manigandan, Krishna P Bhat D, Nick Vaccaro, Patrick Rudolph, EricR Lai. Hello Reka Norman, build bot (Jenkins), Jamie Ryu, Kangheui Won, Ravishankar Sarawadi, Tim Wawrzynczak, Rizwan Qureshi, Subrata Banik, Nick Vaccaro, Balaji Manigandan, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62358 to look at the new patch set (#3). Change subject: soc/intel/common: Add Kconfig to enable compression on ME_RW blobs ...................................................................... soc/intel/common: Add Kconfig to enable compression on ME_RW blobs Add SOC_INTEL_CSE_LITE_COMPRESS_ME_RW Kconfig to enable compression on ME_RW blobs. Select the Kconfig to add LZMA compressed ME_RW blobs to ME_RW_A/B regions. This helps in savings of ~665KB in each of ME_RW_A/B regions. FMAP REGION: ME_RW_A Name Offset Type Size Comp me_rw 0x0 raw 1275246 LZMA (1957888 decompressed) (empty) 0x1375c0 null 193056 none FMAP REGION: ME_RW_B Name Offset Type Size Comp me_rw 0x0 raw 1275246 LZMA (1957888 decompressed) (empty) 0x1375c0 null 193056 none Change-Id: I2e31c358b4969b077d65ce6369a877914d573aed Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> --- M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/Makefile.inc 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/62358/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/62358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e31c358b4969b077d65ce6369a877914d573aed Gerrit-Change-Number: 62358 Gerrit-PatchSet: 3 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/denverton_ns: enable Denverton to use common MPINIT code
by Jeff Daly (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Angel Pons, Michal Motyl, Patrick Rudolph. Hello build bot (Jenkins), Mariusz Szafrański, Suresh Bellampalli, Vanessa Eusebio, Michal Motyl, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61026 to look at the new patch set (#9). Change subject: soc/intel/denverton_ns: enable Denverton to use common MPINIT code ...................................................................... soc/intel/denverton_ns: enable Denverton to use common MPINIT code Use Intel common SoC CPU MPINIT code for Denverton refactor. Signed-off-by: Jeff Daly <jeffd(a)silicom-usa.com> Change-Id: Id151ee920e10cc3d8d79c3065797bb417f6641f0 --- M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/denverton_ns/Makefile.inc M src/soc/intel/denverton_ns/chip.c M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/denverton_ns/include/soc/cpu.h 6 files changed, 183 insertions(+), 231 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/61026/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/61026 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id151ee920e10cc3d8d79c3065797bb417f6641f0 Gerrit-Change-Number: 61026 Gerrit-PatchSet: 9 Gerrit-Owner: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Reviewer: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Mariusz Szafrański <mariuszx.szafranski(a)intel.com> Gerrit-Attention: Suresh Bellampalli <suresh.bellampalli(a)intel.com> Gerrit-Attention: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Michal Motyl <michalx.motyl(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2022