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Change subject: drivers/efi: Add EFI variable store option support
......................................................................
Patch Set 10:
(1 comment)
File src/drivers/efi/Kconfig:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143013):
https://review.coreboot.org/c/coreboot/+/52564/comment/2d67cd4d_c3545991
PS10, Line 4: Adds a driver that is able to read and write an EFI formated
'formated' may be misspelled - perhaps 'formatted'?
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Change subject: bsd/cb_err: Add error code for UEFI variable store
......................................................................
Patch Set 2:
(1 comment)
File src/commonlib/bsd/include/commonlib/bsd/cb_err.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143011):
https://review.coreboot.org/c/coreboot/+/61960/comment/9743bd61_275c2282
PS2, Line 46: CB_EFI_FVH_INVALID = -500, /**< UEFI FVH is corrupted */
please, no space before tabs
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Change subject: soc/mediatek/mt8186: Add GPIO driving functions
......................................................................
Patch Set 8:
(2 comments)
File src/soc/mediatek/common/include/soc/gpio_common.h:
https://review.coreboot.org/c/coreboot/+/62471/comment/7b8827bb_babac81f
PS7, Line 45: GPIO_DRV_ADV_1_MA = 3,
> Use PA for picoampere instead of P for point(?)?
I use uA which is 10^-6 and mA is 10^-3.
File src/soc/mediatek/common/include/soc/gpio_common.h:
https://review.coreboot.org/c/coreboot/+/62471/comment/04c282d0_3920d307
PS4, Line 31: };
> I am still not fully convinced, but am too ignorant to hold this up.
thanks.
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Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62471
to look at the new patch set (#8).
Change subject: soc/mediatek/mt8186: Add GPIO driving functions
......................................................................
soc/mediatek/mt8186: Add GPIO driving functions
Add GPIO driving functions to adjust pin driving.
The value of drive strength is different for each SoC, so we define
GPIO_DRV0 to GPIO_DRV7 which are corresponding to 2/4/6/8/10/12/14/16mA
in MT8186.
This implementation is according to chapter 5.1 in MT8186 Functional
Specification.
BUG=b:218775654, b:216462313, b:212375511
TEST=build pass
Signed-off-by: Guodong Liu <guodong.liu(a)mediatek.corp-partner.google.com>
Change-Id: I6d987f28be98b515fa5c542222bda08bea1d5118
---
M src/soc/mediatek/common/include/soc/gpio_common.h
M src/soc/mediatek/mt8186/gpio.c
M src/soc/mediatek/mt8186/include/soc/gpio.h
3 files changed, 529 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/62471/8
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62471 )
Change subject: soc/mediatek/mt8186: Add GPIO driving functions
......................................................................
Patch Set 7:
(1 comment)
File src/soc/mediatek/common/include/soc/gpio_common.h:
https://review.coreboot.org/c/coreboot/+/62471/comment/ea8048dc_64f03fb6
PS7, Line 45: GPIO_DRV_ADV_1_MA = 3,
Use PA for picoampere instead of P for point(?)?
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Change subject: soc/mediatek/mt8186: Add GPIO driving functions
......................................................................
Patch Set 7:
(1 comment)
File src/soc/mediatek/common/include/soc/gpio_common.h:
https://review.coreboot.org/c/coreboot/+/62471/comment/f3b7b45e_a948b162
PS4, Line 31: };
> There are 8 stage for all mediatek SoCs, but they may have different drive strength. […]
I am still not fully convinced, but am too ignorant to hold this up.
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Change subject: soc/mediatek: Enable PCIe support for mt8195
......................................................................
Patch Set 14:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/56793/comment/0a1de583_a7da3939
PS14, Line 7: soc/mediatek
soc/mediatek/mt8195
File src/soc/mediatek/mt8195/Kconfig:
https://review.coreboot.org/c/coreboot/+/56793/comment/37123c6d_cf479c8c
PS8, Line 13: select PCIE_MEDIATEK
> Thanks for reminder, I think we should enable this for specific board, it will affect the boot time […]
hungte@, do you prefer enabling PCI in mainboard Kconfig?
File src/soc/mediatek/mt8195/Kconfig:
https://review.coreboot.org/c/coreboot/+/56793/comment/b99e40b8_62433d3d
PS14, Line 58:
Unrelated change.
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Change subject: libpayload/bin/lpgcc: Make lpgcc provide TPM configuration for vboot
......................................................................
Patch Set 3:
(2 comments)
Patchset:
PS2:
> Oh I see, someone else did... hmmm. […]
I re-uploaded the patch. We should be ok :)
File payloads/libpayload/bin/lpgcc:
https://review.coreboot.org/c/coreboot/+/62516/comment/042b448a_472d61a6
PS2, Line 67: 61960: bsd/cb_err: Add error code for UEFI variable store | https://review.coreboot.org/c/coreboot/+/61960
> ?
Done
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Change subject: soc/mediatek: Add PCIe support
......................................................................
Patch Set 12:
(5 comments)
File src/soc/mediatek/common/include/soc/pcie_common.h:
https://review.coreboot.org/c/coreboot/+/56791/comment/d50655e2_2c2ecb7e
PS11, Line 19: void (*reset)( uintptr_t base, bool enable);
> space prohibited after that open parenthesis '('
Please fix.
https://review.coreboot.org/c/coreboot/+/56791/comment/0e3f6ba7_f68b4b7f
PS11, Line 25: domain
dev
Same for other instances in pcie.c.
File src/soc/mediatek/common/pcie.c:
https://review.coreboot.org/c/coreboot/+/56791/comment/5fa6470b_e6434949
PS10, Line 120: val = read32(ctrl->base + PCIE_SETTING_REG);
: val |= PCIE_RC_MODE;
: write32(ctrl->base + PCIE_SETTING_REG, val);
> I use write32p() instead, is that OK?
Ack
File src/soc/mediatek/common/pcie.c:
https://review.coreboot.org/c/coreboot/+/56791/comment/ec044bbc_f3128b48
PS11, Line 3: arch
device
Please remember to sort the headers.
https://review.coreboot.org/c/coreboot/+/56791/comment/16882ba9_4ffc9833
PS11, Line 197: mtk_pcie_domain_set_resources
Maybe put this below mtk_pcie_domain_read_resources() to follow the calling order.
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