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Change subject: soc/mediatek/mt8186: Modify internal capid to 0xE0
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62563/comment/11ec94aa_6b103493
PS1, Line 9: Request from Google hardware team:
: We cannot disable the internal cap.
since this is 'mt8186' instead of 'corsola' (board), we should not say request from google hw team. instead, you can say
The mainboard may not be able to disable the internal cap,
so we want to set 0xe0 for all boards to minimize the internal
cap. And a mainboard implementation may choose XTAL with higher
cload if the frequency requirement meets, and the total
capacitance can be tuned externally for different boards.
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Change subject: soc/mediatek/mt8186: Modify internal capid to 0xE0
......................................................................
soc/mediatek/mt8186: Modify internal capid to 0xE0
Request from Google hardware team:
We cannot disable the internal cap. Therefore, set 0xE0 for all
boards to minimize the internal cap. And it's allowed for ODM to
choose xtal with higher cload if the frequency requirement meets,
and ODM can tune the total capacitance externally.
BUG=b:218439447
TEST=set capid to 0xe0.
Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com>
Change-Id: I2139e6b3456d7a50e3cdc8fc606e5f6ea3406044
---
M src/soc/mediatek/mt8186/rtc.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/62563/1
diff --git a/src/soc/mediatek/mt8186/rtc.c b/src/soc/mediatek/mt8186/rtc.c
index 2f78be8..7375bc3 100644
--- a/src/soc/mediatek/mt8186/rtc.c
+++ b/src/soc/mediatek/mt8186/rtc.c
@@ -13,7 +13,7 @@
#include <soc/pmic_wrap.h>
#include <timer.h>
-#define MT8186_RTC_DXCO_CAPID 0xC0
+#define MT8186_RTC_DXCO_CAPID 0xE0
/* Initialize RTC setting of using DCXO clock */
static bool rtc_enable_dcxo(void)
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: [TEST] mb/google/dedede: Update DRAM population
......................................................................
[TEST] mb/google/dedede: Update DRAM population
In order to configure DRAM with half population for EVT all SKUs
in Beadrix project with built-in 4 memory IC of Channel 0 and
channel 1 (total 8 GB), we desolder 2 memory IC of Channel 1
(4 GB) according to mainboard schematic. We set half populated
to 1 to indicate the only usage of 2 memory IC of Channel 0 (4 GB).
The number of memory segments is passed to FSP for memory
initialization.
BUG=b:222232246
BRANCH=dedede
TEST=Build and boot up beadrix built-in DRAM Channel 0 (4 GB)
only. The number of memory information is passed to FSP.
Signed-off-by: Teddy Shih <teddyshih(a)ami.corp-partner.google.com>
Change-Id: I8ec14c113ff7c355138e7b48640fb1766fb5958d
---
M src/mainboard/google/dedede/variants/beadrix/memory.c
1 file changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/62556/3
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Change subject: drivers/efi: Add EFI variable store option support
......................................................................
Patch Set 10:
(1 comment)
File src/drivers/efi/Kconfig:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143013):
https://review.coreboot.org/c/coreboot/+/52564/comment/2d67cd4d_c3545991
PS10, Line 4: Adds a driver that is able to read and write an EFI formated
'formated' may be misspelled - perhaps 'formatted'?
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Change subject: bsd/cb_err: Add error code for UEFI variable store
......................................................................
Patch Set 2:
(1 comment)
File src/commonlib/bsd/include/commonlib/bsd/cb_err.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-143011):
https://review.coreboot.org/c/coreboot/+/61960/comment/9743bd61_275c2282
PS2, Line 46: CB_EFI_FVH_INVALID = -500, /**< UEFI FVH is corrupted */
please, no space before tabs
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Change subject: soc/mediatek/mt8186: Add GPIO driving functions
......................................................................
Patch Set 8:
(2 comments)
File src/soc/mediatek/common/include/soc/gpio_common.h:
https://review.coreboot.org/c/coreboot/+/62471/comment/7b8827bb_babac81f
PS7, Line 45: GPIO_DRV_ADV_1_MA = 3,
> Use PA for picoampere instead of P for point(?)?
I use uA which is 10^-6 and mA is 10^-3.
File src/soc/mediatek/common/include/soc/gpio_common.h:
https://review.coreboot.org/c/coreboot/+/62471/comment/04c282d0_3920d307
PS4, Line 31: };
> I am still not fully convinced, but am too ignorant to hold this up.
thanks.
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Hello Hung-Te Lin, build bot (Jenkins), Yu-Ping Wu,
I'd like you to reexamine a change. Please visit
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Change subject: soc/mediatek/mt8186: Add GPIO driving functions
......................................................................
soc/mediatek/mt8186: Add GPIO driving functions
Add GPIO driving functions to adjust pin driving.
The value of drive strength is different for each SoC, so we define
GPIO_DRV0 to GPIO_DRV7 which are corresponding to 2/4/6/8/10/12/14/16mA
in MT8186.
This implementation is according to chapter 5.1 in MT8186 Functional
Specification.
BUG=b:218775654, b:216462313, b:212375511
TEST=build pass
Signed-off-by: Guodong Liu <guodong.liu(a)mediatek.corp-partner.google.com>
Change-Id: I6d987f28be98b515fa5c542222bda08bea1d5118
---
M src/soc/mediatek/common/include/soc/gpio_common.h
M src/soc/mediatek/mt8186/gpio.c
M src/soc/mediatek/mt8186/include/soc/gpio.h
3 files changed, 529 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/62471/8
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Change subject: soc/mediatek/mt8186: Add GPIO driving functions
......................................................................
Patch Set 7:
(1 comment)
File src/soc/mediatek/common/include/soc/gpio_common.h:
https://review.coreboot.org/c/coreboot/+/62471/comment/ea8048dc_64f03fb6
PS7, Line 45: GPIO_DRV_ADV_1_MA = 3,
Use PA for picoampere instead of P for point(?)?
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Change subject: soc/mediatek/mt8186: Add GPIO driving functions
......................................................................
Patch Set 7:
(1 comment)
File src/soc/mediatek/common/include/soc/gpio_common.h:
https://review.coreboot.org/c/coreboot/+/62471/comment/f3b7b45e_a948b162
PS4, Line 31: };
> There are 8 stage for all mediatek SoCs, but they may have different drive strength. […]
I am still not fully convinced, but am too ignorant to hold this up.
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