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Change subject: soc/intel/denverton_ns: enable Denverton to use common PMC code
......................................................................
soc/intel/denverton_ns: enable Denverton to use common PMC code
Use Intel common SoC PMC code for Denverton refactor. By necessity,
this includes the SoC common SMBUS/TCO functionality as well.
Signed-off-by: Jeff Daly <jeffd(a)silicom-usa.com>
Change-Id: Id386cba1bd7dd236e292a3f6ce78a9cac6d7b447
---
M src/soc/intel/denverton_ns/Kconfig
M src/soc/intel/denverton_ns/Makefile.inc
M src/soc/intel/denverton_ns/acpi.c
M src/soc/intel/denverton_ns/chip.h
A src/soc/intel/denverton_ns/include/soc/gpe.h
M src/soc/intel/denverton_ns/include/soc/smbus.h
M src/soc/intel/denverton_ns/include/soc/soc_util.h
M src/soc/intel/denverton_ns/romstage.c
M src/soc/intel/denverton_ns/smihandler.c
M src/soc/intel/denverton_ns/smm.c
M src/soc/intel/denverton_ns/soc_util.c
11 files changed, 67 insertions(+), 61 deletions(-)
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Change subject: soc/intel/denverton_ns: enable Denverton to use common power limit code
......................................................................
soc/intel/denverton_ns: enable Denverton to use common power limit code
Use Intel common SoC power limit code for Denverton refactor
Signed-off-by: Jeff Daly <jeffd(a)silicom-usa.com>
Change-Id: Idffa1298f289add045e2d053d654dd38dc0a6bd5
---
M src/soc/intel/denverton_ns/Kconfig
M src/soc/intel/denverton_ns/chip.h
M src/soc/intel/denverton_ns/systemagent.c
3 files changed, 23 insertions(+), 15 deletions(-)
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Change subject: soc/intel/denverton_ns: enable Denverton to use common systemagent code
......................................................................
soc/intel/denverton_ns: enable Denverton to use common systemagent code
Use Intel common SoC systemagent code for Denverton refactor
Signed-off-by: Jeff Daly <jeffd(a)silicom-usa.com>
Change-Id: I39df1f0889c1c4ac6f2b3c25ccb7817e4492f446
---
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/denverton_ns/Kconfig
M src/soc/intel/denverton_ns/Makefile.inc
M src/soc/intel/denverton_ns/acpi.c
M src/soc/intel/denverton_ns/bootblock/bootblock.c
M src/soc/intel/denverton_ns/chip.h
M src/soc/intel/denverton_ns/include/soc/iomap.h
M src/soc/intel/denverton_ns/include/soc/nvs.h
M src/soc/intel/denverton_ns/include/soc/soc_util.h
M src/soc/intel/denverton_ns/include/soc/systemagent.h
D src/soc/intel/denverton_ns/memmap.c
M src/soc/intel/denverton_ns/soc_util.c
M src/soc/intel/denverton_ns/systemagent.c
13 files changed, 219 insertions(+), 544 deletions(-)
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Change subject: soc/intel/denverton_ns/chip.c: add soc_acpi_name function
......................................................................
soc/intel/denverton_ns/chip.c: add soc_acpi_name function
Intel common SoC code uses SoC-specific soc_acpi_name function to
generate ACPI tables, add this to Denverton
Signed-off-by: Jeff Daly <jeffd(a)silicom-usa.com>
Change-Id: I5f50733656ca7724caf8a6570bcb21f7b761c3ce
---
M src/soc/intel/denverton_ns/chip.c
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Change subject: soc/intel/denverton_ns: add common device function macros
......................................................................
soc/intel/denverton_ns: add common device function macros
Add device function macros for Denverton similar to other SoCs
Signed-off-by: Jeff Daly <jeffd(a)silicom-usa.com>
Change-Id: I75daaf4907515f80a10c003eb473bbe557a42acc
---
M src/soc/intel/denverton_ns/include/soc/pci_devs.h
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62496 )
Change subject: drivers/gfx/nvidia: Add Optimus driver based on Intel PCIe RTD3
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS1:
> so, we have two drivers for the same thing now, I guess? :/ CB:57034
Not sure if Tim was still able to work on that or not... so I had talked to him some and I was working on one as well... https://review.coreboot.org/c/coreboot/+/62381
We should really coordinate here. The ChromeOS device has different requirements for power sequencing (it is all driven by the PCH), so just a single "enable" GPIO won't cut it, hence why I left most of the power sequencing to the mainboard.
Also this really copies and pastes a lot from the pcie/rtd3 driver, I think we could probably do some refactoring to make this cleaner, instead of re-implementing the Intel PCIE RTD3 sequence in so many places.
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Hello Felix Singer, build bot (Jenkins), Martin Roth, Mariusz Szafrański, Suresh Bellampalli, Stefan Reinauer, Vanessa Eusebio, Angel Pons, Michal Motyl, Michael Niewöhner, Kyösti Mälkki, Patrick Rudolph,
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Change subject: util/ifdtool: Add support for Denverton Soc
......................................................................
util/ifdtool: Add support for Denverton Soc
TEST='ifdtool -p dnv coreboot.rom' and verify correct output
Signed-off-by: Jeff Daly <jeffd(a)silicom-usa.com>
Change-Id: I15939ce4672123f39a807d63c13ba7df98c57523
---
M src/soc/intel/denverton_ns/Kconfig
M util/ifdtool/ifdtool.c
M util/ifdtool/ifdtool.h
3 files changed, 77 insertions(+), 11 deletions(-)
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Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62355 )
Change subject: cpu/x86/smm,lib/cbmem_console: Enable CBMEMC when using DEBUG_SMI
......................................................................
Patch Set 4:
(2 comments)
File src/cpu/x86/smm/smm_module_loader.c:
https://review.coreboot.org/c/coreboot/+/62355/comment/d0f42cf8_34e9b8b5
PS3, Line 562: cbmemc = cbmem_entry_find(CBMEM_ID_CONSOLE);
> nit: wrap in `if (CONFIG_CONSOLE_CBMEM)`?
Done.
File src/lib/cbmem_console.c:
https://review.coreboot.org/c/coreboot/+/62355/comment/74f1d095_fa5b40c6
PS3, Line 93: if (cbmemc != NULL && cbmemc_size > 0)
> nit: init_console_ptr() already checks both of these
Yeah. I wanted to avoid making people go and trace `init_console_ptr`. But since you raised it, I'll remove it.
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I'd like you to reexamine a change. Please visit
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Change subject: cpu/x86/smm,lib/cbmem_console: Enable CBMEMC when using DEBUG_SMI
......................................................................
cpu/x86/smm,lib/cbmem_console: Enable CBMEMC when using DEBUG_SMI
This change will allow the SMI handler to write to the cbmem console
buffer. Normally SMIs can only be debugged using some kind of serial
port (UART). By storing the SMI logs into cbmem we can debug SMIs using
`cbmem -1`. Now that these logs are available to the OS we could also
verify there were no errors in the SMI handler.
Since SMM can write to all of DRAM, we can't trust any pointers
provided by cbmem after the OS has booted. For this reason we store the
cbmem console pointer as part of the SMM runtime parameters. The cbmem
console is implemented as a circular buffer so it will never write
outside of this area.
BUG=b:221231786
TEST=Boot non-serial FW with DEBUG_SMI and verified SMI messages are
visible when running `cbmem -1`. Perform a suspend/resume cycle and
verify new SMI events are written to the cbmem console log.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: Ia1e310a12ca2f54210ccfaee58807cb808cfff79
---
M src/cpu/x86/smm/smm_module_handler.c
M src/cpu/x86/smm/smm_module_loader.c
M src/include/console/cbmem_console.h
M src/include/cpu/x86/smm.h
M src/lib/Makefile.inc
M src/lib/cbmem_console.c
6 files changed, 36 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/62355/4
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