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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/denverton_ns: add common device function macros
......................................................................
soc/intel/denverton_ns: add common device function macros
Add device function macros for Denverton similar to other SoCs
Signed-off-by: Jeff Daly <jeffd(a)silicom-usa.com>
Change-Id: I75daaf4907515f80a10c003eb473bbe557a42acc
---
M src/soc/intel/denverton_ns/include/soc/pci_devs.h
1 file changed, 101 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/60990/10
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Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62496 )
Change subject: drivers/gfx/nvidia: Add Optimus driver based on Intel PCIe RTD3
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS1:
> so, we have two drivers for the same thing now, I guess? :/ CB:57034
Not sure if Tim was still able to work on that or not... so I had talked to him some and I was working on one as well... https://review.coreboot.org/c/coreboot/+/62381
We should really coordinate here. The ChromeOS device has different requirements for power sequencing (it is all driven by the PCH), so just a single "enable" GPIO won't cut it, hence why I left most of the power sequencing to the mainboard.
Also this really copies and pastes a lot from the pcie/rtd3 driver, I think we could probably do some refactoring to make this cleaner, instead of re-implementing the Intel PCIE RTD3 sequence in so many places.
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Hello Felix Singer, build bot (Jenkins), Martin Roth, Mariusz Szafrański, Suresh Bellampalli, Stefan Reinauer, Vanessa Eusebio, Angel Pons, Michal Motyl, Michael Niewöhner, Kyösti Mälkki, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
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Change subject: util/ifdtool: Add support for Denverton Soc
......................................................................
util/ifdtool: Add support for Denverton Soc
TEST='ifdtool -p dnv coreboot.rom' and verify correct output
Signed-off-by: Jeff Daly <jeffd(a)silicom-usa.com>
Change-Id: I15939ce4672123f39a807d63c13ba7df98c57523
---
M src/soc/intel/denverton_ns/Kconfig
M util/ifdtool/ifdtool.c
M util/ifdtool/ifdtool.h
3 files changed, 77 insertions(+), 11 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/60830/14
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Change subject: cpu/x86/smm,lib/cbmem_console: Enable CBMEMC when using DEBUG_SMI
......................................................................
cpu/x86/smm,lib/cbmem_console: Enable CBMEMC when using DEBUG_SMI
This change will allow the SMI handler to write to the cbmem console
buffer. Normally SMIs can only be debugged using some kind of serial
port (UART). By storing the SMI logs into cbmem we can debug SMIs using
`cbmem -1`. Now that these logs are available to the OS we could also
verify there were no errors in the SMI handler.
Since SMM can write to all of DRAM, we can't trust any pointers
provided by cbmem after the OS has booted. For this reason we store the
cbmem console pointer as part of the SMM runtime parameters. The cbmem
console is implemented as a circular buffer so it will never write
outside of this area.
BUG=b:221231786
TEST=Boot non-serial FW with DEBUG_SMI and verified SMI messages are
visible when running `cbmem -1`. Perform a suspend/resume cycle and
verify new SMI events are written to the cbmem console log.
Signed-off-by: Raul E Rangel <rrangel(a)chromium.org>
Change-Id: Ia1e310a12ca2f54210ccfaee58807cb808cfff79
---
M src/cpu/x86/smm/smm_module_handler.c
M src/cpu/x86/smm/smm_module_loader.c
M src/include/console/cbmem_console.h
M src/include/cpu/x86/smm.h
M src/lib/Makefile.inc
M src/lib/cbmem_console.c
6 files changed, 36 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/62355/4
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Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62355 )
Change subject: cpu/x86/smm,lib/cbmem_console: Enable CBMEMC when using DEBUG_SMI
......................................................................
Patch Set 4:
(2 comments)
File src/cpu/x86/smm/smm_module_loader.c:
https://review.coreboot.org/c/coreboot/+/62355/comment/d0f42cf8_34e9b8b5
PS3, Line 562: cbmemc = cbmem_entry_find(CBMEM_ID_CONSOLE);
> nit: wrap in `if (CONFIG_CONSOLE_CBMEM)`?
Done.
File src/lib/cbmem_console.c:
https://review.coreboot.org/c/coreboot/+/62355/comment/74f1d095_fa5b40c6
PS3, Line 93: if (cbmemc != NULL && cbmemc_size > 0)
> nit: init_console_ptr() already checks both of these
Yeah. I wanted to avoid making people go and trace `init_console_ptr`. But since you raised it, I'll remove it.
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Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62566 )
Change subject: intel/block/cpu: Keep flash region cached until the payload is loaded
......................................................................
intel/block/cpu: Keep flash region cached until the payload is loaded
Since FSP version 2.1 EFI_MP_SERVICES_PPI can be used to bring up all
the APs. For some SOCs it is mandatory that MP init is done by FSP
in order to have the full features enabled (e.g. Elkhart Lake or Alder
Lake). If the MP init is done by FSP, early MTRR setup is done by FSP,
too. Later in the boot flow, in BS_WRITE_TABLES exit, the MTRR setup is
re-configured by coreboot native code based on the registered resources.
This is done before payload is loaded. Now, in this scenario, the SPI
flash linear address range is not registered as a resource (since the
common SPI driver in src/soc/intel/common/block/spi is shared across
multiple SPI controllers and therefore cannot distinguish where the
flash is actually located at). This in turn leads to an uncached flash
range when coreboot re-configures the MTRRs. The result of this chain is
that loading the payload from flash takes much longer now (on mc_ehl1 it
takes ~12 seconds for 4.5 MB).
This patch adds a call to 'fast_spi_cache_bios_region()' right after the
MTRR setup has been performed by coreboot. With this call a temporary
MTRR region will be added that covers the flash range which will
accelerate the payload loading a lot (on mc_ehl1 now to ~4 seconds).
The call to 'fast_spi_cache_bios_region()' has to be done after MTRR
setup as otherwise there will be no free variable MTRR slot available
due to the missing initialization of the MTRR structure.
Here is the timestamp portion showing the payload load time as a
comparison between current upstream and the patched version:
upstream:
90:starting to load payload 1,072,459 (1,802)
958:calling FspNotify(ReadyToBoot) 12,818,079 (11,745,619)
with this patch:
90:starting to load payload 1,072,663 (2,627)
958:calling FspNotify(ReadyToBoot) 5,299,535 (4,226,871)
Change-Id: If19beaefc8fd3bbbe4b181820993abcd882bbbe1
Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com>
---
M src/soc/intel/common/block/cpu/mp_init.c
1 file changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/62566/1
diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c
index 8f220a8..eb69489 100644
--- a/src/soc/intel/common/block/cpu/mp_init.c
+++ b/src/soc/intel/common/block/cpu/mp_init.c
@@ -160,6 +160,9 @@
{
if (mp_run_on_all_cpus(&wrapper_x86_setup_mtrrs, NULL) != CB_SUCCESS)
printk(BIOS_ERR, "MTRR programming failure\n");
+ /* Make sure SPI flash region stays cached to load the payload fast. */
+ if (CONFIG(MP_SERVICES_PPI) && CONFIG(SOC_INTEL_COMMON_BLOCK_FAST_SPI))
+ fast_spi_cache_bios_region();
x86_mtrr_check();
}
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62514 )
Change subject: ec/starlabs/merlin: Don't report a battery capacity higher than design capacity
......................................................................
ec/starlabs/merlin: Don't report a battery capacity higher than design capacity
If B1FC (Battery Full Capacity) is higher than B1DC (Battery Design
Capacity), only report the design capacity. This handles cases where
the battery calibration is incorrect, and the battery runs out before
the OS thinks it's empty.
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: Ib3e4769c809b69e0a237b5f043e6c41c12d53752
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62514
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/ec/starlabs/merlin/acpi/battery.asl
1 file changed, 3 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Angel Pons: Looks good to me, approved
diff --git a/src/ec/starlabs/merlin/acpi/battery.asl b/src/ec/starlabs/merlin/acpi/battery.asl
index abdcc5b..12aaa74 100644
--- a/src/ec/starlabs/merlin/acpi/battery.asl
+++ b/src/ec/starlabs/merlin/acpi/battery.asl
@@ -34,6 +34,9 @@
Method (_BIF, 0, Serialized)
{
BPKG[1] = B1DC
+ If (B1FC >= B1DC) {
+ B1FC = B1DC
+ }
BPKG[2] = B1FC
BPKG[4] = B1DV
If (B1FC)
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