Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62514 )
Change subject: ec/starlabs/merlin: Don't report a battery capacity higher than design capacity
......................................................................
ec/starlabs/merlin: Don't report a battery capacity higher than design capacity
If B1FC (Battery Full Capacity) is higher than B1DC (Battery Design
Capacity), only report the design capacity. This handles cases where
the battery calibration is incorrect, and the battery runs out before
the OS thinks it's empty.
Signed-off-by: Sean Rhodes <sean(a)starlabs.systems>
Change-Id: Ib3e4769c809b69e0a237b5f043e6c41c12d53752
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62514
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/ec/starlabs/merlin/acpi/battery.asl
1 file changed, 3 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Angel Pons: Looks good to me, approved
diff --git a/src/ec/starlabs/merlin/acpi/battery.asl b/src/ec/starlabs/merlin/acpi/battery.asl
index abdcc5b..12aaa74 100644
--- a/src/ec/starlabs/merlin/acpi/battery.asl
+++ b/src/ec/starlabs/merlin/acpi/battery.asl
@@ -34,6 +34,9 @@
Method (_BIF, 0, Serialized)
{
BPKG[1] = B1DC
+ If (B1FC >= B1DC) {
+ B1FC = B1DC
+ }
BPKG[2] = B1FC
BPKG[4] = B1DV
If (B1FC)
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Gerrit-Change-Id: Ib3e4769c809b69e0a237b5f043e6c41c12d53752
Gerrit-Change-Number: 62514
Gerrit-PatchSet: 3
Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems>
Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60968 )
Change subject: soc/amd/common/block/psp: Add platform secure boot support
......................................................................
Patch Set 14:
(1 comment)
File src/soc/amd/common/block/psp/Kconfig:
https://review.coreboot.org/c/coreboot/+/60968/comment/4f5bceca_6c420a07
PS13, Line 48: bool "Platform secure boot enable"
> Yes, it requires BIOS image to be signed and also "Platform secure boot enable" option to be selecte […]
ran a quick test and only user-visible options can be selected via the build's .config file, so this needs to be user-visible, since the default needs to be n, but it also needs to be possible to switch this on via the .config
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Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62563 )
Change subject: soc/mediatek/mt8186: Modify internal capid to 0xE0
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62563/comment/0aa42138_2c62ceb7
PS1, Line 9: Request from Google hardware team:
: We cannot disable the internal cap.
> since this is 'mt8186' instead of 'corsola' (board), we should not say request from google hw team. […]
Done
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Hello Hung-Te Lin,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/62563
to look at the new patch set (#2).
Change subject: soc/mediatek/mt8186: Modify internal capid to 0xE0
......................................................................
soc/mediatek/mt8186: Modify internal capid to 0xE0
The mainboard may not be able to disable the internal cap, so we want
to set 0xe0 for all boards to minimize the internal cap. And a
mainboard implementation may choose XTAL with higher cload if the
frequency requirement meets, and the total capacitance can be tuned
externally for different boards.
BUG=b:218439447
TEST=set capid to 0xe0.
Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com>
Change-Id: I2139e6b3456d7a50e3cdc8fc606e5f6ea3406044
---
M src/soc/mediatek/mt8186/rtc.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/62563/2
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Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62563 )
Change subject: soc/mediatek/mt8186: Modify internal capid to 0xE0
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/62563/comment/11ec94aa_6b103493
PS1, Line 9: Request from Google hardware team:
: We cannot disable the internal cap.
since this is 'mt8186' instead of 'corsola' (board), we should not say request from google hw team. instead, you can say
The mainboard may not be able to disable the internal cap,
so we want to set 0xe0 for all boards to minimize the internal
cap. And a mainboard implementation may choose XTAL with higher
cload if the frequency requirement meets, and the total
capacitance can be tuned externally for different boards.
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