coreboot-gerrit March 2022

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Change in coreboot[master]: soc/mediatek/mt8186: Add GPIO driving functions
by Yu-Ping Wu (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Paul Menzel. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62471 ) Change subject: soc/mediatek/mt8186: Add GPIO driving functions ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62471 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d987f28be98b515fa5c542222bda08bea1d5118 Gerrit-Change-Number: 62471 Gerrit-PatchSet: 8 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 03 Mar 2022 14:37:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: intel/block/cpu: Keep flash region cached until the payload is loaded
by Werner Zeh (Code Review) 03 Mar '22

03 Mar '22

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62566 ) Change subject: intel/block/cpu: Keep flash region cached until the payload is loaded ...................................................................... intel/block/cpu: Keep flash region cached until the payload is loaded Since FSP version 2.1 EFI_MP_SERVICES_PPI can be used to bring up all the APs. For some SOCs it is mandatory that MP init is done by FSP in order to have the full features enabled (e.g. Elkhart Lake or Alder Lake). If the MP init is done by FSP, early MTRR setup is done by FSP, too. Later in the boot flow, in BS_WRITE_TABLES exit, the MTRR setup is re-configured by coreboot native code based on the registered resources. This is done before payload is loaded. Now, in this scenario, the SPI flash linear address range is not registered as a resource (since the common SPI driver in src/soc/intel/common/block/spi is shared across multiple SPI controllers and therefore cannot distinguish where the flash is actually located at). This in turn leads to an uncached flash range when coreboot re-configures the MTRRs. The result of this chain is that loading the payload from flash takes much longer now (on mc_ehl1 it takes ~12 seconds for 4.5 MB). This patch adds a call to 'fast_spi_cache_bios_region()' right after the MTRR setup has been performed by coreboot. With this call a temporary MTRR region will be added that covers the flash range which will accelerate the payload loading a lot (on mc_ehl1 now to ~4 seconds). The call to 'fast_spi_cache_bios_region()' has to be done after MTRR setup as otherwise there will be no free variable MTRR slot available due to the missing initialization of the MTRR structure. Here is the timestamp portion showing the payload load time as a comparison between current upstream and the patched version: upstream: 90:starting to load payload 1,072,459 (1,802) 958:calling FspNotify(ReadyToBoot) 12,818,079 (11,745,619) with this patch: 90:starting to load payload 1,072,663 (2,627) 958:calling FspNotify(ReadyToBoot) 5,299,535 (4,226,871) Change-Id: If19beaefc8fd3bbbe4b181820993abcd882bbbe1 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/common/block/cpu/mp_init.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/62566/1 diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 8f220a8..eb69489 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -160,6 +160,9 @@ { if (mp_run_on_all_cpus(&wrapper_x86_setup_mtrrs, NULL) != CB_SUCCESS) printk(BIOS_ERR, "MTRR programming failure\n"); + /* Make sure SPI flash region stays cached to load the payload fast. */ + if (CONFIG(MP_SERVICES_PPI) && CONFIG(SOC_INTEL_COMMON_BLOCK_FAST_SPI)) + fast_spi_cache_bios_region(); x86_mtrr_check(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/62566 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If19beaefc8fd3bbbe4b181820993abcd882bbbe1 Gerrit-Change-Number: 62566 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: ec/starlabs/merlin: Don't report a battery capacity higher than desig...
by Felix Held (Code Review) 03 Mar '22

03 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62514 ) Change subject: ec/starlabs/merlin: Don't report a battery capacity higher than design capacity ...................................................................... ec/starlabs/merlin: Don't report a battery capacity higher than design capacity If B1FC (Battery Full Capacity) is higher than B1DC (Battery Design Capacity), only report the design capacity. This handles cases where the battery calibration is incorrect, and the battery runs out before the OS thinks it's empty. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: Ib3e4769c809b69e0a237b5f043e6c41c12d53752 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62514 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/ec/starlabs/merlin/acpi/battery.asl 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved diff --git a/src/ec/starlabs/merlin/acpi/battery.asl b/src/ec/starlabs/merlin/acpi/battery.asl index abdcc5b..12aaa74 100644 --- a/src/ec/starlabs/merlin/acpi/battery.asl +++ b/src/ec/starlabs/merlin/acpi/battery.asl @@ -34,6 +34,9 @@ Method (_BIF, 0, Serialized) { BPKG[1] = B1DC + If (B1FC >= B1DC) { + B1FC = B1DC + } BPKG[2] = B1FC BPKG[4] = B1DV If (B1FC) -- To view, visit https://review.coreboot.org/c/coreboot/+/62514 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib3e4769c809b69e0a237b5f043e6c41c12d53752 Gerrit-Change-Number: 62514 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Andy Pont <andy.pont(a)sdcsystems.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/brya/var/vell: Change to ELAN touchpanel driver
by Felix Held (Code Review) 03 Mar '22

03 Mar '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/62317 ) Change subject: mb/google/brya/var/vell: Change to ELAN touchpanel driver ...................................................................... mb/google/brya/var/vell: Change to ELAN touchpanel driver Disabled G2touch driver and add ELAN touchpanel driver for vell. Due to incorrect BIOS setting, touch screen IC FW can't update and work. According to ELAN's recommendations, we coreect the ELAN2513 driver's setting and change I2C address to 0x10 BUG=b:221340736 TEST=emerge-brya coreboot and can flash touch screen FW Change-Id: I22f04fa21b542e21e88c46547779cfb55beb5c12 Signed-off-by: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/62317 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Reviewed-by: YH Lin <yueherngl(a)google.com> --- M src/mainboard/google/brya/variants/vell/overridetree.cb 1 file changed, 9 insertions(+), 24 deletions(-) Approvals: build bot (Jenkins): Verified YH Lin: Looks good to me, but someone else must approve EricR Lai: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/vell/overridetree.cb b/src/mainboard/google/brya/variants/vell/overridetree.cb index 690e266..1562482 100644 --- a/src/mainboard/google/brya/variants/vell/overridetree.cb +++ b/src/mainboard/google/brya/variants/vell/overridetree.cb @@ -208,40 +208,25 @@ end end device ref i2c3 on - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" - register "probed" = "1" - register "reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" - register "reset_delay_ms" = "100" - register "reset_off_delay_ms" = "5" - register "enable_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" - register "enable_delay_ms" = "10" - register "enable_off_delay_ms" = "1" - register "stop_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" - register "has_power_resource" = "1" - register "disable_gpio_export_in_crs" = "1" - device i2c 10 on end - end chip drivers/i2c/hid - register "generic.hid" = ""GTCH7503"" - register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.hid" = ""ELAN2513"" + register "generic.desc" = ""ELAN Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" - register "generic.reset_delay_ms" = "50" + register "generic.reset_delay_ms" = "200" + register "generic.reset_off_delay_ms" = "1" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" - register "generic.enable_delay_ms" = "1" + register "generic.enable_delay_ms" = "6" + register "generic.stop_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" + register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" register "generic.disable_gpio_export_in_crs" = "1" register "hid_desc_reg_offset" = "0x01" - device i2c 40 on end + device i2c 0x10 on end end end device ref i2c2 on -- To view, visit https://review.coreboot.org/c/coreboot/+/62317 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22f04fa21b542e21e88c46547779cfb55beb5c12 Gerrit-Change-Number: 62317 Gerrit-PatchSet: 9 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <coreboot.test(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com> Gerrit-CC: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/block/psp: Add platform secure boot support
by Felix Held (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: Jason Glenesk, Raul Rangel, ritul guru, Marshall Dawson, Paul Menzel, Angel Pons, Aamir Bohra, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60968 ) Change subject: soc/amd/common/block/psp: Add platform secure boot support ...................................................................... Patch Set 14: (1 comment) File src/soc/amd/common/block/psp/Kconfig: https://review.coreboot.org/c/coreboot/+/60968/comment/4f5bceca_6c420a07 PS13, Line 48: bool "Platform secure boot enable" > Yes, it requires BIOS image to be signed and also "Platform secure boot enable" option to be selecte […] ran a quick test and only user-visible options can be selected via the build's .config file, so this needs to be user-visible, since the default needs to be n, but it also needs to be possible to switch this on via the .config -- To view, visit https://review.coreboot.org/c/coreboot/+/60968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30aac29a22a5800d5995a78c50fdecd660a3d4eb Gerrit-Change-Number: 60968 Gerrit-PatchSet: 14 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Mar 2022 14:04:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: ritul guru <ritul.bits(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "mb/google/brya/var/taeko: Fix PLD group order (W/A)"
by Kevin Chang (Code Review) 03 Mar '22

03 Mar '22

Kevin Chang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62565 ) Change subject: Revert "mb/google/brya/var/taeko: Fix PLD group order (W/A)" ...................................................................... Revert "mb/google/brya/var/taeko: Fix PLD group order (W/A)" This revert commit acb17fec34a609c5b674ad0d2af04d47800530e2. This issue fix by OS that revert core boot work around. BUG=b:210497855 BRANCH=none TEST=build coreboot and boot into OS. Signed-off-by: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Change-Id: Ic836e0cf53c2f9d30bd12851be285d864b2256b8 --- M src/mainboard/google/brya/variants/taeko/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/62565/1 diff --git a/src/mainboard/google/brya/variants/taeko/overridetree.cb b/src/mainboard/google/brya/variants/taeko/overridetree.cb index 760ffa6..ac83e58 100644 --- a/src/mainboard/google/brya/variants/taeko/overridetree.cb +++ b/src/mainboard/google/brya/variants/taeko/overridetree.cb @@ -466,7 +466,7 @@ register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))" device ref tcss_usb3_port3 on probe DB_USB DB_USB3_NO_A probe DB_USB DB_USB3_1C_1A @@ -489,7 +489,7 @@ register "desc" = ""USB2 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))" device ref usb2_port3 on probe DB_USB DB_USB3_NO_A probe DB_USB DB_USB3_1C_1A -- To view, visit https://review.coreboot.org/c/coreboot/+/62565 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic836e0cf53c2f9d30bd12851be285d864b2256b8 Gerrit-Change-Number: 62565 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chang <kevin.chang(a)lcfc.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/brya/var/redrix{4es}: Correct the unused USB2/TCSS port
by Chen Wisley (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: Wisley Chen. Hello Wisley Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/62564 to review the following change. Change subject: mb/google/brya/var/redrix{4es}: Correct the unused USB2/TCSS port ...................................................................... mb/google/brya/var/redrix{4es}: Correct the unused USB2/TCSS port BT didn't work due to incorrectly disable usb port#9 for BT. The patch includes the changes. 1. enable USB2 port#9 for BT 2. disable TCSS PCIe port1 BUG=b:217238553 TEST=build and verfied BT work Change-Id: Ie94ef847fc130019f1e06983fc5039f1f564cd3a Signed-off-by: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/redrix/overridetree.cb M src/mainboard/google/brya/variants/redrix4es/overridetree.cb 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/62564/1 diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index 62a24ed..7fb10bb 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -43,7 +43,6 @@ register "usb2_ports[1]" = "USB2_PORT_EMPTY" register "usb2_ports[5]" = "USB2_PORT_EMPTY" - register "usb2_ports[9]" = "USB2_PORT_EMPTY" register "tcss_ports[1]" = "TCSS_PORT_EMPTY" # Intel Common SoC Config @@ -151,6 +150,7 @@ device generic 0 alias dptf_policy on end end end + device ref tbt_pcie_rp1 off end device ref ipu on chip drivers/intel/mipi_camera register "acpi_uid" = "0x50000" diff --git a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb index 5cb105d..f74df93 100644 --- a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb @@ -43,7 +43,6 @@ register "usb2_ports[1]" = "USB2_PORT_EMPTY" register "usb2_ports[5]" = "USB2_PORT_EMPTY" - register "usb2_ports[9]" = "USB2_PORT_EMPTY" register "tcss_ports[1]" = "TCSS_PORT_EMPTY" # Intel Common SoC Config @@ -137,6 +136,7 @@ device generic 0 alias dptf_policy on end end end + device ref tbt_pcie_rp1 off end device ref ipu on chip drivers/intel/mipi_camera register "acpi_uid" = "0x50000" -- To view, visit https://review.coreboot.org/c/coreboot/+/62564 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie94ef847fc130019f1e06983fc5039f1f564cd3a Gerrit-Change-Number: 62564 Gerrit-PatchSet: 1 Gerrit-Owner: Chen Wisley <wisley.chen(a)quantatw.com> Gerrit-Reviewer: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-Attention: Wisley Chen <wisley.chen(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8186: Modify internal capid to 0xE0
by Rex-BC Chen (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: Hung-Te Lin. Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62563 ) Change subject: soc/mediatek/mt8186: Modify internal capid to 0xE0 ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/62563/comment/0aa42138_2c62ceb7 PS1, Line 9: Request from Google hardware team: : We cannot disable the internal cap. > since this is 'mt8186' instead of 'corsola' (board), we should not say request from google hw team. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/62563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2139e6b3456d7a50e3cdc8fc606e5f6ea3406044 Gerrit-Change-Number: 62563 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Comment-Date: Thu, 03 Mar 2022 11:45:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Hung-Te Lin <hungte(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Modify internal capid to 0xE0
by Rex-BC Chen (Code Review) 03 Mar '22

03 Mar '22

Rex-BC Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/62563 ) Change subject: soc/mediatek/mt8186: Modify internal capid to 0xE0 ...................................................................... Patch Set 2: Code-Review-1 -- To view, visit https://review.coreboot.org/c/coreboot/+/62563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2139e6b3456d7a50e3cdc8fc606e5f6ea3406044 Gerrit-Change-Number: 62563 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Comment-Date: Thu, 03 Mar 2022 11:45:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8186: Modify internal capid to 0xE0
by Rex-BC Chen (Code Review) 03 Mar '22

03 Mar '22

Attention is currently required from: Rex-BC Chen. Hello Hung-Te Lin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/62563 to look at the new patch set (#2). Change subject: soc/mediatek/mt8186: Modify internal capid to 0xE0 ...................................................................... soc/mediatek/mt8186: Modify internal capid to 0xE0 The mainboard may not be able to disable the internal cap, so we want to set 0xe0 for all boards to minimize the internal cap. And a mainboard implementation may choose XTAL with higher cload if the frequency requirement meets, and the total capacitance can be tuned externally for different boards. BUG=b:218439447 TEST=set capid to 0xe0. Signed-off-by: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Change-Id: I2139e6b3456d7a50e3cdc8fc606e5f6ea3406044 --- M src/soc/mediatek/mt8186/rtc.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/62563/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/62563 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2139e6b3456d7a50e3cdc8fc606e5f6ea3406044 Gerrit-Change-Number: 62563 Gerrit-PatchSet: 2 Gerrit-Owner: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-Attention: Rex-BC Chen <rex-bc.chen(a)mediatek.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2022