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Change subject: console: Add loglevel marker codes to stored consoles
......................................................................
Patch Set 6: Code-Review+2
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Change subject: cpu/x86/smm: Improve smm stack setup
......................................................................
Patch Set 5: Code-Review+1
(1 comment)
File src/cpu/x86/smm/smm_module_loader.c:
https://review.coreboot.org/c/coreboot/+/58698/comment/6aac72b0_812576a1
PS5, Line 262: return 0;
Sorry maybe an out of topic question:
does it makes sense to use 'CB_SUCCESS' and 'CB_ERR' instead of return {0,-1} ?
(sorry again for out of topic question)
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Change subject: console: Add ANSI escape sequences for highlighting
......................................................................
Patch Set 5:
(1 comment)
File src/console/printk.c:
https://review.coreboot.org/c/coreboot/+/61307/comment/f5a9300a_3afe1ef7
PS5, Line 82: console_interactive_tx_byte
I think using `vtxprintf` would make this more maintainable.
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Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices
......................................................................
Patch Set 12:
(3 comments)
File src/soc/amd/cezanne/fch.c:
https://review.coreboot.org/c/coreboot/+/61259/comment/280dadae_98e3f042
PS4, Line 183: tree. */
> This situation is something that happens normally at the moment. […]
Done
File src/soc/amd/cezanne/fch.c:
https://review.coreboot.org/c/coreboot/+/61259/comment/b0013e06_bf6ebf09
PS5, Line 169: if (gpp_child->enabled) {
> I believe a NULL check isn't needed here, but not completely sure.
Done
File src/soc/amd/cezanne/fch.c:
https://review.coreboot.org/c/coreboot/+/61259/comment/5217f8af_34e6ec55
PS6, Line 164: i
> there is no 1:1 mapping of the pcie gpp port numbers to the gpp clock request lines and gpp clock ou […]
Done
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Change subject: src/ec: Get rid of unnecessary blank line {before,after} brace
......................................................................
Patch Set 1:
(2 comments)
Patchset:
PS1:
Thx
File src/ec/google/chromeec/ec_commands.h:
PS1:
> This file is always synced directly from the Chromium OS EC repo (minus the header/copyright notice […]
Ack
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Change subject: console: Add loglevel prefix to interactive consoles
......................................................................
Patch Set 5:
(2 comments)
File src/console/printk.c:
https://review.coreboot.org/c/coreboot/+/61306/comment/44cc9c57_66842729
PS5, Line 80: console_interactive_tx_byte
Can we use `vtxprintf(interactive_putchar, BIOS_LOG_PREFIX_PATTERN, &bios_log_prefix[state.level], NULL)`?
https://review.coreboot.org/c/coreboot/+/61306/comment/e862dc60_d338c432
PS5, Line 85:
nit: Do we need two spaces?
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Rob Barnes, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61259
to look at the new patch set (#12).
Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices
......................................................................
soc/amd/cezanne: Turn off gpp clock request for disabled devices
The current behavior does not actually check if a device is present before enabling the corresponding gpp_clkx_clock_request_mapping bits which may cause issues with L1SS. This change sets the corresponding gpp_clkx_clock_request_mapping to off if the corresponding device is disabled.
BUG=b:202252869
TEST=Checked that value of GPP_CLK_CNTRL matched the expected value when devices are enabled/disabled
FIXED=b:202252869
Signed-off-by: Robert Zieba <robertzieba(a)google.com>
Change-Id: I77389372c60bdec572622a3b49484d4789fd4e4c
---
M src/mainboard/google/guybrush/Makefile.inc
M src/soc/amd/cezanne/Makefile.inc
M src/soc/amd/cezanne/chip.h
M src/soc/amd/cezanne/fch.c
A src/soc/amd/cezanne/platform_descriptors.c
5 files changed, 94 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/61259/12
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Change subject: console: Pass log_state to vtxprintf()
......................................................................
Patch Set 1: Code-Review+2
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Change subject: soc/amd/cezanne: Turn off gpp clock request for disabled devices
......................................................................
Patch Set 11:
(9 comments)
File src/soc/amd/cezanne/platform_descriptors.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139892):
https://review.coreboot.org/c/coreboot/+/61259/comment/67327aba_09ae0c96
PS11, Line 9: *dxio_descs = NULL;
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139892):
https://review.coreboot.org/c/coreboot/+/61259/comment/2894711b_f8e75767
PS11, Line 9: *dxio_descs = NULL;
please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139892):
https://review.coreboot.org/c/coreboot/+/61259/comment/684290e0_0fbf3517
PS11, Line 10: *dxio_num = 0;
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139892):
https://review.coreboot.org/c/coreboot/+/61259/comment/a588c817_60fb652f
PS11, Line 10: *dxio_num = 0;
please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139892):
https://review.coreboot.org/c/coreboot/+/61259/comment/741be26c_0dcfb80f
PS11, Line 11: *ddi_descs = NULL;
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139892):
https://review.coreboot.org/c/coreboot/+/61259/comment/d58cc9c4_d9ae1097
PS11, Line 11: *ddi_descs = NULL;
please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139892):
https://review.coreboot.org/c/coreboot/+/61259/comment/01a56a8d_701a6f1c
PS11, Line 12: *ddi_num = 0;
code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139892):
https://review.coreboot.org/c/coreboot/+/61259/comment/570e624a_9452fab7
PS11, Line 12: *ddi_num = 0;
please, no spaces at the start of a line
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139892):
https://review.coreboot.org/c/coreboot/+/61259/comment/724d39a5_592ab918
PS11, Line 13: }
adding a line without newline at end of file
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Change subject: soc/intel/tigerlake: Don't override lpc_io_setup_comm_a_b()
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Unless I'm missing something, I don't think it will override lpc_io_setup...
lpc_enable_fixed_io_ranges() ORs in the bits you selected to LPC_IO_ENABLEs, therefore it shouldn't disable anything that lpc_io_setup... would have done.
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