coreboot-gerrit February 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: amdfwtool: Add SPL support
by Raul Rangel (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Bao Zheng, Zheng Bao. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61426 ) Change subject: amdfwtool: Add SPL support ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61426 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4665f2372ccd599ab835c8784da08cde5558a795 Gerrit-Change-Number: 61426 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Avinash Alevoor Gerrit-Reviewer: Mohan Viswanathan Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Thu, 03 Feb 2022 16:34:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/cezanne: Add the fw SPL to fw.cfg
by Raul Rangel (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Bao Zheng, Marshall Dawson, Zheng Bao, Felix Held. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61425 ) Change subject: soc/amd/cezanne: Add the fw SPL to fw.cfg ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0aa456b8b4eec506fbb319293f0903b293325cb0 Gerrit-Change-Number: 61425 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Avinash Alevoor Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Mohan Viswanathan Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Feb 2022 16:33:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/guybrush: Add the fw SPL to amdfw.cfg
by Raul Rangel (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Bao Zheng, Name of user not set #1004133, Zheng Bao. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61445 ) Change subject: mb/google/guybrush: Add the fw SPL to amdfw.cfg ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/mainboard/google/guybrush/variants/baseboard/amdfw.cfg: https://review.coreboot.org/c/coreboot/+/61445/comment/3ceb6262_ef69aafc PS1, Line 27: TypeId0x55_SplTable_Prod_CZN_Chrome > Not sure this is required upstream. […] I think we should push it upstream at some point. Ideally we should be able to build functional firmware from the upstream repos. -- To view, visit https://review.coreboot.org/c/coreboot/+/61445 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I268a92c9916b261fbc899ebb72f75f7a3f12c441 Gerrit-Change-Number: 61445 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Avinash Alevoor Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-CC: Name of user not set #1004133 Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rob Barnes <robbarnes(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Name of user not set #1004133 Gerrit-Attention: Zheng Bao Gerrit-Comment-Date: Thu, 03 Feb 2022 16:33:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Comment-In-Reply-To: Name of user not set #1004133 Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/psp: add PSP command
by Mohan Viswanathan (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Name of user not set #1004133, Al Hirani, Avinash Alevoor, Rob Barnes, Fred Reitberger, Felix Held. Mohan Viswanathan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61462 ) Change subject: soc/amd/common/block/psp: add PSP command ...................................................................... Patch Set 6: Code-Review-1 (1 comment) File src/soc/amd/common/block/psp/psp_def.h: https://review.coreboot.org/c/coreboot/+/61462/comment/2187e44f_503e44cf PS6, Line 30: #define CORE_2_PSP_MSG_38_FUSE_SPL BIT(3) This should be BIT(12). PSP sets bit 12 to indicate fusing is required. -- To view, visit https://review.coreboot.org/c/coreboot/+/61462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If0575356a7c6172e2e0f2eaf9d1a6706468fe92d Gerrit-Change-Number: 61462 Gerrit-PatchSet: 6 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Al Hirani <al.hirani13(a)gmail.com> Gerrit-Reviewer: Avinash Alevoor Gerrit-Reviewer: Fred Reitberger <fred.reitberger(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Mohan Viswanathan Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Name of user not set #1004133 Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Name of user not set #1004133 Gerrit-Attention: Al Hirani <al.hirani13(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Avinash Alevoor Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Fred Reitberger <fred.reitberger(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Feb 2022 16:27:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/gimble: Disable PCIE RP 6 and TCSS Port 1
by Felix Held (Code Review) 03 Feb '22

03 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61266 ) Change subject: mb/google/brya/variants/gimble: Disable PCIE RP 6 and TCSS Port 1 ...................................................................... mb/google/brya/variants/gimble: Disable PCIE RP 6 and TCSS Port 1 Gimble does not use WWAN and TCP Port 1 according to the schematics. Hence disabling it. BUG=b:216533766 TEST=Boot to kernel and verify WWAN and TCSS Port 1 disabled Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> change-Id: I0e7ae72620da39fc18ff253c440d006e83c576f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61266 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/variants/gimble/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, but someone else must approve Tim Wawrzynczak: Looks good to me, approved Sridhar Siricilla: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb index 23071fe..408d380 100644 --- a/src/mainboard/google/brya/variants/gimble/overridetree.cb +++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb @@ -38,6 +38,7 @@ register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Type-A DB Port register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port + register "tcss_ports[1]" = "TCSS_PORT_EMPTY" # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | @@ -121,6 +122,7 @@ device generic 0 on end end end + device ref pcie_rp6 off end device ref pcie_rp8 on chip soc/intel/common/block/pcie/rtd3 register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)" -- To view, visit https://review.coreboot.org/c/coreboot/+/61266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e7ae72620da39fc18ff253c440d006e83c576f3 Gerrit-Change-Number: 61266 Gerrit-PatchSet: 4 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane.chen(a)intel.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/prodrive/atlas: Configure PCIe device tree settings
by Felix Held (Code Review) 03 Feb '22

03 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61296 ) Change subject: mb/prodrive/atlas: Configure PCIe device tree settings ...................................................................... mb/prodrive/atlas: Configure PCIe device tree settings Add CPU & PCH PCIe configs and remove the unused devices. Configures per Atlas schematics v6. Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Change-Id: Id3145156c4ab3ec1c2d3eb6c433108a1b1cab9e8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61296 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/mainboard/prodrive/atlas/devicetree.cb 1 file changed, 36 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved diff --git a/src/mainboard/prodrive/atlas/devicetree.cb b/src/mainboard/prodrive/atlas/devicetree.cb index ccda650..7b094e4 100644 --- a/src/mainboard/prodrive/atlas/devicetree.cb +++ b/src/mainboard/prodrive/atlas/devicetree.cb @@ -41,29 +41,56 @@ [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + # Enable PCH PCIE RP 5, 6, 7, 8, 9, 10 using free running CLK (0x80) + # Clock source is shared hence marked as free running. + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED, + }" + register "pch_pcie_rp[PCH_RP(6)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED, + }" + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED, + }" + register "pch_pcie_rp[PCH_RP(8)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED, + }" + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED, + }" + register "pch_pcie_rp[PCH_RP(10)]" = "{ + .flags = PCIE_RP_CLK_SRC_UNUSED, + }" + register "pcie_clk_config_flag[0]" = "PCIE_CLK_FREE_RUNNING" + register "pcie_clk_config_flag[1]" = "PCIE_CLK_FREE_RUNNING" + + # Enable CPU PCIE RP 1, 2, 3 using using free running CLK (0x80) + # Clock source is shared hence marked as free running. + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED, + }" + register "cpu_pcie_rp[CPU_RP(2)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED, + }" + register "cpu_pcie_rp[CPU_RP(3)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED, + }" + device domain 0 on device ref pcie5 on end device ref igpu on end device ref dtt on end device ref pcie4_0 on end device ref pcie4_1 on end - device ref tbt_pcie_rp0 on end - device ref tbt_pcie_rp1 on end - device ref tbt_pcie_rp2 on end - device ref tbt_pcie_rp3 on end device ref crashlog off end device ref xhci on end - device ref cnvi_wifi on end device ref heci1 on end device ref sata on end - device ref pcie_rp1 on end - device ref pcie_rp3 on end # W/A to FSP issue - device ref pcie_rp4 on end # W/A to FSP issue device ref pcie_rp5 on end device ref pcie_rp6 on end device ref pcie_rp8 on end device ref pcie_rp9 on end - device ref pcie_rp11 on end + device ref pcie_rp10 on end device ref uart0 on end device ref uart1 on end device ref p2sb on end 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3145156c4ab3ec1c2d3eb6c433108a1b1cab9e8 Gerrit-Change-Number: 61296 Gerrit-PatchSet: 6 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/prodrive/atlas: Configure SATA, USB & HSIO device tree settings
by Felix Held (Code Review) 03 Feb '22

03 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61277 ) Change subject: mb/prodrive/atlas: Configure SATA, USB & HSIO device tree settings ...................................................................... mb/prodrive/atlas: Configure SATA, USB & HSIO device tree settings Configure SATA, USB & HSIO settings per Atlas schematics v6. Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Change-Id: I88c898d4b0c3bfeefbca71e13dad55e2c5fc846f Reviewed-on: https://review.coreboot.org/c/coreboot/+/61277 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/prodrive/atlas/devicetree.cb 1 file changed, 34 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/prodrive/atlas/devicetree.cb b/src/mainboard/prodrive/atlas/devicetree.cb index cf2e270..ccda650 100644 --- a/src/mainboard/prodrive/atlas/devicetree.cb +++ b/src/mainboard/prodrive/atlas/devicetree.cb @@ -8,6 +8,39 @@ register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_E" + # USB configuration + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" + register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[3]" = "USB2_PORT_MID(OC1)" + register "usb2_ports[4]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" + register "usb2_ports[6]" = "USB2_PORT_MID(OC3)" + register "usb2_ports[7]" = "USB2_PORT_MID(OC3)" + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)" + + register "SataSalpSupport" = "1" + + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + }" + + register "SataPortsDevSlp" = "{ + [0] = 1, + [1] = 1, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoPci, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + device domain 0 on device ref pcie5 on end device ref igpu on end @@ -19,18 +52,10 @@ device ref tbt_pcie_rp2 on end device ref tbt_pcie_rp3 on end device ref crashlog off end - device ref tcss_xhci on end - device ref tcss_dma0 on end - device ref tcss_dma1 on end device ref xhci on end device ref cnvi_wifi on end - device ref i2c0 on end - device ref i2c1 on end - device ref i2c2 on end - device ref i2c3 on end device ref heci1 on end device ref sata on end - device ref i2c5 on end device ref pcie_rp1 on end device ref pcie_rp3 on end # W/A to FSP issue device ref pcie_rp4 on end # W/A to FSP issue @@ -40,7 +65,7 @@ device ref pcie_rp9 on end device ref pcie_rp11 on end device ref uart0 on end - device ref gspi0 on end + device ref uart1 on end device ref p2sb on end device ref hda on end device ref smbus on end 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61277 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88c898d4b0c3bfeefbca71e13dad55e2c5fc846f Gerrit-Change-Number: 61277 Gerrit-PatchSet: 5 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: console: Add loglevel prefix to interactive consoles
by Raul Rangel (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Nico Huber, Patrick Georgi, Julius Werner, Kyösti Mälkki. Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61306 ) Change subject: console: Add loglevel prefix to interactive consoles ...................................................................... Patch Set 5: (1 comment) File src/console/printk.c: https://review.coreboot.org/c/coreboot/+/61306/comment/f980eb10_851515ee PS5, Line 80: console_interactive_tx_byte > Can we use `vtxprintf(interactive_putchar, BIOS_LOG_PREFIX_PATTERN, &bios_log_prefix[state. […] Might be cleaner to add a `static interactive_printk(fmt, args)`. Then you can use the format specifiers for the styling as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/61306 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic83413475400821f8097ef1819a293ee8926bb0b Gerrit-Change-Number: 61306 Gerrit-PatchSet: 5 Gerrit-Owner: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Feb 2022 16:23:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: Documentation/releases: Add 4.17 release notes template
by Martin Roth (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Jason Glenesk, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61573 ) Change subject: Documentation/releases: Add 4.17 release notes template ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61573 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iffb95257fa99f3276f851507a0c9e4583c47bacc Gerrit-Change-Number: 61573 Gerrit-PatchSet: 2 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 03 Feb 2022 16:21:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/mp_init.c: Rename num_concurrent_stacks
by HAOUAS Elyes (Code Review) 03 Feb '22

03 Feb '22

Attention is currently required from: Angel Pons, Arthur Heymans, Kyösti Mälkki. HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58699 ) Change subject: cpu/x86/mp_init.c: Rename num_concurrent_stacks ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/58699 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2156136894eeda4a29e8e694480abe06da62959 Gerrit-Change-Number: 58699 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 03 Feb 2022 16:18:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit February 2022