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Mohan Viswanathan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61462 )
Change subject: soc/amd/common/block/psp: add PSP command
......................................................................
Patch Set 6: Code-Review-1
(1 comment)
File src/soc/amd/common/block/psp/psp_def.h:
https://review.coreboot.org/c/coreboot/+/61462/comment/2187e44f_503e44cf
PS6, Line 30: #define CORE_2_PSP_MSG_38_FUSE_SPL BIT(3)
This should be BIT(12). PSP sets bit 12 to indicate fusing is required.
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61266 )
Change subject: mb/google/brya/variants/gimble: Disable PCIE RP 6 and TCSS Port 1
......................................................................
mb/google/brya/variants/gimble: Disable PCIE RP 6 and TCSS Port 1
Gimble does not use WWAN and TCP Port 1 according to the schematics.
Hence disabling it.
BUG=b:216533766
TEST=Boot to kernel and verify WWAN and TCSS Port 1 disabled
Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com>
change-Id: I0e7ae72620da39fc18ff253c440d006e83c576f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61266
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com>
---
M src/mainboard/google/brya/variants/gimble/overridetree.cb
1 file changed, 2 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Nick Vaccaro: Looks good to me, but someone else must approve
Tim Wawrzynczak: Looks good to me, approved
Sridhar Siricilla: Looks good to me, but someone else must approve
diff --git a/src/mainboard/google/brya/variants/gimble/overridetree.cb b/src/mainboard/google/brya/variants/gimble/overridetree.cb
index 23071fe..408d380 100644
--- a/src/mainboard/google/brya/variants/gimble/overridetree.cb
+++ b/src/mainboard/google/brya/variants/gimble/overridetree.cb
@@ -38,6 +38,7 @@
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Type-A DB Port
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type A MLB port
+ register "tcss_ports[1]" = "TCSS_PORT_EMPTY"
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
@@ -121,6 +122,7 @@
device generic 0 on end
end
end
+ device ref pcie_rp6 off end
device ref pcie_rp8 on
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H13)"
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61296 )
Change subject: mb/prodrive/atlas: Configure PCIe device tree settings
......................................................................
mb/prodrive/atlas: Configure PCIe device tree settings
Add CPU & PCH PCIe configs and remove the unused devices.
Configures per Atlas schematics v6.
Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com>
Change-Id: Id3145156c4ab3ec1c2d3eb6c433108a1b1cab9e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61296
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
---
M src/mainboard/prodrive/atlas/devicetree.cb
1 file changed, 36 insertions(+), 9 deletions(-)
Approvals:
build bot (Jenkins): Verified
Paul Menzel: Looks good to me, but someone else must approve
Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/prodrive/atlas/devicetree.cb b/src/mainboard/prodrive/atlas/devicetree.cb
index ccda650..7b094e4 100644
--- a/src/mainboard/prodrive/atlas/devicetree.cb
+++ b/src/mainboard/prodrive/atlas/devicetree.cb
@@ -41,29 +41,56 @@
[PchSerialIoIndexUART2] = PchSerialIoDisabled,
}"
+ # Enable PCH PCIE RP 5, 6, 7, 8, 9, 10 using free running CLK (0x80)
+ # Clock source is shared hence marked as free running.
+ register "pch_pcie_rp[PCH_RP(5)]" = "{
+ .flags = PCIE_RP_CLK_SRC_UNUSED,
+ }"
+ register "pch_pcie_rp[PCH_RP(6)]" = "{
+ .flags = PCIE_RP_CLK_SRC_UNUSED,
+ }"
+ register "pch_pcie_rp[PCH_RP(7)]" = "{
+ .flags = PCIE_RP_CLK_SRC_UNUSED,
+ }"
+ register "pch_pcie_rp[PCH_RP(8)]" = "{
+ .flags = PCIE_RP_CLK_SRC_UNUSED,
+ }"
+ register "pch_pcie_rp[PCH_RP(9)]" = "{
+ .flags = PCIE_RP_CLK_SRC_UNUSED,
+ }"
+ register "pch_pcie_rp[PCH_RP(10)]" = "{
+ .flags = PCIE_RP_CLK_SRC_UNUSED,
+ }"
+ register "pcie_clk_config_flag[0]" = "PCIE_CLK_FREE_RUNNING"
+ register "pcie_clk_config_flag[1]" = "PCIE_CLK_FREE_RUNNING"
+
+ # Enable CPU PCIE RP 1, 2, 3 using using free running CLK (0x80)
+ # Clock source is shared hence marked as free running.
+ register "cpu_pcie_rp[CPU_RP(1)]" = "{
+ .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED,
+ }"
+ register "cpu_pcie_rp[CPU_RP(2)]" = "{
+ .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED,
+ }"
+ register "cpu_pcie_rp[CPU_RP(3)]" = "{
+ .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_SRC_UNUSED,
+ }"
+
device domain 0 on
device ref pcie5 on end
device ref igpu on end
device ref dtt on end
device ref pcie4_0 on end
device ref pcie4_1 on end
- device ref tbt_pcie_rp0 on end
- device ref tbt_pcie_rp1 on end
- device ref tbt_pcie_rp2 on end
- device ref tbt_pcie_rp3 on end
device ref crashlog off end
device ref xhci on end
- device ref cnvi_wifi on end
device ref heci1 on end
device ref sata on end
- device ref pcie_rp1 on end
- device ref pcie_rp3 on end # W/A to FSP issue
- device ref pcie_rp4 on end # W/A to FSP issue
device ref pcie_rp5 on end
device ref pcie_rp6 on end
device ref pcie_rp8 on end
device ref pcie_rp9 on end
- device ref pcie_rp11 on end
+ device ref pcie_rp10 on end
device ref uart0 on end
device ref uart1 on end
device ref p2sb on end
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61277 )
Change subject: mb/prodrive/atlas: Configure SATA, USB & HSIO device tree settings
......................................................................
mb/prodrive/atlas: Configure SATA, USB & HSIO device tree settings
Configure SATA, USB & HSIO settings per Atlas schematics v6.
Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com>
Change-Id: I88c898d4b0c3bfeefbca71e13dad55e2c5fc846f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61277
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Angel Pons <th3fanbus(a)gmail.com>
---
M src/mainboard/prodrive/atlas/devicetree.cb
1 file changed, 34 insertions(+), 9 deletions(-)
Approvals:
build bot (Jenkins): Verified
Angel Pons: Looks good to me, approved
diff --git a/src/mainboard/prodrive/atlas/devicetree.cb b/src/mainboard/prodrive/atlas/devicetree.cb
index cf2e270..ccda650 100644
--- a/src/mainboard/prodrive/atlas/devicetree.cb
+++ b/src/mainboard/prodrive/atlas/devicetree.cb
@@ -8,6 +8,39 @@
register "pmc_gpe0_dw1" = "GPP_D"
register "pmc_gpe0_dw2" = "GPP_E"
+ # USB configuration
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC1)"
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC1)"
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC2)"
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC2)"
+ register "usb2_ports[6]" = "USB2_PORT_MID(OC3)"
+ register "usb2_ports[7]" = "USB2_PORT_MID(OC3)"
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)"
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)"
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)"
+ register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC1)"
+
+ register "SataSalpSupport" = "1"
+
+ register "SataPortsEnable" = "{
+ [0] = 1,
+ [1] = 1,
+ }"
+
+ register "SataPortsDevSlp" = "{
+ [0] = 1,
+ [1] = 1,
+ }"
+
+ register "SerialIoUartMode" = "{
+ [PchSerialIoIndexUART0] = PchSerialIoSkipInit,
+ [PchSerialIoIndexUART1] = PchSerialIoPci,
+ [PchSerialIoIndexUART2] = PchSerialIoDisabled,
+ }"
+
device domain 0 on
device ref pcie5 on end
device ref igpu on end
@@ -19,18 +52,10 @@
device ref tbt_pcie_rp2 on end
device ref tbt_pcie_rp3 on end
device ref crashlog off end
- device ref tcss_xhci on end
- device ref tcss_dma0 on end
- device ref tcss_dma1 on end
device ref xhci on end
device ref cnvi_wifi on end
- device ref i2c0 on end
- device ref i2c1 on end
- device ref i2c2 on end
- device ref i2c3 on end
device ref heci1 on end
device ref sata on end
- device ref i2c5 on end
device ref pcie_rp1 on end
device ref pcie_rp3 on end # W/A to FSP issue
device ref pcie_rp4 on end # W/A to FSP issue
@@ -40,7 +65,7 @@
device ref pcie_rp9 on end
device ref pcie_rp11 on end
device ref uart0 on end
- device ref gspi0 on end
+ device ref uart1 on end
device ref p2sb on end
device ref hda on end
device ref smbus on end
3 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
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Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61306 )
Change subject: console: Add loglevel prefix to interactive consoles
......................................................................
Patch Set 5:
(1 comment)
File src/console/printk.c:
https://review.coreboot.org/c/coreboot/+/61306/comment/f980eb10_851515ee
PS5, Line 80: console_interactive_tx_byte
> Can we use `vtxprintf(interactive_putchar, BIOS_LOG_PREFIX_PATTERN, &bios_log_prefix[state. […]
Might be cleaner to add a `static interactive_printk(fmt, args)`. Then you can use the format specifiers for the styling as well.
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Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61573 )
Change subject: Documentation/releases: Add 4.17 release notes template
......................................................................
Patch Set 2: Code-Review+2
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Change subject: console: Add loglevel marker codes to stored consoles
......................................................................
Patch Set 6: Code-Review+2
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Change subject: cpu/x86/smm: Improve smm stack setup
......................................................................
Patch Set 5: Code-Review+1
(1 comment)
File src/cpu/x86/smm/smm_module_loader.c:
https://review.coreboot.org/c/coreboot/+/58698/comment/6aac72b0_812576a1
PS5, Line 262: return 0;
Sorry maybe an out of topic question:
does it makes sense to use 'CB_SUCCESS' and 'CB_ERR' instead of return {0,-1} ?
(sorry again for out of topic question)
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Change subject: console: Add ANSI escape sequences for highlighting
......................................................................
Patch Set 5:
(1 comment)
File src/console/printk.c:
https://review.coreboot.org/c/coreboot/+/61307/comment/f5a9300a_3afe1ef7
PS5, Line 82: console_interactive_tx_byte
I think using `vtxprintf` would make this more maintainable.
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