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Hello Shelley Chen, build bot (Jenkins), mturney mturney, Julius Werner, mturney mturney,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59195
to look at the new patch set (#18).
Change subject: soc/qualcomm/common: Add dram information to CBMEM table
......................................................................
soc/qualcomm/common: Add dram information to CBMEM table
BUG=b:182963902,177917361
TEST=Validated on qualcomm sc7280 developement board
Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org>
Change-Id: I0f1dd05ee224bf8284661c0afaa01d0a9d71daa7
---
M src/soc/qualcomm/common/include/soc/qclib_common.h
M src/soc/qualcomm/common/qclib.c
2 files changed, 35 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/59195/18
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Hello Shelley Chen, build bot (Jenkins), Taniya Das,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#8).
Change subject: qualcomm/sc7280: Add display external clock support in coreboot
......................................................................
qualcomm/sc7280: Add display external clock support in coreboot
Add support for EDP (Embedded DisplayPort) clocks in coreboot.
This change supports the configuration and enablement of
EDP PIXEL, LINK, LINK_INTF and AUX clocks.
BUG=b:182963902,216687885
TEST=Validated on qualcomm sc7280 development board.
Signed-off-by: Taniya Das <quic_tdas(a)quicinc.com>
Change-Id: Ia6872ede515401e95ea2dadc9766e3e70fb66144
---
M src/soc/qualcomm/sc7280/clock.c
M src/soc/qualcomm/sc7280/include/soc/clock.h
2 files changed, 53 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/59611/8
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58700 )
Change subject: [WIP]cpu/x86/smm: Support PARALLEL_MP with SMM_ASEG
......................................................................
Patch Set 3:
(1 comment)
File src/cpu/x86/smm/smm_module_loader.c:
https://review.coreboot.org/c/coreboot/+/58700/comment/f4855477_0e9b2a63
PS2, Line 619: */
> Patchset #1, #2 have stuff leaking below 0xa0000.
>
> Installing permanent SMM handler to 0x000a0000
> smm_create_map: cpus allowed in one segment 62
> smm_create_map: min # of segments needed 1
> CPU 0x0
> smbase a0000 entry a8000
> ss_start afe00 code_end a81e0
> CPU 0x1
> smbase 9fe00 entry a7e00
> ss_start afc00 code_end a7fe0
That looks fine. smbase are below 0xa0000 so that the save states grow downwards from 0xb0000.
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61499 )
Change subject: mb/google/brya: Allow mainboard to lock I2C TPM SCL/SDA GPIO PADs
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
@Tim/Nick/Eric, Can you take a look into this CL
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Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59636 )
Change subject: Revert "util/crossgcc: Update gcc to 11.2"
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Mike, any news here? This change-set is probably not the best way to discuss this. […]
So far I've provided all the requested logs (see above) and tried a suggestion with the "safe" flags (which didn't help unfortunately). This issue have been reproduced by other people with AMD boards like G505S and also Thinkpad X201 ( https://ticket.coreboot.org/issues/322 ) <--- although in X201 case the board seemed unbootable at all, while in my case it usually gets past this coreboot+SeaBIOS point and gets stuck booting Linux. I'm not sure how to proceed, and any suggestions will be appreciated.
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Change subject: soc/intel/{adl, common}: Add routines into CSE IA-common code
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/alderlake/finalize.c:
https://review.coreboot.org/c/coreboot/+/61518/comment/7dfeafb1_ef57f09e
PS1, Line 83: /* Function to set D0I3 for all HECI devices */
: void soc_set_d0i3_for_heci(void)
: {
: unsigned int cse_dev[] = {
: PCH_DEVFN_CSE,
: PCH_DEVFN_CSE_2,
: PCH_DEVFN_CSE_3,
: PCH_DEVFN_CSE_4
: };
:
: for (int i = 0; i < ARRAY_SIZE(cse_dev); i++) {
: if (!is_cse_devfn_visible(cse_dev[i]))
: continue;
:
: set_cse_device_state(cse_dev[i], DEV_IDLE);
: }
: }
:
> Could this function just be moved to common code?
The only reason why I would prefer to have HECI device lists coming from SoC layer instead common code because of number of HECI device.
ADL, CNL, ICL, JSL, => 4 HECI devices
SKL => 3 HECI devices
TGL => 3 HECI devices (but there is mistake it should be 4 as per EDS)
After reading your comments I had another idea, let me try something today.
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Change subject: mb/google/brya: Allow mainboard to lock PCH_WP_OD GPIO PADs
......................................................................
Patch Set 2: Code-Review+2
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Change subject: mb/google/brya: Allow mainboard to lock GSC_PCH_INT_ODL GPIO PADs
......................................................................
Patch Set 2: Code-Review+2
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Change subject: mb/google/brya/variants/gimble: Disable PCIE RP 6 and TCSS Port 1
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61266/comment/945a40ba_21b2a59a
PS2, Line 10: Hence disabling it.
> Kindly update the tests you did with this CL. […]
Done
https://review.coreboot.org/c/coreboot/+/61266/comment/54f26ac1_31247559
PS2, Line 12: Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com>
> BUG=b:216533766 […]
Done
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