coreboot-gerrit February 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/qualcomm/common: Add dram information to CBMEM table
by Ravi kumar (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Ravi kumar, mturney mturney, Sudheer Amrabadi. Hello Shelley Chen, build bot (Jenkins), mturney mturney, Julius Werner, mturney mturney, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59195 to look at the new patch set (#18). Change subject: soc/qualcomm/common: Add dram information to CBMEM table ...................................................................... soc/qualcomm/common: Add dram information to CBMEM table BUG=b:182963902,177917361 TEST=Validated on qualcomm sc7280 developement board Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org> Change-Id: I0f1dd05ee224bf8284661c0afaa01d0a9d71daa7 --- M src/soc/qualcomm/common/include/soc/qclib_common.h M src/soc/qualcomm/common/qclib.c 2 files changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/59195/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/59195 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f1dd05ee224bf8284661c0afaa01d0a9d71daa7 Gerrit-Change-Number: 59195 Gerrit-PatchSet: 18 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: mturney mturney <mturney(a)codeaurora.org> Gerrit-Attention: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: mturney mturney <quic_mturney(a)quicinc.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: qualcomm/sc7280: Add display external clock support in coreboot
by Ravi kumar (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Ravi kumar, Taniya Das. Hello Shelley Chen, build bot (Jenkins), Taniya Das, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/59611 to look at the new patch set (#8). Change subject: qualcomm/sc7280: Add display external clock support in coreboot ...................................................................... qualcomm/sc7280: Add display external clock support in coreboot Add support for EDP (Embedded DisplayPort) clocks in coreboot. This change supports the configuration and enablement of EDP PIXEL, LINK, LINK_INTF and AUX clocks. BUG=b:182963902,216687885 TEST=Validated on qualcomm sc7280 development board. Signed-off-by: Taniya Das <quic_tdas(a)quicinc.com> Change-Id: Ia6872ede515401e95ea2dadc9766e3e70fb66144 --- M src/soc/qualcomm/sc7280/clock.c M src/soc/qualcomm/sc7280/include/soc/clock.h 2 files changed, 53 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/59611/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/59611 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6872ede515401e95ea2dadc9766e3e70fb66144 Gerrit-Change-Number: 59611 Gerrit-PatchSet: 8 Gerrit-Owner: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Taniya Das <tdas(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Attention: Taniya Das <quic_tdas(a)quicinc.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP]cpu/x86/smm: Support PARALLEL_MP with SMM_ASEG
by Arthur Heymans (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Arthur Heymans, Kyösti Mälkki. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58700 ) Change subject: [WIP]cpu/x86/smm: Support PARALLEL_MP with SMM_ASEG ...................................................................... Patch Set 3: (1 comment) File src/cpu/x86/smm/smm_module_loader.c: https://review.coreboot.org/c/coreboot/+/58700/comment/f4855477_0e9b2a63 PS2, Line 619: */ > Patchset #1, #2 have stuff leaking below 0xa0000. > > Installing permanent SMM handler to 0x000a0000 > smm_create_map: cpus allowed in one segment 62 > smm_create_map: min # of segments needed 1 > CPU 0x0 > smbase a0000 entry a8000 > ss_start afe00 code_end a81e0 > CPU 0x1 > smbase 9fe00 entry a7e00 > ss_start afc00 code_end a7fe0 That looks fine. smbase are below 0xa0000 so that the save states grow downwards from 0xb0000. -- To view, visit https://review.coreboot.org/c/coreboot/+/58700 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If499e21a8dc7fca18bd5990f833170d0fc21e10c Gerrit-Change-Number: 58700 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Tue, 01 Feb 2022 08:25:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Allow mainboard to lock I2C TPM SCL/SDA GPIO PADs
by Subrata Banik (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61499 ) Change subject: mb/google/brya: Allow mainboard to lock I2C TPM SCL/SDA GPIO PADs ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: @Tim/Nick/Eric, Can you take a look into this CL -- To view, visit https://review.coreboot.org/c/coreboot/+/61499 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f2a7014faeecd4701ea35ec77ef0e1692516b9d Gerrit-Change-Number: 61499 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 01 Feb 2022 08:23:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "util/crossgcc: Update gcc to 11.2"
by Mike Banon (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Nico Huber, Branden Waldner, Idwer Vollering, Paul Menzel, Jacob Garber, Arthur Heymans, Werner Zeh, Iru Cai, HAOUAS Elyes, Harshit Sharma. Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59636 ) Change subject: Revert "util/crossgcc: Update gcc to 11.2" ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Mike, any news here? This change-set is probably not the best way to discuss this. […] So far I've provided all the requested logs (see above) and tried a suggestion with the "safe" flags (which didn't help unfortunately). This issue have been reproduced by other people with AMD boards like G505S and also Thinkpad X201 ( https://ticket.coreboot.org/issues/322 ) <--- although in X201 case the board seemed unbootable at all, while in my case it usually gets past this coreboot+SeaBIOS point and gets stuck booting Linux. I'm not sure how to proceed, and any suggestions will be appreciated. -- To view, visit https://review.coreboot.org/c/coreboot/+/59636 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09a789f9ccb284ac7cad32b12bbf60ecb82efb44 Gerrit-Change-Number: 59636 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-Reviewer: Branden Waldner <scruffy99(a)gmail.com> Gerrit-Reviewer: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-CC: Michal Zygowski <miczyg94(a)gmail.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Branden Waldner <scruffy99(a)gmail.com> Gerrit-Attention: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jacob Garber <jgarber1(a)ualberta.ca> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Attention: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Attention: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Comment-Date: Tue, 01 Feb 2022 07:04:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: [TEST]src/drivers/intel/fsp2_0: Change fsp_is_multi_phase_init_enable...
by Ronak Kanabar (Code Review) 01 Feb '22

01 Feb '22

Ronak Kanabar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61527 ) Change subject: [TEST]src/drivers/intel/fsp2_0: Change fsp_is_multi_phase_init_enabled check ...................................................................... [TEST]src/drivers/intel/fsp2_0: Change fsp_is_multi_phase_init_enabled check Add check of USE_INTEL_FSP_MP_INIT config in fsp_is_multi_phase_init_enabled Change-Id: I35ba5a3f0540c18652e5ad2c25e11258477e53b6 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/drivers/intel/fsp2_0/silicon_init.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/61527/1 diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 83d44b1..cc7a98a 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -75,7 +75,8 @@ bool fsp_is_multi_phase_init_enabled(void) { return CONFIG(FSPS_USE_MULTI_PHASE_INIT) && - (fsps_hdr.multi_phase_si_init_entry_offset != 0); + (fsps_hdr.multi_phase_si_init_entry_offset != 0) && + (!CONFIG(USE_INTEL_FSP_MP_INIT)); } static void fsp_fill_common_arch_params(FSPS_UPD *supd) -- To view, visit https://review.coreboot.org/c/coreboot/+/61527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I35ba5a3f0540c18652e5ad2c25e11258477e53b6 Gerrit-Change-Number: 61527 Gerrit-PatchSet: 1 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/{adl, common}: Add routines into CSE IA-common code
by Subrata Banik (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Werner Zeh, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61518 ) Change subject: soc/intel/{adl, common}: Add routines into CSE IA-common code ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/alderlake/finalize.c: https://review.coreboot.org/c/coreboot/+/61518/comment/7dfeafb1_ef57f09e PS1, Line 83: /* Function to set D0I3 for all HECI devices */ : void soc_set_d0i3_for_heci(void) : { : unsigned int cse_dev[] = { : PCH_DEVFN_CSE, : PCH_DEVFN_CSE_2, : PCH_DEVFN_CSE_3, : PCH_DEVFN_CSE_4 : }; : : for (int i = 0; i < ARRAY_SIZE(cse_dev); i++) { : if (!is_cse_devfn_visible(cse_dev[i])) : continue; : : set_cse_device_state(cse_dev[i], DEV_IDLE); : } : } : > Could this function just be moved to common code? The only reason why I would prefer to have HECI device lists coming from SoC layer instead common code because of number of HECI device. ADL, CNL, ICL, JSL, => 4 HECI devices SKL => 3 HECI devices TGL => 3 HECI devices (but there is mistake it should be 4 as per EDS) After reading your comments I had another idea, let me try something today. -- To view, visit https://review.coreboot.org/c/coreboot/+/61518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie32887196628fe6386896604e50338f4bc0bedfe Gerrit-Change-Number: 61518 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 01 Feb 2022 05:51:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Allow mainboard to lock PCH_WP_OD GPIO PADs
by EricR Lai (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Nick Vaccaro. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61501 ) Change subject: mb/google/brya: Allow mainboard to lock PCH_WP_OD GPIO PADs ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia125c513c09ecbb1047100e72f8540369646988e Gerrit-Change-Number: 61501 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 01 Feb 2022 05:32:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya: Allow mainboard to lock GSC_PCH_INT_ODL GPIO PADs
by EricR Lai (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Subrata Banik, Tim Wawrzynczak, Nick Vaccaro. EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61500 ) Change subject: mb/google/brya: Allow mainboard to lock GSC_PCH_INT_ODL GPIO PADs ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61500 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icfc251152278c59f9a94b84fcd8c6d36c26bff62 Gerrit-Change-Number: 61500 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 01 Feb 2022 05:32:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/brya/variants/gimble: Disable PCIE RP 6 and TCSS Port 1
by Meera Ravindranath (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Maulik V Vaghela, Sridhar Siricilla, Nick Vaccaro. Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61266 ) Change subject: mb/google/brya/variants/gimble: Disable PCIE RP 6 and TCSS Port 1 ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/61266/comment/945a40ba_21b2a59a PS2, Line 10: Hence disabling it. > Kindly update the tests you did with this CL. […] Done https://review.coreboot.org/c/coreboot/+/61266/comment/54f26ac1_31247559 PS2, Line 12: Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> > BUG=b:216533766 […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/61266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0e7ae72620da39fc18ff253c440d006e83c576f3 Gerrit-Change-Number: 61266 Gerrit-PatchSet: 3 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Mark Hsieh <mark_hsieh(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anfernee Chen <anfernee_chen(a)wistron.corp-partner.google.com> Gerrit-CC: Casper Chang <casper_chang(a)wistron.corp-partner.google.com> Gerrit-CC: Kane Chen <kane.chen(a)intel.com> Gerrit-CC: Malik Hsu <malik_hsu(a)wistron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Scott Chao <scott_chao(a)wistron.corp-partner.google.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 01 Feb 2022 04:37:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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coreboot-gerrit February 2022