coreboot-gerrit February 2022

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Change in coreboot[master]: soc/intel/alderlake: Add eMMC PCR Port ID for Alder Lake N
by Subrata Banik (Code Review) 01 Feb '22

01 Feb '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61126 ) Change subject: soc/intel/alderlake: Add eMMC PCR Port ID for Alder Lake N ...................................................................... soc/intel/alderlake: Add eMMC PCR Port ID for Alder Lake N Alder Lake N has eMMC storage device. Add PCR Port ID for it. Reference: Alder Lake N platform EDS Doc# 645548. Change-Id: I6dc494d1748e66b8b4058954f127ec226863e8af Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61126 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> --- M src/soc/intel/alderlake/include/soc/pcr_ids.h 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Kangheui Won: Looks good to me, approved diff --git a/src/soc/intel/alderlake/include/soc/pcr_ids.h b/src/soc/intel/alderlake/include/soc/pcr_ids.h index f125ee2..623a8140 100644 --- a/src/soc/intel/alderlake/include/soc/pcr_ids.h +++ b/src/soc/intel/alderlake/include/soc/pcr_ids.h @@ -33,6 +33,9 @@ #define PID_ITSS 0xc4 #define PID_SERIALIO 0xcb +/* eMMC Port ID for Alder Lake N */ +#define PID_EMMC 0xa1 + /* CPU Port IDs */ #define PID_CPU_GPIOCOM0 0xb7 #define PID_CPU_GPIOCOM1 0xb8 -- To view, visit https://review.coreboot.org/c/coreboot/+/61126 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6dc494d1748e66b8b4058954f127ec226863e8af Gerrit-Change-Number: 61126 Gerrit-PatchSet: 5 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Add GPP_I GPIO group for Alder Lake N SOC
by Subrata Banik (Code Review) 01 Feb '22

01 Feb '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61106 ) Change subject: soc/intel/alderlake: Add GPP_I GPIO group for Alder Lake N SOC ...................................................................... soc/intel/alderlake: Add GPP_I GPIO group for Alder Lake N SOC Add definitions for GPP_I GPIO group pins on Alder Lake N SOC and GPIO IRQ routing information. GPP_I GPIO group belongs to GPIO community 1. Hence GPIO community 1 in Alder Lake N contains GPP_S, GPP_I, GPP_H, GPP_D GPIO groups. GPIO groups 1-6 in Doc# 645550 Chapter 36 corresponds to GPIO communities 5-0 respectively. BUG=b:213535859 Change-Id: Ia71a399c03cb7d098a381bd9439d448e8a620761 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61106 Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/gpio.c M src/soc/intel/alderlake/include/soc/gpio_defs.h M src/soc/intel/alderlake/include/soc/gpio_soc_defs.h M src/soc/intel/alderlake/include/soc/pmc.h 4 files changed, 301 insertions(+), 49 deletions(-) Approvals: build bot (Jenkins): Verified Rizwan Qureshi: Looks good to me, approved Kangheui Won: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/alderlake/gpio.c b/src/soc/intel/alderlake/gpio.c index 3d5af83..bf067b2 100644 --- a/src/soc/intel/alderlake/gpio.c +++ b/src/soc/intel/alderlake/gpio.c @@ -46,6 +46,15 @@ {GPP_B0, GPP_B23}, }; +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) +static const struct pad_group adl_community1_groups[] = { + INTEL_GPP_BASE(GPP_S0, GPP_S0, GPP_S7, 96), /* GPP_S */ + INTEL_GPP_BASE(GPP_S0, GPP_I0, GPP_I19, 128), /* GPP_I */ + INTEL_GPP_BASE(GPP_S0, GPP_H0, GPP_H23, 160), /* GPP_H */ + INTEL_GPP_BASE(GPP_S0, GPP_D0, GPP_GSPI2_CLK_LOOPBK, 192), /* GPP_D */ + INTEL_GPP(GPP_S0, GPP_VGPIO_0, GPP_VGPIO_THC1), /* vGPIO */ +}; +#else static const struct pad_group adl_community1_groups[] = { INTEL_GPP_BASE(GPP_S0, GPP_S0, GPP_S7, 96), /* GPP_S */ INTEL_GPP_BASE(GPP_S0, GPP_H0, GPP_H23, 128), /* GPP_H */ @@ -53,6 +62,7 @@ INTEL_GPP(GPP_S0, GPP_CPU_RSVD_1, GPP_CPU_RSVD_24), /* GPP_CPU_RSVD */ INTEL_GPP(GPP_S0, GPP_VGPIO_0, GPP_VGPIO_37), /* vGPIO */ }; +#endif static const struct vw_entries adl_community1_vw[] = { {GPP_D0, GPP_D19}, @@ -112,7 +122,8 @@ .vw_entries = adl_community0_vw, .num_vw_entries = ARRAY_SIZE(adl_community0_vw), }, - [COMM_1] = { /* GPP S, D, H */ + [COMM_1] = { /* GPP S, D, H for ADL-P/M + GPP S, I, D, H for ADL-N */ .port = PID_GPIOCOM1, .cpu_port = PID_CPU_GPIOCOM1, .first_pad = GPIO_COM1_START, @@ -126,7 +137,11 @@ .gpi_smi_sts_reg_0 = GPI_SMI_STS_0, .gpi_smi_en_reg_0 = GPI_SMI_EN_0, .max_pads_per_group = GPIO_MAX_NUM_PER_GROUP, +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) + .name = "GPP_SIHD", +#else .name = "GPP_SDH", +#endif .acpi_path = "\\_SB.PCI0.GPIO", .reset_map = rst_map_gpp, .num_reset_vals = ARRAY_SIZE(rst_map_gpp), @@ -236,6 +251,9 @@ { PMC_GPP_T, GPP_T }, { PMC_GPP_A, GPP_A }, { PMC_GPP_S, GPP_S }, +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) + { PMC_GPP_I, GPP_I }, +#endif { PMC_GPP_H, GPP_H }, { PMC_GPP_D, GPP_D }, { PMC_GPD, GPD }, diff --git a/src/soc/intel/alderlake/include/soc/gpio_defs.h b/src/soc/intel/alderlake/include/soc/gpio_defs.h index e4f84ec..8602167 100644 --- a/src/soc/intel/alderlake/include/soc/gpio_defs.h +++ b/src/soc/intel/alderlake/include/soc/gpio_defs.h @@ -129,6 +129,29 @@ #define GPP_C22_IRQ 0x24 #define GPP_C23_IRQ 0x25 +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) +/* Group D */ +#define GPP_D0_IRQ 0x40 +#define GPP_D1_IRQ 0x41 +#define GPP_D2_IRQ 0x42 +#define GPP_D3_IRQ 0x43 +#define GPP_D4_IRQ 0x44 +#define GPP_D5_IRQ 0x45 +#define GPP_D6_IRQ 0x46 +#define GPP_D7_IRQ 0x47 +#define GPP_D8_IRQ 0x48 +#define GPP_D9_IRQ 0x49 +#define GPP_D10_IRQ 0x4A +#define GPP_D11_IRQ 0x4B +#define GPP_D12_IRQ 0x4C +#define GPP_D13_IRQ 0x4D +#define GPP_D14_IRQ 0x4E +#define GPP_D15_IRQ 0x4F +#define GPP_D16_IRQ 0x50 +#define GPP_D17_IRQ 0x51 +#define GPP_D18_IRQ 0x52 +#define GPP_D19_IRQ 0x53 +#else /* Group D */ #define GPP_D0_IRQ 0x2C #define GPP_D1_IRQ 0x2D @@ -150,6 +173,7 @@ #define GPP_D17_IRQ 0x3D #define GPP_D18_IRQ 0x3E #define GPP_D19_IRQ 0x3F +#endif /* Group E */ #define GPP_E0_IRQ 0x26 @@ -203,6 +227,55 @@ #define GPP_F22_IRQ 0x6C #define GPP_F23_IRQ 0x6D +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) +/* Group H */ +#define GPP_H0_IRQ 0x28 +#define GPP_H1_IRQ 0x29 +#define GPP_H2_IRQ 0x2A +#define GPP_H3_IRQ 0x2B +#define GPP_H4_IRQ 0x2C +#define GPP_H5_IRQ 0x2D +#define GPP_H6_IRQ 0x2E +#define GPP_H7_IRQ 0x2F +#define GPP_H8_IRQ 0x30 +#define GPP_H9_IRQ 0x31 +#define GPP_H10_IRQ 0x32 +#define GPP_H11_IRQ 0x33 +#define GPP_H12_IRQ 0x34 +#define GPP_H13_IRQ 0x35 +#define GPP_H14_IRQ 0x36 +#define GPP_H15_IRQ 0x37 +#define GPP_H16_IRQ 0x38 +#define GPP_H17_IRQ 0x39 +#define GPP_H18_IRQ 0x3A +#define GPP_H19_IRQ 0x3B +#define GPP_H20_IRQ 0x3C +#define GPP_H21_IRQ 0x3D +#define GPP_H22_IRQ 0x3E +#define GPP_H23_IRQ 0x3F + +/* Group I */ +#define GPP_I0_IRQ 0x74 +#define GPP_I1_IRQ 0x75 +#define GPP_I2_IRQ 0x76 +#define GPP_I3_IRQ 0x77 +#define GPP_I4_IRQ 0x18 +#define GPP_I5_IRQ 0x19 +#define GPP_I6_IRQ 0x1A +#define GPP_I7_IRQ 0x1B +#define GPP_I8_IRQ 0x1C +#define GPP_I9_IRQ 0x1D +#define GPP_I10_IRQ 0x1E +#define GPP_I11_IRQ 0x1F +#define GPP_I12_IRQ 0x20 +#define GPP_I13_IRQ 0x21 +#define GPP_I14_IRQ 0x22 +#define GPP_I15_IRQ 0x23 +#define GPP_I16_IRQ 0x24 +#define GPP_I17_IRQ 0x25 +#define GPP_I18_IRQ 0x26 +#define GPP_I19_IRQ 0x27 +#else /* Group H */ #define GPP_H0_IRQ 0x74 #define GPP_H1_IRQ 0x75 @@ -228,6 +301,7 @@ #define GPP_H21_IRQ 0x29 #define GPP_H22_IRQ 0x2A #define GPP_H23_IRQ 0x2B +#endif /* Group R */ #define GPP_R0_IRQ 0x58 diff --git a/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h b/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h index b7216fa..80e656c 100644 --- a/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h +++ b/src/soc/intel/alderlake/include/soc/gpio_soc_defs.h @@ -17,7 +17,12 @@ #define GPP_R INC(GPP_A) #define GPD INC(GPP_R) #define GPP_S INC(GPD) +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) +#define GPP_I INC(GPP_S) +#define GPP_H INC(GPP_I) +#else #define GPP_H INC(GPP_S) +#endif #define GPP_D INC(GPP_H) #define GPP_F 0xA #define GPP_C INC(GPP_F) @@ -35,9 +40,15 @@ * GPIOs are ordered monotonically increasing to match ACPI/OS driver. */ /* - * Group B - * PAD Start Number = 0 - * PAD End Number = 25 + * +------------------------------------+ + * | Group B | + * +------------------+---------+-------+ + * | | ADL-P/M | ADL-N | + * +------------------+---------+-------+ + * | Pad Start Number | 0 | 0 | + * +------------------+---------+-------+ + * | Pad End Number | 25 | 25 | + * +------------------+---------+-------+ */ #define GPP_B0 0 #define GPP_B1 INC(GPP_B0) @@ -67,9 +78,15 @@ #define GPP_B25 INC(GPP_B24) /* GSPI1_CLK_LOOPBK */ /* - * Group T - * PAD Start Number = 26 - * PAD End Number = 41 + * +------------------------------------+ + * | Group T | + * +------------------+---------+-------+ + * | | ADL-P/M | ADL-N | + * +------------------+---------+-------+ + * | Pad Start Number | 26 | 26 | + * +------------------+---------+-------+ + * | Pad End Number | 41 | 41 | + * +------------------+---------+-------+ */ #define GPP_T0 INC(GPP_B25) #define GPP_T1 INC(GPP_T0) @@ -89,9 +106,15 @@ #define GPP_T15 INC(GPP_T14) /* - * Group A - * PAD Start Number = 42 - * PAD End Number = 66 + * +------------------------------------+ + * | Group A | + * +------------------+---------+-------+ + * | | ADL-P/M | ADL-N | + * +------------------+---------+-------+ + * | Pad Start Number | 42 | 42 | + * +------------------+---------+-------+ + * | Pad End Number | 66 | 66 | + * +------------------+---------+-------+ */ #define GPP_A0 INC(GPP_T15) #define GPP_A1 INC(GPP_A0) @@ -124,9 +147,15 @@ #define NUM_GPIO_COM0_PADS (GPIO_COM0_END - GPIO_COM0_START + 1) /* - * Group S - * PAD Start Number = 67 - * PAD End Number = 74 + * +------------------------------------+ + * | Group S | + * +------------------+---------+-------+ + * | | ADL-P/M | ADL-N | + * +------------------+---------+-------+ + * | Pad Start Number | 67 | 67 | + * +------------------+---------+-------+ + * | Pad End Number | 74 | 74 | + * +------------------+---------+-------+ */ #define GPP_S0 INC(GPP_ESPI_CLK_LOOPBK) #define GPP_S1 INC(GPP_S0) @@ -137,12 +166,54 @@ #define GPP_S6 INC(GPP_S5) #define GPP_S7 INC(GPP_S6) +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) /* - * Group H - * PAD Start Number = 75 - * PAD End Number = 98 + * +------------------------------------+ + * | Group I | + * +------------------+---------+-------+ + * | | ADL-P/M | ADL-N | + * +------------------+---------+-------+ + * | Pad Start Number | NA | 75 | + * +------------------+---------+-------+ + * | Pad End Number | NA | 94 | + * +------------------+---------+-------+ */ +#define GPP_I0 INC(GPP_S7) +#define GPP_I1 INC(GPP_I0) +#define GPP_I2 INC(GPP_I1) +#define GPP_I3 INC(GPP_I2) +#define GPP_I4 INC(GPP_I3) +#define GPP_I5 INC(GPP_I4) +#define GPP_I6 INC(GPP_I5) +#define GPP_I7 INC(GPP_I6) +#define GPP_I8 INC(GPP_I7) +#define GPP_I9 INC(GPP_I8) +#define GPP_I10 INC(GPP_I9) +#define GPP_I11 INC(GPP_I10) +#define GPP_I12 INC(GPP_I11) +#define GPP_I13 INC(GPP_I12) +#define GPP_I14 INC(GPP_I13) +#define GPP_I15 INC(GPP_I14) +#define GPP_I16 INC(GPP_I15) +#define GPP_I17 INC(GPP_I16) +#define GPP_I18 INC(GPP_I17) +#define GPP_I19 INC(GPP_I18) + +/* + * +------------------------------------+ + * | Group H | + * +------------------+---------+-------+ + * | | ADL-P/M | ADL-N | + * +------------------+---------+-------+ + * | Pad Start Number | 75 | 95 | + * +------------------+---------+-------+ + * | Pad End Number | 98 | 118 | + * +------------------+---------+-------+ + */ +#define GPP_H0 INC(GPP_I19) +#else #define GPP_H0 INC(GPP_S7) +#endif #define GPP_H1 INC(GPP_H0) #define GPP_H2 INC(GPP_H1) #define GPP_H3 INC(GPP_H2) @@ -168,9 +239,15 @@ #define GPP_H23 INC(GPP_H22) /* - * Group D - * PAD Start Number = 99 - * PAD End Number = 119 + * +------------------------------------+ + * | Group D | + * +------------------+---------+-------+ + * | | ADL-P/M | ADL-N | + * +------------------+---------+-------+ + * | Pad Start Number | 99 | 119 | + * +------------------+---------+-------+ + * | Pad End Number | 119 | 139 | + * +------------------+---------+-------+ */ #define GPP_D0 INC(GPP_H23) #define GPP_D1 INC(GPP_D0) @@ -194,10 +271,17 @@ #define GPP_D19 INC(GPP_D18) #define GPP_GSPI2_CLK_LOOPBK INC(GPP_D19) +#if !CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) /* - * Reserved GPIOs - * PAD Start Number = 120 - * PAD End Number = 143 + * +------------------------------------+ + * | Reserved GPIOs | + * +------------------+---------+-------+ + * | | ADL-P/M | ADL-N | + * +------------------+---------+-------+ + * | Pad Start Number | 120 | NA | + * +------------------+---------+-------+ + * | Pad End Number | 143 | NA | + * +------------------+---------+-------+ */ #define GPP_CPU_RSVD_1 INC(GPP_GSPI2_CLK_LOOPBK) #define GPP_CPU_RSVD_2 INC(GPP_CPU_RSVD_1) @@ -225,11 +309,20 @@ #define GPP_CPU_RSVD_24 INC(GPP_CPU_RSVD_23) /* - * Group VGPIO - * PAD Start Number = 144 - * PAD End Number = 170 + * +------------------------------------+ + * | Group VGPIO | + * +------------------+---------+-------+ + * | | ADL-P/M | ADL-N | + * +------------------+---------+-------+ + * | Pad Start Number | 144 | 140 | + * +------------------+---------+-------+ + * | Pad End Number | 170 | 168 | + * +------------------+---------+-------+ */ #define GPP_VGPIO_0 INC(GPP_CPU_RSVD_24) +#else +#define GPP_VGPIO_0 INC(GPP_GSPI2_CLK_LOOPBK) +#endif #define GPP_VGPIO_4 INC(GPP_VGPIO_0) #define GPP_VGPIO_5 INC(GPP_VGPIO_4) #define GPP_VGPIO_6 INC(GPP_VGPIO_5) @@ -257,16 +350,35 @@ #define GPP_VGPIO_36 INC(GPP_VGPIO_35) #define GPP_VGPIO_37 INC(GPP_VGPIO_36) +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) +#define GPP_VGPIO_THC0 INC(GPP_VGPIO_37) +#define GPP_VGPIO_THC1 INC(GPP_VGPIO_THC0) +#endif + #define GPIO_COM1_START GPP_S0 +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) +#define GPIO_COM1_END GPP_VGPIO_THC1 +#else #define GPIO_COM1_END GPP_VGPIO_37 +#endif #define NUM_GPIO_COM1_PADS (GPIO_COM1_END - GPIO_COM1_START + 1) +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) /* - * Group GPD - * PAD Start Number = 171 - * PAD End Number = 187 + * +------------------------------------+ + * | Group GPD | + * +------------------+---------+-------+ + * | | ADL-P/M | ADL-N | + * +------------------+---------+-------+ + * | Pad Start Number | 171 | 169 | + * +------------------+---------+-------+ + * | Pad End Number | 187 | 185 | + * +------------------+---------+-------+ */ +#define GPD0 INC(GPP_VGPIO_THC1) +#else #define GPD0 INC(GPP_VGPIO_37) +#endif #define GPD1 INC(GPD0) #define GPD2 INC(GPD1) #define GPD3 INC(GPD2) @@ -289,9 +401,15 @@ #define NUM_GPIO_COM2_PADS (GPIO_COM2_END - GPIO_COM2_START + 1) /* - * PCIE VGPIO group - * PAD Start Number = 188 - * PAD End Number = 294 + * +------------------------------------+ + * | PCIE VGPIO Group | + * +------------------+---------+-------+ + * | | ADL-P/M | ADL-N | + * +------------------+---------+-------+ + * | Pad Start Number | 188 | 186 | + * +------------------+---------+-------+ + * | Pad End Number | 294 | 292 | + * +------------------+---------+-------+ */ #define GPP_CPU_RSVD_25 INC(GPD_DRAM_RESETB) #define GPP_CPU_RSVD_26 INC(GPP_CPU_RSVD_25) @@ -406,9 +524,15 @@ #define NUM_GPIO_COM3_PADS (GPIO_COM3_END - GPIO_COM3_START + 1) /* - * Group C - * PAD Start Number = 295 - * PAD End Number = 318 + * +------------------------------------+ + * | Group C | + * +------------------+---------+-------+ + * | | ADL-P/M | ADL-N | + * +------------------+---------+-------+ + * | Pad Start Number | 295 | 293 | + * +------------------+---------+-------+ + * | Pad End Number | 318 | 316 | + * +------------------+---------+-------+ */ #define GPP_C0 INC(GPP_vGPIO_PCIE_83) #define GPP_C1 INC(GPP_C0) @@ -436,9 +560,15 @@ #define GPP_C23 INC(GPP_C22) /* - * Group F - * PAD Start Number = 319 - * PAD End Number = 343 + * +------------------------------------+ + * | Group F | + * +------------------+---------+-------+ + * | | ADL-P/M | ADL-N | + * +------------------+---------+-------+ + * | Pad Start Number | 319 | 317 | + * +------------------+---------+-------+ + * | Pad End Number | 343 | 341 | + * +------------------+---------+-------+ */ #define GPP_F0 INC(GPP_C23) #define GPP_F1 INC(GPP_F0) @@ -467,9 +597,15 @@ #define GPP_F_CLK_LOOPBK INC(GPP_F23) /* - * Group HVMOS - * PAD Start Number = 344 - * PAD End Number = 349 + * +------------------------------------+ + * | Group HVCMOS | + * +------------------+---------+-------+ + * | | ADL-P/M | ADL-N | + * +------------------+---------+-------+ + * | Pad Start Number | 344 | 342 | + * +------------------+---------+-------+ + * | Pad End Number | 349 | 347 | + * +------------------+---------+-------+ */ #define GPP_L_BKLTEN INC(GPP_F_CLK_LOOPBK) #define GPP_L_BKLTCTL INC(GPP_L_BKLTEN) @@ -479,9 +615,15 @@ #define GPP_MLK_RSTB INC(GPP_SYS_RESETB) /* - * Group E - * PAD Start Number = 350 - * PAD End Number = 374 + * +------------------------------------+ + * | Group E | + * +------------------+---------+-------+ + * | | ADL-P/M | ADL-N | + * +------------------+---------+-------+ + * | Pad Start Number | 350 | 348 | + * +------------------+---------+-------+ + * | Pad End Number | 374 | 372 | + * +------------------+---------+-------+ */ #define GPP_E0 INC(GPP_MLK_RSTB) #define GPP_E1 INC(GPP_E0) @@ -514,9 +656,15 @@ #define NUM_GPIO_COM4_PADS (GPIO_COM4_END - GPIO_COM4_START + 1) /* - * Group R - * PAD Start Number = 375 - * PAD End Number = 382 + * +------------------------------------+ + * | Group R | + * +------------------+---------+-------+ + * | | ADL-P/M | ADL-N | + * +------------------+---------+-------+ + * | Pad Start Number | 375 | 373 | + * +------------------+---------+-------+ + * | Pad End Number | 382 | 380 | + * +------------------+---------+-------+ */ #define GPP_R0 INC(GPP_E_CLK_LOOPBK) #define GPP_R1 INC(GPP_R0) @@ -528,9 +676,15 @@ #define GPP_R7 INC(GPP_R6) /* - * Group SPI0 - * PAD Start Number = 383 - * PAD End Number = 390 + * +------------------------------------+ + * | Group SPI0 | + * +------------------+---------+-------+ + * | | ADL-P/M | ADL-N | + * +------------------+---------+-------+ + * | Pad Start Number | 383 | 381 | + * +------------------+---------+-------+ + * | Pad End Number | 390 | 388 | + * +------------------+---------+-------+ */ #define GPP_SPI0_IO_2 INC(GPP_R7) #define GPP_SPI0_IO_3 INC(GPP_SPI0_IO_2) diff --git a/src/soc/intel/alderlake/include/soc/pmc.h b/src/soc/intel/alderlake/include/soc/pmc.h index 2c02a2d..52cc0b5 100644 --- a/src/soc/intel/alderlake/include/soc/pmc.h +++ b/src/soc/intel/alderlake/include/soc/pmc.h @@ -112,8 +112,14 @@ #define PMC_GPP_R 0x3 #define PMC_GPD 0x4 #define PMC_GPP_S 0x5 +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) +#define PMC_GPP_I 0x6 +#define PMC_GPP_H 0x7 +#define PMC_GPP_D 0x8 +#else #define PMC_GPP_H 0x6 #define PMC_GPP_D 0x7 +#endif #define PMC_GPP_F 0xA #define PMC_GPP_C 0xB #define PMC_GPP_E 0xC -- To view, visit https://review.coreboot.org/c/coreboot/+/61106 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia71a399c03cb7d098a381bd9439d448e8a620761 Gerrit-Change-Number: 61106 Gerrit-PatchSet: 12 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/tigerlake: Use PMC IPC to disable HECI1
by Subrata Banik (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Wonkyu Kim, Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai, Karthik Ramasubramanian. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61457 ) Change subject: soc/intel/tigerlake: Use PMC IPC to disable HECI1 ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/tigerlake/smihandler.c: https://review.coreboot.org/c/coreboot/+/61457/comment/b22db25c_9c5c1d98 PS5, Line 19: if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) : heci1_disable(); > Since this is now supposed to use PMC IPC, can we move it outside of SMM ? Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/61457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5f1e3f622f65cd0f892c0dc541625bfd50d038e Gerrit-Change-Number: 61457 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wonkyu Kim Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 01 Feb 2022 10:07:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add PMC register base for ADL-N
by Rizwan Qureshi (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Krishna P Bhat D, Patrick Rudolph, Felix Held. Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61148 ) Change subject: soc/intel/alderlake: Add PMC register base for ADL-N ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/61148/comment/755f15aa_65e0571d PS3, Line 7: adlrvp > alderlake Done -- To view, visit https://review.coreboot.org/c/coreboot/+/61148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c788e149744bfae2c5260c996b16fc1ce2070c1 Gerrit-Change-Number: 61148 Gerrit-PatchSet: 4 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 01 Feb 2022 10:06:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add PMC register base for ADL-N
by Usha P (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Krishna P Bhat D, Patrick Rudolph, Felix Held. Usha P has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61148 ) Change subject: soc/intel/alderlake: Add PMC register base for ADL-N ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/61148/comment/e1f0a13f_cbf1e832 PS3, Line 7: adlrvp > alderlake Done -- To view, visit https://review.coreboot.org/c/coreboot/+/61148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c788e149744bfae2c5260c996b16fc1ce2070c1 Gerrit-Change-Number: 61148 Gerrit-PatchSet: 4 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 01 Feb 2022 10:06:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add PMC register base for ADL-N
by Rizwan Qureshi (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Krishna P Bhat D, Usha P, Patrick Rudolph, Felix Held. Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61148 ) Change subject: soc/intel/alderlake: Add PMC register base for ADL-N ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c788e149744bfae2c5260c996b16fc1ce2070c1 Gerrit-Change-Number: 61148 Gerrit-PatchSet: 4 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 01 Feb 2022 10:06:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add PMC register base for ADL-N
by Usha P (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Krishna P Bhat D, Usha P, Patrick Rudolph, Felix Held. Hello build bot (Jenkins), Maulik V Vaghela, Kangheui Won, Tim Wawrzynczak, Rizwan Qureshi, Reka Norman, Krishna P Bhat D, Patrick Rudolph, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61148 to look at the new patch set (#4). Change subject: soc/intel/alderlake: Add PMC register base for ADL-N ...................................................................... soc/intel/alderlake: Add PMC register base for ADL-N Add PCR_PSF3_TO_SHDW_PMC_REG_BASE for Alderlake-N.This value is updated from the FSP code. Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: I7c788e149744bfae2c5260c996b16fc1ce2070c1 --- M src/soc/intel/alderlake/bootblock/pch.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/61148/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/61148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c788e149744bfae2c5260c996b16fc1ce2070c1 Gerrit-Change-Number: 61148 Gerrit-PatchSet: 4 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/adlrvp: Add PMC register base for ADL-N
by Rizwan Qureshi (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Maulik V Vaghela, Paul Menzel, Krishna P Bhat D, Usha P, Patrick Rudolph, Felix Held. Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61148 ) Change subject: soc/intel/adlrvp: Add PMC register base for ADL-N ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/61148/comment/8781dd78_c01cc804 PS3, Line 7: adlrvp alderlake -- To view, visit https://review.coreboot.org/c/coreboot/+/61148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c788e149744bfae2c5260c996b16fc1ce2070c1 Gerrit-Change-Number: 61148 Gerrit-PatchSet: 3 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 01 Feb 2022 10:05:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Drop unnecessary guard for HECI1 disable FSP UPD
by Subrata Banik (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61455 ) Change subject: soc/intel/cannonlake: Drop unnecessary guard for HECI1 disable FSP UPD ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/cannonlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/61455/comment/012c2fcf_4e6005b7 PS5, Line 590: params->Heci1Disabled = CONFIG(DISABLE_HECI1_AT_PRE_BOOT); > I thought the point was letting coreboot do the disable, so this would be `0` ? Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/61455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8908c080ca9991e7a71e795ccb8fc76d99514f8 Gerrit-Change-Number: 61455 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 01 Feb 2022 10:00:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: security/vboot/secdata_tpm: Set up space for widevine counter info
by Name of user not set (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Andrey Pronin, Paul Menzel, Julius Werner, Rob Barnes, Yu-Ping Wu, Karthik Ramasubramanian. Name of user not set #1004134 has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61521 ) Change subject: security/vboot/secdata_tpm: Set up space for widevine counter info ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > Is there any additional info on what exactly this space should contain and why it is needed anywhere […] This space is required as PSP does not have access to persistent storage and this is required to store Widevine Counter related information in this NV space. How many counters are in use and how many are available, etc. -- To view, visit https://review.coreboot.org/c/coreboot/+/61521 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I80de9024195452a235cbed73e21410f848c91722 Gerrit-Change-Number: 61521 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Name of user not set #1004134 Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Pronin <apronin(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Rob Barnes <robbarnes(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 01 Feb 2022 10:00:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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coreboot-gerrit February 2022