Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61174 )
Change subject: mb/google/guybrush/var/dewatt: Update touchpad GPIO configuration
......................................................................
Patch Set 5:
(1 comment)
File src/mainboard/google/guybrush/variants/dewatt/gpio.c:
https://review.coreboot.org/c/coreboot/+/61174/comment/636a4886_a843b567
PS2, Line 43: LEVEL_LOW
> FW_CONFIG probe is pretty much free isn't it?
It is more to do with the HID over I2C ACPI specification than the trackpad vendor differences.
As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered.
http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3…
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Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61521 )
Change subject: security/vboot/secdata_tpm: Set up space for widevine counter info
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
Is there any additional info on what exactly this space should contain and why it is needed anywhere? I just see a deep chain of bugs that eventually leads to Andrey asking this question in b/192918550#comment64, and it doesn't look like he ever really got an answer? Just want to make sure this was well thought-out, we have been adding a lot of TPM spaces lately.
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Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61354 )
Change subject: drivers/wwan/fm: Add Fibocom 5G WWAN ACPI support
......................................................................
Patch Set 7:
(1 comment)
File src/drivers/wwan/fm/acpi_fm350gl.c:
https://review.coreboot.org/c/coreboot/+/61354/comment/f0a13bc5_2cedf98b
PS2, Line 106: acpigen_write_store_int_to_namestr(1, acpi_device_path_join(parent_dev, "RTD3._OFS"));
> Done
Tim, This is included in today's patchset. Please check this one and the rdt3 one in https://review.coreboot.org/c/coreboot/+/61353.
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Change subject: soc/amd/common/fsp: check fsp image revision
......................................................................
Patch Set 11:
(3 comments)
File src/soc/amd/common/fsp/fsp_validate.c:
https://review.coreboot.org/c/coreboot/+/61281/comment/9c9bf10c_2e0ec7b0
PS10, Line 12: };
> since this is used to deserialize data, i'd add a __packed attribute just to be sure that the compil […]
Ack
https://review.coreboot.org/c/coreboot/+/61281/comment/6530b324_902d8549
PS10, Line 47: " build's FspmUpd.h\n");
> i'd indent this line
Ack
https://review.coreboot.org/c/coreboot/+/61281/comment/449e764d_37d7b16a
PS10, Line 51: printk(BIOS_ERR, "IMAGE_REVISION_MAJOR_VERSION mismatch, halting\n");
: die("Goodbye now\n");
> put the message from the printk line in the die call?
Ack
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Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Andrey Petrov, Patrick Rudolph, Julian Schroeder, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: soc/amd/common/fsp: check fsp image revision
......................................................................
soc/amd/common/fsp: check fsp image revision
Check if FSP binary and coreboot FSP structures (fspmupd.h) match
sufficiently.
A change in minor number denotes less critical changes or additions
to the FSP API that still allow for the boot process to proceed.
A change of the AMD image revision major number will halt boot.
The Fspmupd.h header now defines IMAGE_REVISION_ macros for AMD
Picasso and Cezanne APUs.
BUG=b:184650244
TEST=build, boot and check fsp image revision info. Example:
FSP major = 1
FSP minor = 0
FSP revision = 5
FSP build = 0
Signed-off-by: Julian Schroeder <julianmarcusschroeder(a)gmail.com>
Change-Id: I0fbf9413b0cf3e6093ee9c61ff692ff78ebefebc
---
M src/soc/amd/common/fsp/fsp_validate.c
M src/vendorcode/amd/fsp/cezanne/FspmUpd.h
M src/vendorcode/amd/fsp/picasso/FspmUpd.h
M src/vendorcode/amd/fsp/sabrina/FspmUpd.h
4 files changed, 55 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/61281/11
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Change subject: drivers/wwan/fm: Add Fibocom 5G WWAN ACPI support
......................................................................
drivers/wwan/fm: Add Fibocom 5G WWAN ACPI support
Support PXSX._RST and PXSX.MRST._RST for warm and cold reset.
PXSX._RST is invoked on driver removal.
Test:
Add chip entry to the corresponding root port and check PXSX Device
is generated in ssdt.
Signed-off-by: Cliff Huang <cliff.huang(a)intel.com>
Change-Id: I1e0b9fd405f6cfb1e216ea27558bb9299a09e566
---
A src/drivers/wwan/fm/Kconfig
A src/drivers/wwan/fm/Makefile.inc
A src/drivers/wwan/fm/acpi_fm350gl.c
A src/drivers/wwan/fm/chip.h
4 files changed, 249 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/61354/7
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