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Change subject: src/lib: Added CBMEM tag id to parse ddr information
......................................................................
Patch Set 18:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59194/comment/079cee46_839211ca
PS16, Line 9: BUG=b:182963902
> Please add Bug id 177917361, to BUG=
Done
File src/commonlib/include/commonlib/cbmem_id.h:
https://review.coreboot.org/c/coreboot/+/59194/comment/5639c557_45b960b6
PS5, Line 82: 0x10
> Well, it's an emergent pattern more than a rule... […]
Done
https://review.coreboot.org/c/coreboot/+/59194/comment/3f208b24_5ae80d74
PS5, Line 152:
> no extra space
Done
File src/commonlib/include/commonlib/coreboot_tables.h:
https://review.coreboot.org/c/coreboot/+/59194/comment/2cdad2cf_bcdd533e
PS5, Line 88: /* The following options are CMOS-related */
> Your entry is not CMOS-related so it should be added above here (as 0x0043). […]
Done
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Change subject: qualcomm/sc7280: Add support for edp and mdp driver
......................................................................
Patch Set 4: Verified+1
(2 comments)
File src/mainboard/google/herobrine/mainboard.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139619):
https://review.coreboot.org/c/coreboot/+/61342/comment/3a44c7b8_44903bfc
PS4, Line 61: if (display_init_required()) {
suspect code indent for conditional statements (8, 24)
File src/soc/qualcomm/sc7280/display/edp_ctrl.c:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-139619):
https://review.coreboot.org/c/coreboot/+/61342/comment/5b762180_ed15aa37
PS4, Line 863: ret = edp_start_link_train_2(ctrl,dpcd);
space required after that ',' (ctx:VxV)
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Hello Shelley Chen, build bot (Jenkins), Taniya Das,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#8).
Change subject: qualcomm/sc7280: Add display external clock support in coreboot
......................................................................
qualcomm/sc7280: Add display external clock support in coreboot
Add support for EDP (Embedded DisplayPort) clocks in coreboot.
This change supports the configuration and enablement of
EDP PIXEL, LINK, LINK_INTF and AUX clocks.
BUG=b:182963902,216687885
TEST=Validated on qualcomm sc7280 development board.
Signed-off-by: Taniya Das <quic_tdas(a)quicinc.com>
Change-Id: Ia6872ede515401e95ea2dadc9766e3e70fb66144
---
M src/soc/qualcomm/sc7280/clock.c
M src/soc/qualcomm/sc7280/include/soc/clock.h
2 files changed, 53 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/59611/8
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Hello Shelley Chen, build bot (Jenkins), mturney mturney, Julius Werner, mturney mturney,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/59194
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Change subject: src/lib: Added CBMEM tag id to parse ddr information
......................................................................
src/lib: Added CBMEM tag id to parse ddr information
BUG=b:182963902,177917361
TEST=Validated on qualcomm sc7280 developement board
Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org>
Change-Id: I594bd9266a6379e3a85de507eaf4c56619b17a6f
---
M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
1 file changed, 4 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/59194/18
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I'd like you to reexamine a change. Please visit
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Change subject: soc/qualcomm/common: Add dram information to CBMEM table
......................................................................
soc/qualcomm/common: Add dram information to CBMEM table
BUG=b:182963902,177917361
TEST=Validated on qualcomm sc7280 developement board
Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org>
Change-Id: I0f1dd05ee224bf8284661c0afaa01d0a9d71daa7
---
M src/soc/qualcomm/common/include/soc/qclib_common.h
M src/soc/qualcomm/common/qclib.c
2 files changed, 35 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/59195/18
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Change subject: libpayload: Parse DDR Information through coreboot tables
......................................................................
libpayload: Parse DDR Information through coreboot tables
BUG=b:182963902,177917361
TEST=Validated on qualcomm sc7280 developement board
Signed-off-by: Ravi Kumar Bokka <rbokka(a)codeaurora.org>
Change-Id: Ieca7e9fc0e1a018fcb2e9315aebee088edac858e
---
M payloads/libpayload/include/libpayload.h
M payloads/libpayload/include/sysinfo.h
M payloads/libpayload/libc/coreboot.c
A src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h
4 files changed, 51 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/59193/18
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Change subject: [WIP]cpu/x86/smm: Support PARALLEL_MP with SMM_ASEG
......................................................................
Patch Set 3:
(1 comment)
File src/cpu/x86/smm/smm_module_loader.c:
https://review.coreboot.org/c/coreboot/+/58700/comment/f4855477_0e9b2a63
PS2, Line 619: */
> Patchset #1, #2 have stuff leaking below 0xa0000.
>
> Installing permanent SMM handler to 0x000a0000
> smm_create_map: cpus allowed in one segment 62
> smm_create_map: min # of segments needed 1
> CPU 0x0
> smbase a0000 entry a8000
> ss_start afe00 code_end a81e0
> CPU 0x1
> smbase 9fe00 entry a7e00
> ss_start afc00 code_end a7fe0
That looks fine. smbase are below 0xa0000 so that the save states grow downwards from 0xb0000.
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Change subject: mb/google/brya: Allow mainboard to lock I2C TPM SCL/SDA GPIO PADs
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
@Tim/Nick/Eric, Can you take a look into this CL
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Mike Banon has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59636 )
Change subject: Revert "util/crossgcc: Update gcc to 11.2"
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> Mike, any news here? This change-set is probably not the best way to discuss this. […]
So far I've provided all the requested logs (see above) and tried a suggestion with the "safe" flags (which didn't help unfortunately). This issue have been reproduced by other people with AMD boards like G505S and also Thinkpad X201 ( https://ticket.coreboot.org/issues/322 ) <--- although in X201 case the board seemed unbootable at all, while in my case it usually gets past this coreboot+SeaBIOS point and gets stuck booting Linux. I'm not sure how to proceed, and any suggestions will be appreciated.
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