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Change subject: soc/intel/tigerlake: Use PMC IPC to disable HECI1
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/tigerlake/smihandler.c:
https://review.coreboot.org/c/coreboot/+/61457/comment/b22db25c_9c5c1d98
PS5, Line 19: if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT))
: heci1_disable();
> Since this is now supposed to use PMC IPC, can we move it outside of SMM ?
Ack
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Change subject: soc/intel/alderlake: Add PMC register base for ADL-N
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61148/comment/755f15aa_65e0571d
PS3, Line 7: adlrvp
> alderlake
Done
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Change subject: soc/intel/alderlake: Add PMC register base for ADL-N
......................................................................
Patch Set 4:
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https://review.coreboot.org/c/coreboot/+/61148/comment/e1f0a13f_cbf1e832
PS3, Line 7: adlrvp
> alderlake
Done
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Change subject: soc/intel/alderlake: Add PMC register base for ADL-N
......................................................................
Patch Set 4: Code-Review+2
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Hello build bot (Jenkins), Maulik V Vaghela, Kangheui Won, Tim Wawrzynczak, Rizwan Qureshi, Reka Norman, Krishna P Bhat D, Patrick Rudolph, Felix Held,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/alderlake: Add PMC register base for ADL-N
......................................................................
soc/intel/alderlake: Add PMC register base for ADL-N
Add PCR_PSF3_TO_SHDW_PMC_REG_BASE for Alderlake-N.This value is updated
from the FSP code.
Signed-off-by: Usha P <usha.p(a)intel.com>
Change-Id: I7c788e149744bfae2c5260c996b16fc1ce2070c1
---
M src/soc/intel/alderlake/bootblock/pch.c
1 file changed, 5 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/61148/4
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Change subject: soc/intel/adlrvp: Add PMC register base for ADL-N
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61148/comment/8781dd78_c01cc804
PS3, Line 7: adlrvp
alderlake
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Change subject: soc/intel/cannonlake: Drop unnecessary guard for HECI1 disable FSP UPD
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/cannonlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/61455/comment/012c2fcf_4e6005b7
PS5, Line 590: params->Heci1Disabled = CONFIG(DISABLE_HECI1_AT_PRE_BOOT);
> I thought the point was letting coreboot do the disable, so this would be `0` ?
Ack
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Change subject: security/vboot/secdata_tpm: Set up space for widevine counter info
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> Is there any additional info on what exactly this space should contain and why it is needed anywhere […]
This space is required as PSP does not have access to persistent storage and this is required to store Widevine Counter related information in this NV space. How many counters are in use and how many are available, etc.
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Change subject: security/vboot/secdata_tpm: Set up space for widevine counter info
......................................................................
Patch Set 3:
(1 comment)
File src/security/vboot/secdata_tpm.c:
https://review.coreboot.org/c/coreboot/+/61521/comment/8fb9800b_20b18b10
PS3, Line 360: rw_space_attributes, NULL, 0);
We will need to set TPMA_NV_AUTHWRITE = 1 to the rw_space_attributes as the tpm_nv_write from PSP fails with an error 0x12F - TPM_RC_AUTH_UNAVAILABLE.
I believe the TPMA_NV_AUTHWRITE needs to be set for the index to be written once the OS has started.
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Change subject: mb/intel/adlrvp: Fix vbt loading error
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Isn't this function being added to ensure we have single binary with different vbt configuration.
@Maulik ?
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