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Change subject: soc/intel/common/cse: Add `cse_send_end_of_post()` a public function
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/common/block/cse/cse_eop.c:
https://review.coreboot.org/c/coreboot/+/61519/comment/4cc40205_c4e1ef3b
PS3, Line 210: /* FIXME: Add check to skip sending EOP cmd multiple time */
Since EOP is only sent in ramstage, you can use a static variable:
static bool eop_sent = false;
if (eop_sent) {
printk(BIOS_ERR, "EOP already sent\n");
return;
}
eop_sent = true;
This logic would go in `set_cse_end_of_post()`, not here.
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Change subject: soc/intel/common/cse: Add function to perform CSE lock configuration
......................................................................
Patch Set 3: Code-Review+1
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Change subject: soc/intel/common/dsp: Add function to enable `PME` for Audio Controller
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
File src/soc/intel/common/block/include/intelblocks/dsp.h:
https://review.coreboot.org/c/coreboot/+/61530/comment/b02331e6_200c03a7
PS1, Line 8: #define PCS 0x54
: #define PME_ENABLE BIT(8)
Does this need to be part of the API? If not, please move into dsp.c
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Change subject: soc/intel/common/block/notify: Implement coreboot notify native driver
......................................................................
Patch Set 18:
(2 comments)
File src/soc/intel/common/block/notify/notify.c:
https://review.coreboot.org/c/coreboot/+/60405/comment/48cabb69_8acf9e67
PS18, Line 8: the
remove `the`
https://review.coreboot.org/c/coreboot/+/60405/comment/cb1ceb61_ed690589
PS18, Line 39: Setting
Set
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Attention is currently required from: Arthur Heymans, Felix Singer, Tim Wawrzynczak, Sridhar Siricilla, Angel Pons, Werner Zeh, Patrick Rudolph, EricR Lai.
Hello Felix Singer, build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60405
to look at the new patch set (#18).
Change subject: soc/intel/common/block/notify: Implement coreboot notify native driver
......................................................................
soc/intel/common/block/notify: Implement coreboot notify native driver
This patch implements the required HECI operations to perform prior
to booting to OS after platform decides to skip FSP notify APIs
i.e. Ready to Boot and End Of Firmware.
BUG=b:211954778
TEST=Able to build brya with these changes and coreboot log with this
code change as below when ADL SoC selects
SOC_INTEL_COMMON_BLOCK_NOTIFY:
BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 62 ms
coreboot skipped calling FSP notify phase: 00000040.
coreboot skipped calling FSP notify phase: 000000f0.
BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 11 ms
Finalizing chipset.
apm_control: Finalizing SMM.
APMC done.
HECI: Sending End-of-Post
CSE: EOP requested action: continue boot
CSE EOP successful, continuing boot
HECI: CSE device 16.1 is disabled
HECI: CSE device 16.4 is disabled
HECI: CSE device 16.5 is disabled
BS: BS_PAYLOAD_BOOT entry times (exec / console): 9 / 27 ms
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7
---
A src/soc/intel/common/block/notify/Kconfig
A src/soc/intel/common/block/notify/Makefile.inc
A src/soc/intel/common/block/notify/notify.c
3 files changed, 56 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/60405/18
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Hello build bot (Jenkins), Wonkyu Kim, Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/tigerlake: Use PMC IPC to disable HECI1
......................................................................
soc/intel/tigerlake: Use PMC IPC to disable HECI1
This patch allows common CSE block to disable HECI1 device using PMC
IPC command `0xA9`.
Select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC config for
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Additionally, remove dead code that deals with HECI1 disabling using
in SMM as HECI1 disabling using PMC IPC is simpler solution.
BUG=none
TEST=None
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: Id5f1e3f622f65cd0f892c0dc541625bfd50d038e
---
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/finalize.c
M src/soc/intel/tigerlake/smihandler.c
3 files changed, 4 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/61457/7
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