coreboot-gerrit February 2022

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Change in coreboot[master]: soc/intel/common/cse: Add `cse_send_end_of_post()` a public function
by Subrata Banik (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Werner Zeh, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61519 ) Change subject: soc/intel/common/cse: Add `cse_send_end_of_post()` a public function ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/common/block/cse/cse_eop.c: https://review.coreboot.org/c/coreboot/+/61519/comment/fb43908f_eb146b7f PS3, Line 210: /* FIXME: Add check to skip sending EOP cmd multiple time */ > Since EOP is only sent in ramstage, you can use a static variable: […] Thanks, I was exploring some CSE command to verify if EOP is received already. But this will work as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/61519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I837c5723eca766d21b191b98e39eb52889498bfc Gerrit-Change-Number: 61519 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 01 Feb 2022 14:23:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/apollolake: Rename PWRMBASE macro and function
by Subrata Banik (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Andrey Petrov, Patrick Rudolph. Hello Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61532 to look at the new patch set (#4). Change subject: soc/intel/apollolake: Rename PWRMBASE macro and function ...................................................................... soc/intel/apollolake: Rename PWRMBASE macro and function This patch ensures PWRMBASE macro name and function to get PWRMBASE address on APL SoC is align with other IA SoC. PMC_BAR0 -> PCH_PWRM_BASE_ADDRESS read_pmc_mmio_bar() -> pmc_mmio_regs() Additionally, make `pmc_mmio_regs` a public function for other IA common code may need to get access to this function. BUG=None TEST=None Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I3a61117f34b60ed6eeb9bda3ad853f0ffe6390f7 --- M src/soc/intel/apollolake/acpi/pmc_ipc.asl M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/apollolake/include/soc/iomap.h M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/apollolake/pmc.c M src/soc/intel/apollolake/pmutil.c 6 files changed, 12 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/61532/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/61532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a61117f34b60ed6eeb9bda3ad853f0ffe6390f7 Gerrit-Change-Number: 61532 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common: Add the Primary to Sideband bridge library
by Felix Held (Code Review) 01 Feb '22

01 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61283 ) Change subject: soc/intel/common: Add the Primary to Sideband bridge library ...................................................................... soc/intel/common: Add the Primary to Sideband bridge library New platforms have additional Primary to Sideband bridge besides the PCH P2SB. This change puts the common functions into the P2SB library. BUG=b:213574324 TEST=Build platforms coreboot images successfully. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I63f58584e8c3bfe42cdd81912e1e5140337c2d55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61283 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim(a)intel.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/common/block/include/intelblocks/p2sb.h A src/soc/intel/common/block/include/intelblocks/p2sblib.h M src/soc/intel/common/block/p2sb/Makefile.inc M src/soc/intel/common/block/p2sb/p2sb.c A src/soc/intel/common/block/p2sb/p2sblib.c 5 files changed, 126 insertions(+), 44 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Wonkyu Kim: Looks good to me, but someone else must approve EricR Lai: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/common/block/include/intelblocks/p2sb.h b/src/soc/intel/common/block/include/intelblocks/p2sb.h index 436861c..b330ccd 100644 --- a/src/soc/intel/common/block/include/intelblocks/p2sb.h +++ b/src/soc/intel/common/block/include/intelblocks/p2sb.h @@ -43,7 +43,6 @@ union p2sb_bdf p2sb_get_ioapic_bdf(void); void p2sb_set_ioapic_bdf(union p2sb_bdf bdf); - /* SOC overrides */ /* * Each SoC should implement EP Mask register to disable SB access diff --git a/src/soc/intel/common/block/include/intelblocks/p2sblib.h b/src/soc/intel/common/block/include/intelblocks/p2sblib.h new file mode 100644 index 0000000..7df528d2 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/p2sblib.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_INTEL_COMMON_BLOCK_P2SBLIB_H +#define SOC_INTEL_COMMON_BLOCK_P2SBLIB_H + +#include <stddef.h> +#include <stdint.h> + +/* P2SB generic configuration register */ +#define P2SBC 0xe0 +#define P2SBC_HIDE_BIT (1 << 0) + +bool p2sb_dev_is_hidden(pci_devfn_t dev); +void p2sb_dev_unhide(pci_devfn_t dev); +void p2sb_dev_hide(pci_devfn_t dev); +uint32_t p2sb_dev_sbi_read(pci_devfn_t dev, uint8_t pid, uint16_t reg); +void p2sb_dev_sbi_write(pci_devfn_t dev, uint8_t pid, uint16_t reg, uint32_t val); + +#endif /* SOC_INTEL_COMMON_BLOCK_P2SBLIB_H */ diff --git a/src/soc/intel/common/block/p2sb/Makefile.inc b/src/soc/intel/common/block/p2sb/Makefile.inc index d557e36..5c6378e 100644 --- a/src/soc/intel/common/block/p2sb/Makefile.inc +++ b/src/soc/intel/common/block/p2sb/Makefile.inc @@ -1,4 +1,8 @@ -bootblock-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c -romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c -ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c -smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB) += p2sb.c +ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB),y) +bootblock-y += p2sb.c +romstage-y += p2sb.c +ramstage-y += p2sb.c +ramstage-y += p2sblib.c +smm-y += p2sb.c +smm-y += p2sblib.c +endif diff --git a/src/soc/intel/common/block/p2sb/p2sb.c b/src/soc/intel/common/block/p2sb/p2sb.c index a9384ae..16da691 100644 --- a/src/soc/intel/common/block/p2sb/p2sb.c +++ b/src/soc/intel/common/block/p2sb/p2sb.c @@ -1,11 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#define __SIMPLE_DEVICE__ + #include <device/pci_ops.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <intelblocks/p2sb.h> +#include <intelblocks/p2sblib.h> #include <soc/iomap.h> #include <soc/p2sb.h> #include <soc/pci_devs.h> @@ -13,20 +16,6 @@ #define PCH_P2SB_EPMASK(mask_number) (PCH_P2SB_EPMASK0 + ((mask_number) * 4)) -#define HIDE_BIT (1 << 0) - -static bool p2sb_is_hidden(void) -{ - const uint16_t pci_vid = pci_read_config16(PCH_DEV_P2SB, PCI_VENDOR_ID); - - if (pci_vid == 0xffff) - return true; - if (pci_vid == PCI_VENDOR_ID_INTEL) - return false; - printk(BIOS_ERR, "P2SB PCI_VENDOR_ID is invalid, unknown if hidden\n"); - return true; -} - void p2sb_enable_bar(void) { /* Enable PCR Base address in PCH */ @@ -56,7 +45,7 @@ union p2sb_bdf p2sb_get_hpet_bdf(void) { - const bool was_hidden = p2sb_is_hidden(); + const bool was_hidden = p2sb_dev_is_hidden(PCH_DEV_P2SB); if (was_hidden) p2sb_unhide(); @@ -75,7 +64,7 @@ union p2sb_bdf p2sb_get_ioapic_bdf(void) { - const bool was_hidden = p2sb_is_hidden(); + const bool was_hidden = p2sb_dev_is_hidden(PCH_DEV_P2SB); if (was_hidden) p2sb_unhide(); @@ -92,35 +81,14 @@ pci_write_config16(PCH_DEV_P2SB, PCH_P2SB_IBDF, bdf.raw); } -static void p2sb_set_hide_bit(int hide) -{ - const uint16_t reg = PCH_P2SB_E0 + 1; - const uint8_t mask = HIDE_BIT; - uint8_t val; - - val = pci_read_config8(PCH_DEV_P2SB, reg); - val &= ~mask; - if (hide) - val |= mask; - pci_write_config8(PCH_DEV_P2SB, reg, val); -} - void p2sb_unhide(void) { - p2sb_set_hide_bit(0); - - if (p2sb_is_hidden()) - die_with_post_code(POST_HW_INIT_FAILURE, - "Unable to unhide PCH_DEV_P2SB device !\n"); + p2sb_dev_unhide(PCH_DEV_P2SB); } void p2sb_hide(void) { - p2sb_set_hide_bit(1); - - if (!p2sb_is_hidden()) - die_with_post_code(POST_HW_INIT_FAILURE, - "Unable to hide PCH_DEV_P2SB device !\n"); + p2sb_dev_hide(PCH_DEV_P2SB); } static void p2sb_configure_endpoints(int epmask_id, uint32_t mask) diff --git a/src/soc/intel/common/block/p2sb/p2sblib.c b/src/soc/intel/common/block/p2sb/p2sblib.c new file mode 100644 index 0000000..d00606d --- /dev/null +++ b/src/soc/intel/common/block/p2sb/p2sblib.c @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define __SIMPLE_DEVICE__ + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <intelblocks/p2sb.h> +#include <intelblocks/p2sblib.h> +#include <intelblocks/pcr.h> +#include <soc/pci_devs.h> + +bool p2sb_dev_is_hidden(pci_devfn_t dev) +{ + const uint16_t pci_vid = pci_read_config16(dev, PCI_VENDOR_ID); + + if (pci_vid == 0xffff) + return true; + if (pci_vid == PCI_VENDOR_ID_INTEL) + return false; + printk(BIOS_ERR, "P2SB PCI_VENDOR_ID is invalid, unknown if hidden\n"); + return true; +} + +static void p2sb_dev_set_hide_bit(pci_devfn_t dev, int hide) +{ + const uint16_t reg = P2SBC + 1; + const uint8_t mask = P2SBC_HIDE_BIT; + uint8_t val; + + val = pci_read_config8(dev, reg); + val &= ~mask; + if (hide) + val |= mask; + pci_write_config8(dev, reg, val); +} + +void p2sb_dev_unhide(pci_devfn_t dev) +{ + p2sb_dev_set_hide_bit(dev, 0); + + if (p2sb_dev_is_hidden(dev)) + die_with_post_code(POST_HW_INIT_FAILURE, + "Unable to unhide the P2SB device!\n"); +} + +void p2sb_dev_hide(pci_devfn_t dev) +{ + p2sb_dev_set_hide_bit(dev, 1); + + if (!p2sb_dev_is_hidden(dev)) + die_with_post_code(POST_HW_INIT_FAILURE, + "Unable to hide the P2SB device!\n"); +} + +static void p2sb_execute_sideband_access(pci_devfn_t dev, uint8_t cmd, uint8_t pid, + uint16_t reg, uint32_t *data) +{ + struct pcr_sbi_msg msg = { + .pid = pid, + .offset = reg, + .opcode = cmd, + .is_posted = false, + .fast_byte_enable = 0xF, + .bar = 0, + .fid = 0 + }; + uint8_t response; + int status; + + /* Unhide the P2SB device */ + p2sb_dev_unhide(dev); + + status = pcr_execute_sideband_msg(dev, &msg, data, &response); + if (status || response) + printk(BIOS_ERR, "Fail to execute p2sb sideband access\n"); + + /* Hide the P2SB device */ + p2sb_dev_hide(dev); +} + +uint32_t p2sb_dev_sbi_read(pci_devfn_t dev, uint8_t pid, uint16_t reg) +{ + uint32_t val = 0; + p2sb_execute_sideband_access(dev, PCR_READ, pid, reg, &val); + return val; +} + +void p2sb_dev_sbi_write(pci_devfn_t dev, uint8_t pid, uint16_t reg, uint32_t val) +{ + p2sb_execute_sideband_access(dev, PCR_WRITE, pid, reg, &val); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/61283 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63f58584e8c3bfe42cdd81912e1e5140337c2d55 Gerrit-Change-Number: 61283 Gerrit-PatchSet: 8 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/apollolake: Rename PWRMBASE macro and function
by Subrata Banik (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Andrey Petrov, Patrick Rudolph. Hello Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61532 to look at the new patch set (#3). Change subject: soc/intel/apollolake: Rename PWRMBASE macro and function ...................................................................... soc/intel/apollolake: Rename PWRMBASE macro and function This patch ensures PWRMBASE macro name and function to get PWRMBASE address on APL SoC is align with other IA SoC. PMC_BAR0 -> PCH_PWRM_BASE_ADDRESS read_pmc_mmio_bar() -> pmc_mmio_regs() Additionally, make `pmc_mmio_regs` a public function for other IA common code may need to get access to this function. BUG=None TEST=None Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I3a61117f34b60ed6eeb9bda3ad853f0ffe6390f7 --- M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/apollolake/include/soc/iomap.h M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/apollolake/pmc.c M src/soc/intel/apollolake/pmutil.c 5 files changed, 11 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/61532/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/61532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a61117f34b60ed6eeb9bda3ad853f0ffe6390f7 Gerrit-Change-Number: 61532 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/apollolake: Rename PWRMBASE macro and function
by Subrata Banik (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Andrey Petrov, Patrick Rudolph. Hello Andrey Petrov, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61532 to look at the new patch set (#2). Change subject: soc/intel/apollolake: Rename PWRMBASE macro and function ...................................................................... soc/intel/apollolake: Rename PWRMBASE macro and function This patch ensures PWRMBASE macro name and function to get PWRMBASE address on APL SoC is align with other IA SoC. PMC_BAR0 -> PCH_PWRM_BASE_ADDRESS read_pmc_mmio_bar() -> pmc_mmio_regs() BUG=None TEST=None Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I3a61117f34b60ed6eeb9bda3ad853f0ffe6390f7 --- M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/apollolake/include/soc/iomap.h M src/soc/intel/apollolake/pmc.c M src/soc/intel/apollolake/pmutil.c 4 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/61532/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a61117f34b60ed6eeb9bda3ad853f0ffe6390f7 Gerrit-Change-Number: 61532 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/amd/common/block/psp: Add platform secure boot support
by ritul guru (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Paul Menzel, Angel Pons, Aamir Bohra, Felix Held. ritul guru has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/60968 ) Change subject: soc/amd/common/block/psp: Add platform secure boot support ...................................................................... Patch Set 11: (2 comments) File src/soc/amd/common/block/psp/Kconfig: https://review.coreboot.org/c/coreboot/+/60968/comment/301ba34b_8870620d PS5, Line 33: default n > not needed though..but fine with it. Ack File src/soc/amd/common/block/psp/Kconfig: https://review.coreboot.org/c/coreboot/+/60968/comment/a20aecf4_803434d4 PS9, Line 34: help > I see some of the APIs like send_psp_command sourced from SOC_AMD_COMMON_BLOCK_PSP_GEN2/1.. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/60968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30aac29a22a5800d5995a78c50fdecd660a3d4eb Gerrit-Change-Number: 60968 Gerrit-PatchSet: 11 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 01 Feb 2022 13:47:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: ritul guru <ritul.bits(a)gmail.com> Comment-In-Reply-To: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/block/psp: Add platform secure boot support
by ritul guru (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Jason Glenesk, Raul Rangel, ritul guru, Marshall Dawson, Paul Menzel, Angel Pons, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Marshall Dawson, Aamir Bohra, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60968 to look at the new patch set (#11). Change subject: soc/amd/common/block/psp: Add platform secure boot support ...................................................................... soc/amd/common/block/psp: Add platform secure boot support Add Platform Secure Boot (PSB) enablement via the PSP if it is not already enabled. Upon receiving psb command, PSP will program PSB fuses as long as BIOS signing key token is valid. Change-Id: I30aac29a22a5800d5995a78c50fdecd660a3d4eb Signed-off-by: Ritul Guru <ritul.bits(a)gmail.com> --- M src/soc/amd/common/block/psp/Kconfig M src/soc/amd/common/block/psp/Makefile.inc A src/soc/amd/common/block/psp/psb.c M src/soc/amd/common/block/psp/psp_def.h M src/soc/amd/common/block/psp/psp_gen2.c 5 files changed, 238 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/60968/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/60968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30aac29a22a5800d5995a78c50fdecd660a3d4eb Gerrit-Change-Number: 60968 Gerrit-PatchSet: 11 Gerrit-Owner: ritul guru <ritul.bits(a)gmail.com> Gerrit-Reviewer: Aamir Bohra <aamirbohra(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/apollolake: Rename PWRMBASE macro and function
by Subrata Banik (Code Review) 01 Feb '22

01 Feb '22

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61532 ) Change subject: soc/intel/apollolake: Rename PWRMBASE macro and function ...................................................................... soc/intel/apollolake: Rename PWRMBASE macro and function This patch ensures PWRMBASE macro name and function to get PWRMBASE address on APL SoC is align with other IA SoC. PMC_BAR0 -> PCH_PWRM_BASE_ADDRESS read_pmc_mmio_bar() -> pmc_mmio_regs() BUG=None TEST=None Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I3a61117f34b60ed6eeb9bda3ad853f0ffe6390f7 --- M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/apollolake/include/soc/iomap.h M src/soc/intel/apollolake/pmc.c M src/soc/intel/apollolake/pmutil.c 4 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/61532/1 diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 14e9b11..fe0cb93 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -62,7 +62,7 @@ pci_devfn_t pmc = PCH_DEV_PMC; /* Set PMC base addresses and enable decoding. */ - pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PMC_BAR0); + pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PCH_PWRM_BASE_ADDRESS); pci_write_config32(pmc, PCI_BASE_ADDRESS_1, 0); /* 64-bit BAR */ pci_write_config32(pmc, PCI_BASE_ADDRESS_2, PMC_BAR1); pci_write_config32(pmc, PCI_BASE_ADDRESS_3, 0); /* 64-bit BAR */ diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index 5e5b40e..e92227b 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -25,7 +25,7 @@ #define ACPI_PMIO_CST_REG (ACPI_BASE_ADDRESS + 0x14) /* Accesses to these BARs are hardcoded in FSP */ -#define PMC_BAR0 0xfe042000 +#define PCH_PWRM_BASE_ADDRESS 0xfe042000 #define PMC_BAR1 0xfe044000 #define PMC_BAR0_SIZE (8 * KiB) diff --git a/src/soc/intel/apollolake/pmc.c b/src/soc/intel/apollolake/pmc.c index 959fb53..4bb6229 100644 --- a/src/soc/intel/apollolake/pmc.c +++ b/src/soc/intel/apollolake/pmc.c @@ -15,7 +15,7 @@ int pmc_soc_get_resources(struct pmc_resource_config *cfg) { cfg->pwrmbase_offset = PCI_BASE_ADDRESS_0; - cfg->pwrmbase_addr = PMC_BAR0; + cfg->pwrmbase_addr = PCH_PWRM_BASE_ADDRESS; cfg->pwrmbase_size = PMC_BAR0_SIZE; cfg->abase_offset = PCI_BASE_ADDRESS_4; cfg->abase_addr = ACPI_BASE_ADDRESS; diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 06c2d63..5383e52 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -24,14 +24,14 @@ #include "chip.h" -static uintptr_t read_pmc_mmio_bar(void) +static uint8_t *pmc_mmio_regs(void) { - return PMC_BAR0; + return (void *)(uintptr_t)PCH_PWRM_BASE_ADDRESS; } uintptr_t soc_read_pmc_base(void) { - return read_pmc_mmio_bar(); + return (uintptr_t)pmc_mmio_regs(); } uint32_t *soc_pmc_etr_addr(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/61532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a61117f34b60ed6eeb9bda3ad853f0ffe6390f7 Gerrit-Change-Number: 61532 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/prodrive/hermes: Add VT-x control via EEPROM
by Marvin Drees (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Patrick Rudolph, Christian Walter, Angel Pons. Marvin Drees has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61507 ) Change subject: mb/prodrive/hermes: Add VT-x control via EEPROM ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/61507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If65c58dd6e5069dba1675ad875c7ac89e704350e Gerrit-Change-Number: 61507 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 01 Feb 2022 13:18:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/cannonlake: Add `disable_vmx` devtree option
by Marvin Drees (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Angel Pons. Marvin Drees has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61506 ) Change subject: soc/intel/cannonlake: Add `disable_vmx` devtree option ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/61506 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia760be61466bc6a0ec187746e6e32537029512b4 Gerrit-Change-Number: 61506 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 01 Feb 2022 13:18:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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