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Change subject: soc/intel/alderlake: Use PMC IPC to disable HECI1
......................................................................
Patch Set 7:
(1 comment)
File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/61458/comment/f0d8c394_8137b357
PS7, Line 81: select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if DISABLE_HECI1_AT_PRE_BOOT
> You guard DISABLE_HECI1_AT_PRE_BOOT in the C code, I think we don't need guard here again?
`if` clause might denote here the dependency. there is no need for SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if we don't even bother to select DISABLE_HECI1_AT_PRE_BOOT.
I also agreed with you that we have ample guard to ensure PMC IPC Kconfig won't do anything unless the base dependency is resolved.
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Change subject: soc/intel/common/dsp: Add function to enable `PME` for Audio Controller
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> +1, I don't understand why ? Seems like it should be a kernel driver setting this. […]
Attribute for this BIT is RW so anyone can set this bit coreboot/payload/kernel.
As per EDS, this bit is cleared on every power-on reset and sw should set this bit appropriately.
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Change subject: soc/intel/common/dsp: Add function to enable `PME` for Audio Controller
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
> just for curious, why we need this in coreboot? I think depthcharge or kernel can do it by itself. […]
+1, I don't understand why ? Seems like it should be a kernel driver setting this. I also see that PME bit is set on my brya0 already without this patch.
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Change subject: soc/intel/common/dsp: Add function to enable `PME` for Audio Controller
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
just for curious, why we need this in coreboot? I think depthcharge or kernel can do it by itself. coreboot doesn't need the dsp, right?
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Change subject: mb/google/brya: Allow mainboard to lock I2C TPM SCL/SDA GPIO PADs
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> Which one is redundant Eric. […]
never mind, I mead my comment. LGTM no needs extra to me :p just typo. This CL is all correct to me.
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Change subject: soc/intel/common/cse: Add function to perform CSE lock configuration
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
oh, will this effect the MP device? Once we the do ME lock, we still need preform global reset in coreboot for aux update/CSE RW jump/H1 update etc...?
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Change subject: soc/intel/alderlake: Use PMC IPC to disable HECI1
......................................................................
Patch Set 7:
(1 comment)
File src/soc/intel/alderlake/Kconfig:
https://review.coreboot.org/c/coreboot/+/61458/comment/114445db_feffde05
PS7, Line 81: select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if DISABLE_HECI1_AT_PRE_BOOT
You guard DISABLE_HECI1_AT_PRE_BOOT in the C code, I think we don't need guard here again?
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Change subject: mb/google/brya: Allow mainboard to lock I2C TPM SCL/SDA GPIO PADs
......................................................................
Patch Set 3:
(1 comment)
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PS3:
> > LGTM to me. […]
Which one is redundant Eric. sorry didn't get you!
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Hello build bot (Jenkins), Jason Glenesk, Marshall Dawson, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/61461
to look at the new patch set (#6).
Change subject: mb/amd/chausie: update GPIO for chausie
......................................................................
mb/amd/chausie: update GPIO for chausie
Add/update initial GPIO pin descriptions and initialization types for
chausie mainboard.
Change-Id: I14ea0e1086f626398a867896ee81ce07cf530182
Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com>
---
M src/mainboard/amd/chausie/Makefile.inc
M src/mainboard/amd/chausie/early_gpio.c
A src/mainboard/amd/chausie/gpio.c
M src/mainboard/amd/chausie/gpio.h
M src/mainboard/amd/chausie/mainboard.c
5 files changed, 206 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/61461/6
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Change subject: mb/google/brya: Allow mainboard to lock I2C TPM SCL/SDA GPIO PADs
......................................................................
Patch Set 3:
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Patchset:
PS3:
> LGTM to me.
woops to me is redundant.
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