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Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61519 )
Change subject: soc/intel/common/cse: Add `cse_send_end_of_post()` a public function
......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/61519/comment/f16a6440_ab754540
PS4, Line 9: eates a global function `cse_send_end_of_post()`
The patch is doing more operation than commit message.
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Hello Felix Singer, build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Lean Sheng Tan, Patrick Rudolph, EricR Lai,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/60406
to look at the new patch set (#14).
Change subject: soc/intel/alderlake: Skip FSP Notify APIs
......................................................................
soc/intel/alderlake: Skip FSP Notify APIs
SoC selects `SOC_INTEL_COMMON_BLOCK_NOTIFY` Kconfig to skip FSP notify
APIs (Ready to boot and End of Firmware) and make use of native coreboot
driver to perform require heci notify prior booting to OS.
BUG=b:211954778
TEST=Able to build brya with these changes and coreboot log with this
code change as below when ADL SoC selects
SOC_INTEL_COMMON_BLOCK_NOTIFY.
BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 62 ms
coreboot skipped calling FSP notify phase: 00000040.
coreboot skipped calling FSP notify phase: 000000f0.
BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 11 ms
Finalizing chipset.
apm_control: Finalizing SMM.
APMC done.
HECI: Sending End-of-Post
CSE: EOP requested action: continue boot
CSE EOP successful, continuing boot
HECI: CSE device 16.1 is disabled
HECI: CSE device 16.4 is disabled
HECI: CSE device 16.5 is disabled
BS: BS_PAYLOAD_BOOT entry times (exec / console): 9 / 27 ms
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I0198c9568de0e74053775682a44324405746389a
---
M src/soc/intel/alderlake/Kconfig
M src/soc/intel/alderlake/finalize.c
2 files changed, 7 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/60406/14
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: soc/intel/common/dsp: Add function to enable `PME` for Audio Controller
......................................................................
soc/intel/common/dsp: Add function to enable `PME` for Audio Controller
This function implements an API that sets PME for audio controller.
BUG=none
TEST=none
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I76125b60cb128fd927b4c1205db6cc8964371b47
---
M src/soc/intel/common/block/dsp/dsp.c
A src/soc/intel/common/block/include/intelblocks/dsp.h
2 files changed, 26 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/61530/2
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I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/common/block/notify: Implement coreboot notify native driver
......................................................................
soc/intel/common/block/notify: Implement coreboot notify native driver
This patch implements the required HECI operations to perform prior
to booting to OS after platform decides to skip FSP notify APIs
i.e. Ready to Boot and End Of Firmware.
BUG=b:211954778
TEST=Able to build brya with these changes and coreboot log with this
code change as below when ADL SoC selects
SOC_INTEL_COMMON_BLOCK_NOTIFY:
BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 62 ms
coreboot skipped calling FSP notify phase: 00000040.
coreboot skipped calling FSP notify phase: 000000f0.
BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 11 ms
Finalizing chipset.
apm_control: Finalizing SMM.
APMC done.
HECI: Sending End-of-Post
CSE: EOP requested action: continue boot
CSE EOP successful, continuing boot
HECI: CSE device 16.1 is disabled
HECI: CSE device 16.4 is disabled
HECI: CSE device 16.5 is disabled
BS: BS_PAYLOAD_BOOT entry times (exec / console): 9 / 27 ms
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7
---
A src/soc/intel/common/block/notify/Kconfig
A src/soc/intel/common/block/notify/Makefile.inc
A src/soc/intel/common/block/notify/notify.c
3 files changed, 56 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/60405/19
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I'd like you to reexamine a change. Please visit
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to look at the new patch set (#4).
Change subject: soc/intel/common/cse: Add `cse_send_end_of_post()` a public function
......................................................................
soc/intel/common/cse: Add `cse_send_end_of_post()` a public function
This patch creates a global function `cse_send_end_of_post()` so
that IA common code may get access to this function for sending EOP
command to the HECI1/CSE device.
BUG=b:211954778
TEST=Able to build and boot Brya.
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I837c5723eca766d21b191b98e39eb52889498bfc
---
M src/soc/intel/common/block/cse/cse_eop.c
M src/soc/intel/common/block/include/intelblocks/cse.h
2 files changed, 16 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/61519/4
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Change subject: soc/intel/common/dsp: Add function to enable `PME` for Audio Controller
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/dsp.h:
https://review.coreboot.org/c/coreboot/+/61530/comment/929db979_474e0ab4
PS1, Line 8: #define PCS 0x54
: #define PME_ENABLE BIT(8)
> Does this need to be part of the API? If not, please move into dsp. […]
Ack
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