coreboot-gerrit February 2022

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Change in coreboot[master]: soc/intel/common/block/notify: Implement coreboot notify native driver
by Subrata Banik (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Arthur Heymans, Felix Singer, Tim Wawrzynczak, Sridhar Siricilla, Angel Pons, Werner Zeh, Patrick Rudolph, EricR Lai. Hello Felix Singer, build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60405 to look at the new patch set (#18). Change subject: soc/intel/common/block/notify: Implement coreboot notify native driver ...................................................................... soc/intel/common/block/notify: Implement coreboot notify native driver This patch implements the required HECI operations to perform prior to booting to OS after platform decides to skip FSP notify APIs i.e. Ready to Boot and End Of Firmware. BUG=b:211954778 TEST=Able to build brya with these changes and coreboot log with this code change as below when ADL SoC selects SOC_INTEL_COMMON_BLOCK_NOTIFY: BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 62 ms coreboot skipped calling FSP notify phase: 00000040. coreboot skipped calling FSP notify phase: 000000f0. BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 11 ms Finalizing chipset. apm_control: Finalizing SMM. APMC done. HECI: Sending End-of-Post CSE: EOP requested action: continue boot CSE EOP successful, continuing boot HECI: CSE device 16.1 is disabled HECI: CSE device 16.4 is disabled HECI: CSE device 16.5 is disabled BS: BS_PAYLOAD_BOOT entry times (exec / console): 9 / 27 ms Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7 --- A src/soc/intel/common/block/notify/Kconfig A src/soc/intel/common/block/notify/Makefile.inc A src/soc/intel/common/block/notify/notify.c 3 files changed, 56 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/60405/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/60405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7 Gerrit-Change-Number: 60405 Gerrit-PatchSet: 18 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tigerlake: Use PMC IPC to disable HECI1
by Subrata Banik (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Wonkyu Kim, Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai, Karthik Ramasubramanian. Hello build bot (Jenkins), Wonkyu Kim, Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61457 to look at the new patch set (#7). Change subject: soc/intel/tigerlake: Use PMC IPC to disable HECI1 ...................................................................... soc/intel/tigerlake: Use PMC IPC to disable HECI1 This patch allows common CSE block to disable HECI1 device using PMC IPC command `0xA9`. Select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC config for Tiger Lake to disable HECI1 device using PMC IPC. Additionally, remove dead code that deals with HECI1 disabling using in SMM as HECI1 disabling using PMC IPC is simpler solution. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Id5f1e3f622f65cd0f892c0dc541625bfd50d038e --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/finalize.c M src/soc/intel/tigerlake/smihandler.c 3 files changed, 4 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/61457/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/61457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5f1e3f622f65cd0f892c0dc541625bfd50d038e Gerrit-Change-Number: 61457 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wonkyu Kim Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/brya: Use PAD config macro to add lock support
by Felix Held (Code Review) 01 Feb '22

01 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/60320 ) Change subject: mb/google/brya: Use PAD config macro to add lock support ...................................................................... mb/google/brya: Use PAD config macro to add lock support Use PAD config macro to add lock support for all the gpios used in CB:58352 CB:58353. BUG=b:211573253 TEST=Boot to OS, issue warm reboot and see no issue with any IP enumeration Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> Change-Id: I558bab39f935ab31a89541c6498a73af70cbf9ee Reviewed-on: https://review.coreboot.org/c/coreboot/+/60320 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/brya/variants/baseboard/brya/gpio.c 1 file changed, 42 insertions(+), 42 deletions(-) Approvals: build bot (Jenkins): Verified Nick Vaccaro: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c index 0583930..88dbe0e 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/gpio.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/gpio.c @@ -35,7 +35,7 @@ /* A15 : USB_OC2# ==> USB_C2_OC_ODL */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* A16 : USB_OC3# ==> USB_A0_OC_ODL */ - PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + PAD_CFG_NF_LOCK(GPP_A16, NONE, NF1, LOCK_CONFIG), /* A17 : DISP_MISCC ==> EN_FCAM_PWR */ PAD_CFG_GPO(GPP_A17, 1, DEEP), /* A18 : DDSP_HPDB ==> HDMI_HPD */ @@ -56,19 +56,19 @@ /* B1 : SOC_VID1 */ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* B2 : VRALERT# ==> M2_SSD_PLA_L */ - PAD_CFG_GPO(GPP_B2, 1, PLTRST), + PAD_CFG_GPO_LOCK(GPP_B2, 1, LOCK_CONFIG), /* B3 : PROC_GP2 ==> SAR2_INT_L */ - PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST, LEVEL, NONE), + PAD_CFG_GPI_APIC_LOCK(GPP_B3, NONE, LEVEL, NONE, LOCK_CONFIG), /* B4 : PROC_GP3 ==> SSD_PERST_L */ - PAD_CFG_GPO(GPP_B4, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG), /* B5 : ISH_I2C0_SDA ==> PCH_I2C_MISC_SDA */ - PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), + PAD_CFG_NF_LOCK(GPP_B5, NONE, NF2, LOCK_CONFIG), /* B6 : ISH_I2C0_SCL ==> PCH_I2C_MISC_SCL */ - PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), + PAD_CFG_NF_LOCK(GPP_B6, NONE, NF2, LOCK_CONFIG), /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ - PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2), + PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG), /* B8 : ISH_I2C1_SCL ==> PCH_I2C_TPM_SCL */ - PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2), + PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG), /* B9 : NC */ PAD_NC(GPP_B9, NONE), /* B10 : NC */ @@ -82,11 +82,11 @@ /* B14 : SPKR ==> GPP_B14_STRAP */ PAD_NC(GPP_B14, NONE), /* B15 : TIME_SYNC0 ==> FP_USER_PRES_FP_L */ - PAD_CFG_GPI(GPP_B15, NONE, PLTRST), + PAD_CFG_GPI_LOCK(GPP_B15, NONE, LOCK_CONFIG), /* B16 : I2C5_SDA ==> PCH_I2C_TCHPAD_SDA */ - PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), + PAD_CFG_NF_LOCK(GPP_B16, NONE, NF2, LOCK_CONFIG), /* B17 : I2C5_SCL ==> PCH_I2C_TCHPAD_SCL */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2), + PAD_CFG_NF_LOCK(GPP_B17, NONE, NF2, LOCK_CONFIG), /* B18 : ADR_COMPLETE ==> GPP_B18_STRAP */ PAD_NC(GPP_B18, NONE), /* B19 : NC */ @@ -120,11 +120,11 @@ /* D0 : ISH_GP0 ==> PCH_FP_BOOT0 */ PAD_NC(GPP_D0, NONE), /* D1 : ISH_GP1 ==> FP_RST_ODL */ - PAD_CFG_GPO(GPP_D1, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_D1, 1, LOCK_CONFIG), /* D2 : ISH_GP2 ==> EN_FP_PWR */ - PAD_CFG_GPO(GPP_D2, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_D2, 1, LOCK_CONFIG), /* D3 : ISH_GP3 ==> WCAM_RST_L */ - PAD_CFG_GPO(GPP_D3, 0, DEEP), + PAD_CFG_GPO_LOCK(GPP_D3, 0, LOCK_CONFIG), /* D4 : IMGCLKOUT0 ==> BT_DISABLE_L */ PAD_CFG_GPO(GPP_D4, 1, DEEP), /* D5 : SRCCLKREQ0# ==> WWAN_DPR_SAR_ODL */ @@ -136,33 +136,33 @@ /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* D9 : ISH_SPI_CS# ==> USB_C2_LSX_TX */ - PAD_CFG_NF(GPP_D9, NONE, DEEP, NF4), + PAD_CFG_NF_LOCK(GPP_D9, NONE, NF4, LOCK_CONFIG), /* D10 : ISH_SPI_CLK ==> USB_C2_LSX_RX_STRAP */ - PAD_CFG_NF(GPP_D10, NONE, DEEP, NF4), + PAD_CFG_NF_LOCK(GPP_D10, NONE, NF4, LOCK_CONFIG), /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */ - PAD_CFG_GPO(GPP_D11, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_D11, 1, LOCK_CONFIG), /* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */ PAD_NC(GPP_D12, NONE), /* D13 : ISH_UART0_RXD ==> CAM_PSW_L */ - PAD_CFG_GPI_INT(GPP_D13, NONE, PLTRST, EDGE_BOTH), + PAD_CFG_GPI_INT_LOCK(GPP_D13, NONE, EDGE_BOTH, LOCK_CONFIG), /* D14 : ISH_UART0_TXD ==> SPKR_INT_L */ - PAD_CFG_GPI(GPP_D14, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_D14, NONE, LOCK_CONFIG), /* D15 : ISH_UART0_RTS# ==> EN_WCAM_SENR_PWR */ - PAD_CFG_GPO(GPP_D15, 0, DEEP), + PAD_CFG_GPO_LOCK(GPP_D15, 0, LOCK_CONFIG), /* D16 : ISH_UART0_CTS# ==> EN_WCAM_PWR */ - PAD_CFG_GPO(GPP_D16, 0, DEEP), + PAD_CFG_GPO_LOCK(GPP_D16, 0, LOCK_CONFIG), /* D17 : UART1_RXD ==> SD_PE_PRSNT_L */ - PAD_CFG_GPI(GPP_D17, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_D17, NONE, LOCK_CONFIG), /* D18 : UART1_TXD ==> SD_PE_RST_L */ - PAD_CFG_GPO(GPP_D18, 1, DEEP), + PAD_CFG_GPO_LOCK(GPP_D18, 1, LOCK_CONFIG), /* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* E0 : see end of E group */ /* E1 : THC0_SPI1_IO2 ==> MEM_STRAP_2 */ - PAD_CFG_GPI(GPP_E1, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_E1, NONE, LOCK_CONFIG), /* E2 : THC0_SPI1_IO3 ==> MEM_STRAP_1 */ - PAD_CFG_GPI(GPP_E2, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_E2, NONE, LOCK_CONFIG), /* E3 : PROC_GP0 ==> HPS_INT_ODL */ PAD_CFG_GPI_IRQ_WAKE(GPP_E3, NONE, PLTRST, LEVEL, NONE), /* E4 : SATA_DEVSLP0 ==> USB4_BB_RT_FORCE_PWR */ @@ -176,15 +176,15 @@ /* E8 : SLP_DRAM# ==> WIFI_DISABLE_L */ PAD_CFG_GPO(GPP_E8, 1, DEEP), /* E9 : USB_OC0# ==> USB_C0_OC_ODL */ - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + PAD_CFG_NF_LOCK(GPP_E9, NONE, NF1, LOCK_CONFIG), /* E10 : THC0_SPI1_CS# ==> WWAN_CONFIG0 */ - PAD_CFG_GPI(GPP_E10, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_E10, NONE, LOCK_CONFIG), /* E11 : THC0_SPI1_CLK ==> MEM_STRAP_0 */ - PAD_CFG_GPI(GPP_E11, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_E11, NONE, LOCK_CONFIG), /* E12 : THC0_SPI1_IO1 ==> MEM_STRAP_3 */ - PAD_CFG_GPI(GPP_E12, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_E12, NONE, LOCK_CONFIG), /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */ - PAD_CFG_GPI(GPP_E13, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG), /* E14 : DDSP_HPDA ==> SOC_EDP_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* E15 : RSVD_TP ==> PCH_WP_OD */ @@ -192,7 +192,7 @@ /* E16 : RSVD_TP ==> WWAN_RST_L */ PAD_CFG_GPO(GPP_E16, 1, DEEP), /* E17 : THC0_SPI1_INT# ==> WWAN_CONFIG3 */ - PAD_CFG_GPI(GPP_E17, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_E17, NONE, LOCK_CONFIG), /* E18 : DDP1_CTRLCLK ==> USB_C0_LSX_SOC_TX */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */ @@ -234,21 +234,21 @@ /* F10 : GPPF10_STRAP */ PAD_NC(GPP_F10, DN_20K), /* F11 : THC1_SPI2_CLK ==> GSPI_PCH_CLK_FPMCU_R */ - PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4), + PAD_CFG_NF_LOCK(GPP_F11, NONE, NF4, LOCK_CONFIG), /* F12 : GSXDOUT ==> GSPI_PCH_DO_FPMCU_DI_R */ - PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4), + PAD_CFG_NF_LOCK(GPP_F12, NONE, NF4, LOCK_CONFIG), /* F13 : GSXDOUT ==> GSPI_PCH_DI_FPMCU_DO */ - PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4), + PAD_CFG_NF_LOCK(GPP_F13, NONE, NF4, LOCK_CONFIG), /* F14 : GSXDIN ==> TCHPAD_INT_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_F14, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F14, NONE, LEVEL, INVERT, LOCK_CONFIG), /* F15 : GSXSRESET# ==> FPMCU_INT_L */ - PAD_CFG_GPI_IRQ_WAKE(GPP_F15, NONE, DEEP, LEVEL, INVERT), + PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F15, NONE, LEVEL, INVERT, LOCK_CONFIG), /* F16 : GSXCLK ==> GSPI_PCH_CS_FPMCU_R_L */ - PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4), + PAD_CFG_NF_LOCK(GPP_F16, NONE, NF4, LOCK_CONFIG), /* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_F17, NONE, DEEP, LEVEL, INVERT), + PAD_CFG_GPI_IRQ_WAKE_LOCK(GPP_F17, NONE, LEVEL, INVERT, LOCK_CONFIG), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ - PAD_CFG_GPI(GPP_F18, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG), /* F19 : SRCCLKREQ6# ==> M2_SSD_PLN_L */ PAD_CFG_GPO(GPP_F19, 1, PLTRST), /* F20 : EXT_PWR_GATE# ==> UCAM_RST_L */ @@ -267,7 +267,7 @@ /* H2 : GPPH2_BOOT_STRAP3 */ PAD_NC(GPP_H2, NONE), /* H3 : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */ - PAD_CFG_GPI(GPP_H3, NONE, DEEP), + PAD_CFG_GPI_LOCK(GPP_H3, NONE, LOCK_CONFIG), /* H4 : I2C0_SDA ==> PCH_I2C_AUD_SDA */ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), /* H5 : I2C0_SCL ==> PCH_I2C_AUD_SCL */ @@ -387,7 +387,7 @@ /* A12 : SATAXPCIE1 ==> EN_PPVAR_WWAN */ PAD_CFG_GPO(GPP_A12, 1, DEEP), /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */ - PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + PAD_CFG_GPI_APIC_LOCK(GPP_A13, NONE, LEVEL, INVERT, LOCK_CONFIG), /* B4 : PROC_GP3 ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_B4, 0, DEEP), /* B7 : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */ @@ -413,7 +413,7 @@ */ PAD_CFG_GPO(GPP_E16, 0, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ - PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E15, NONE, LOCK_CONFIG), /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ 11 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/60320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I558bab39f935ab31a89541c6498a73af70cbf9ee Gerrit-Change-Number: 60320 Gerrit-PatchSet: 13 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/siemens/{mc_apl1,...,mc_apl6}: Disable SATA ALPM support
by Felix Held (Code Review) 01 Feb '22

01 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61402 ) Change subject: mb/siemens/{mc_apl1,...,mc_apl6}: Disable SATA ALPM support ...................................................................... mb/siemens/{mc_apl1,...,mc_apl6}: Disable SATA ALPM support Aggressive Link Power Management are no longer supported on these mainboards and must therefore be disabled. This feature can have a negative impact on the real-time behavior of the systems. TEST: - Boot into system software on mc_apl1 Change-Id: I8b08381743018790a20273ea1f61e5b0a56e6015 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61402 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb 6 files changed, 18 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb index 20d44bb..0d1cc46 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb @@ -72,7 +72,9 @@ device pci 0e.0 on end # - Audio device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH - device pci 12.0 on end # - SATA + device pci 12.0 on # - SATA + register "DisableSataSalpSupport" = "1" + end device pci 13.0 on # - RP 2 - PCIe A 0 - MACPHY register "pcie_rp_clkreq_pin[2]" = "0" register "pcie_rp_hotplug_enable[2]" = "0" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index 1749636..7440256 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -70,7 +70,9 @@ device pci 0e.0 on end # - Audio device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH - device pci 12.0 on end # - SATA + device pci 12.0 on # - SATA + register "DisableSataSalpSupport" = "1" + end device pci 13.0 on # - RP 2 - PCIe A 0 register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" register "pcie_rp_hotplug_enable[2]" = "0" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb index 45cfd85..449230f 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb @@ -67,7 +67,9 @@ device pci 0e.0 on end # - Audio device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH - device pci 12.0 on end # - SATA + device pci 12.0 on # - SATA + register "DisableSataSalpSupport" = "1" + end device pci 13.0 on # - RP 2 - PCIe A 0 register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" register "pcie_rp_hotplug_enable[2]" = "0" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb index 6f37848..58791f3 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -51,7 +51,9 @@ device pci 0e.0 on end # - Audio device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH - device pci 12.0 on end # - SATA + device pci 12.0 on # - SATA + register "DisableSataSalpSupport" = "1" + end device pci 13.0 on # - RP 2 - PCIe A 0 register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" register "pcie_rp_hotplug_enable[2]" = "0" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb index 2500e08..c4c2e3d 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb @@ -70,7 +70,9 @@ device pci 0e.0 on end # - Audio device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH - device pci 12.0 on end # - SATA + device pci 12.0 on # - SATA + register "DisableSataSalpSupport" = "1" + end device pci 13.0 on # - RP 2 - PCIe A 0 register "pcie_rp_clkreq_pin[2]" = "0" register "pcie_rp_hotplug_enable[2]" = "0" diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb index e058fde..f75dc1c 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb @@ -41,7 +41,9 @@ device pci 0e.0 on end # - Audio device pci 0f.0 on end # - CSE device pci 11.0 on end # - ISH - device pci 12.0 on end # - SATA + device pci 12.0 on # - SATA + register "DisableSataSalpSupport" = "1" + end device pci 13.0 on # - RP 2 - PCIe A 0 register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" register "pcie_rp_hotplug_enable[2]" = "0" -- To view, visit https://review.coreboot.org/c/coreboot/+/61402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8b08381743018790a20273ea1f61e5b0a56e6015 Gerrit-Change-Number: 61402 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/appololake: Allow to configure SATA ALPM via devicetree
by Felix Held (Code Review) 01 Feb '22

01 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61401 ) Change subject: soc/intel/appololake: Allow to configure SATA ALPM via devicetree ...................................................................... soc/intel/appololake: Allow to configure SATA ALPM via devicetree Add a devicetree option to disable SATA Aggressive Link Power Management. ALPM is a method of saving power. The corresponding FSP-S UPD parameter is enabled by default. It may be that this feature is unwanted, for example for a real-time system. Therefore, allow to disable ALPM using the devicetree. Change-Id: Ica8920a87ebebe83f5d8cb4d6c8c0a6105e183e4 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61401 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chip.h 2 files changed, 7 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Werner Zeh: Looks good to me, approved diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 98844a5..82ec2da 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -693,6 +693,10 @@ silconfig->PavpEnable = CONFIG(PAVP); + /* SATA config */ + if (is_devfn_enabled(PCH_DEVFN_SATA)) + silconfig->SataSalpSupport = !(cfg->DisableSataSalpSupport); + mainboard_silicon_init_params(silconfig); } diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 482b333..f531381 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -190,6 +190,9 @@ * 0:Enable (default), 1:Disable. */ uint8_t disable_xhci_lfps_pm; + + /* SATA Aggressive Link Power Management */ + uint8_t DisableSataSalpSupport; }; typedef struct soc_intel_apollolake_config config_t; -- To view, visit https://review.coreboot.org/c/coreboot/+/61401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica8920a87ebebe83f5d8cb4d6c8c0a6105e183e4 Gerrit-Change-Number: 61401 Gerrit-PatchSet: 3 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/galtic: Generate SPD ID for Samsung K4U6E3S4AA-MGCR
by Felix Held (Code Review) 01 Feb '22

01 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61105 ) Change subject: mb/google/dedede/var/galtic: Generate SPD ID for Samsung K4U6E3S4AA-MGCR ...................................................................... mb/google/dedede/var/galtic: Generate SPD ID for Samsung K4U6E3S4AA-MGCR Add supported memory parts in the mem_list_variant.txt and generate the SPD ID for the parts. The memory parts being added are: 1. Samsung K4U6E3S4AA-MGCR BUG=b:214460184 TEST=emerge-dedede coreboot Signed-off-by: FrankChu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: Ief75fcb7a8f1c25feaf05b1535a9528a351b23b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61105 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/variants/galtic/memory/Makefile.inc M src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt M src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt 3 files changed, 9 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Frank Chu: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/variants/galtic/memory/Makefile.inc b/src/mainboard/google/dedede/variants/galtic/memory/Makefile.inc index 016e8ea..7b9f433 100644 --- a/src/mainboard/google/dedede/variants/galtic/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/galtic/memory/Makefile.inc @@ -4,6 +4,6 @@ # util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/galtic/memory src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt SPD_SOURCES = -SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:E +SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = H9HCNNNBKMMLXR-NEE, MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR SPD_SOURCES += spd/lp4x/set-1/spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A SPD_SOURCES += spd/lp4x/set-1/spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNCPMMLXR-NEE diff --git a/src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt index 9d92cf1..8d15cd9 100644 --- a/src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt @@ -6,5 +6,6 @@ DRAM Part Name ID to assign H9HCNNNBKMMLXR-NEE 0 (0000) MT53E512M32D2NP-046 WT:E 0 (0000) +K4UBE3D4AA-MGCR 0 (0000) MT53E1G32D2NP-046 WT:A 1 (0001) H9HCNNNCPMMLXR-NEE 2 (0010) diff --git a/src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt index b92e5f1..03c8be0 100644 --- a/src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt @@ -1,4 +1,11 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/lp4x +# See util/spd_tools/lp4x/README.md for more details and instructions. + +# Part Name H9HCNNNBKMMLXR-NEE MT53E512M32D2NP-046 WT:E +K4UBE3D4AA-MGCR MT53E1G32D2NP-046 WT:A H9HCNNNCPMMLXR-NEE -- To view, visit https://review.coreboot.org/c/coreboot/+/61105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief75fcb7a8f1c25feaf05b1535a9528a351b23b0 Gerrit-Change-Number: 61105 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Henry Sun <henrysun(a)google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/google/dedede/var/galtic: Decrease core display clock to 172.8 MHz
by Felix Held (Code Review) 01 Feb '22

01 Feb '22

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61103 ) Change subject: mb/google/dedede/var/galtic: Decrease core display clock to 172.8 MHz ...................................................................... mb/google/dedede/var/galtic: Decrease core display clock to 172.8 MHz Galtic has a rare stability issue. The symptom is display black screen while switching to secure mode, normally it will occurred at the last step of factory side and it'll follow by some specific SOCs. Slowing the initial core display clock frequency down to 172.8 MHz as per Intel recommend for short term solution for Gal series. The CdClock=0xff is set in dedede baseboard, and we overwrite it as 0x0 (172.8 MHz) for Galtic. BUG=b:206557434 BRANCH=dedede TEST=Build firmware and verify on fail DUTs. Check the DUTs can boot up in secure mode well. Signed-off-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Change-Id: Ic059ab306f80a6d01f4b0a380a3b767d3245478d Reviewed-on: https://review.coreboot.org/c/coreboot/+/61103 Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/dedede/variants/galtic/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Karthik Ramasubramanian: Looks good to me, approved Frank Chu: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/dedede/variants/galtic/overridetree.cb b/src/mainboard/google/dedede/variants/galtic/overridetree.cb index 150bfe3..8004736 100644 --- a/src/mainboard/google/dedede/variants/galtic/overridetree.cb +++ b/src/mainboard/google/dedede/variants/galtic/overridetree.cb @@ -67,6 +67,9 @@ register "tcc_offset" = "8" # TCC of 97C + # Core Display Clock Frequency selection + register "cd_clock" = "CD_CLOCK_172_8_MHZ" + device domain 0 on device pci 04.0 on # Default DPTF Policy for all Dedede boards if not overridden -- To view, visit https://review.coreboot.org/c/coreboot/+/61103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic059ab306f80a6d01f4b0a380a3b767d3245478d Gerrit-Change-Number: 61103 Gerrit-PatchSet: 5 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-CC: Hank Lin <hank2_lin(a)pegatron.corp-partner.google.com> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/amd/common/fsp: check fsp image revision
by Felix Held (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Paul Menzel, Name of user not set #1003801, Andrey Petrov, Julian Schroeder, Patrick Rudolph. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61281 ) Change subject: soc/amd/common/fsp: check fsp image revision ...................................................................... Patch Set 11: Code-Review+2 (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/61281/comment/0da2a07e_d22c36ba PS2, Line 11: A change in minor number denotes less critical changes or additions > Please add a blank line between paragraphs. Done https://review.coreboot.org/c/coreboot/+/61281/comment/8514583d_b06c9768 PS2, Line 16: TEST=buld, boot and check fsp image revision info > Please paste the log lines. Done Commit Message: https://review.coreboot.org/c/coreboot/+/61281/comment/e3e8c6a2_8b2e2d73 PS11, Line 16: Picasso and Cezanne APUs. Sabrina APU too -- To view, visit https://review.coreboot.org/c/coreboot/+/61281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fbf9413b0cf3e6093ee9c61ff692ff78ebefebc Gerrit-Change-Number: 61281 Gerrit-PatchSet: 11 Gerrit-Owner: Name of user not set #1003801 Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Name of user not set #1003801 Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Julian Schroeder <julianmarcusschroeder(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 01 Feb 2022 11:39:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cse: Add `cse_send_end_of_post()` a public function
by Subrata Banik (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Werner Zeh, Patrick Rudolph, EricR Lai. Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Werner Zeh, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61519 to look at the new patch set (#2). Change subject: soc/intel/common/cse: Add `cse_send_end_of_post()` a public function ...................................................................... soc/intel/common/cse: Add `cse_send_end_of_post()` a public function This patch creates a global function `cse_send_end_of_post()` so that IA common code may get access to this function for sending EOP command to the HECI1/CSE device. BUG=b:211954778 TEST=Able to build and boot Brya. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I837c5723eca766d21b191b98e39eb52889498bfc --- M src/soc/intel/common/block/cse/cse_eop.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/61519/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I837c5723eca766d21b191b98e39eb52889498bfc Gerrit-Change-Number: 61519 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/alderlake: Use PMC IPC to disable HECI1
by Subrata Banik (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai. Hello build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61458 to look at the new patch set (#5). Change subject: soc/intel/alderlake: Use PMC IPC to disable HECI1 ...................................................................... soc/intel/alderlake: Use PMC IPC to disable HECI1 This patch allows common CSE block to disable HECI1 device using PMC IPC command `0xA9`. Select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC config for Alder Lake to disable HECI1 device using PMC IPC. Additionally, remove dead code that deals with HECI1 disabling using in SMM as HECI1 disabling using PMC IPC is simpler solution. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I11a677173fd6fb38f7c09594a653aeea0df1332c --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/finalize.c M src/soc/intel/alderlake/smihandler.c 3 files changed, 3 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/61458/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/61458 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I11a677173fd6fb38f7c09594a653aeea0df1332c Gerrit-Change-Number: 61458 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit February 2022