coreboot-gerrit February 2022

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/alderlake: Alder Lake choose to skip FSP Notify APIs
by Subrata Banik (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Felix Singer, Tim Wawrzynczak, Angel Pons, Patrick Rudolph, EricR Lai. Hello Felix Singer, build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Lean Sheng Tan, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60406 to look at the new patch set (#12). Change subject: soc/intel/alderlake: Alder Lake choose to skip FSP Notify APIs ...................................................................... soc/intel/alderlake: Alder Lake choose to skip FSP Notify APIs SoC selects `SOC_INTEL_COMMON_BLOCK_NOTIFY` Kconfig to skip FSP notify APIs (Ready to boot and End of Firmware) and make use of native coreboot driver to perform require heci notify prior booting to OS. BUG=b:211954778 TEST=Able to build brya with these changes and coreboot log with this code change as below when ADL SoC selects SOC_INTEL_COMMON_BLOCK_NOTIFY. BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 62 ms coreboot skipped calling FSP notify phase: 00000040. coreboot skipped calling FSP notify phase: 000000f0. BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 11 ms Finalizing chipset. apm_control: Finalizing SMM. APMC done. HECI: Sending End-of-Post CSE: EOP requested action: continue boot CSE EOP successful, continuing boot HECI: CSE device 16.1 is disabled HECI: CSE device 16.4 is disabled HECI: CSE device 16.5 is disabled BS: BS_PAYLOAD_BOOT entry times (exec / console): 9 / 27 ms Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I0198c9568de0e74053775682a44324405746389a --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/finalize.c 2 files changed, 7 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/60406/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/60406 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0198c9568de0e74053775682a44324405746389a Gerrit-Change-Number: 60406 Gerrit-PatchSet: 12 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/block/notify: Implement coreboot notify native driver
by Subrata Banik (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Arthur Heymans, Felix Singer, Tim Wawrzynczak, Sridhar Siricilla, Angel Pons, Werner Zeh, Patrick Rudolph, EricR Lai. Hello Felix Singer, build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/60405 to look at the new patch set (#17). Change subject: soc/intel/common/block/notify: Implement coreboot notify native driver ...................................................................... soc/intel/common/block/notify: Implement coreboot notify native driver This patch implements the required HECI operations to perform prior to booting to OS after platform decides to skip FSP notify APIs i.e. Ready to Boot and End Of Firmware. BUG=b:211954778 TEST=Able to build brya with these changes and coreboot log with this code change as below when ADL SoC selects SOC_INTEL_COMMON_BLOCK_NOTIFY: BS: BS_PAYLOAD_LOAD run times (exec / console): 135 / 62 ms coreboot skipped calling FSP notify phase: 00000040. coreboot skipped calling FSP notify phase: 000000f0. BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 11 ms Finalizing chipset. apm_control: Finalizing SMM. APMC done. HECI: Sending End-of-Post CSE: EOP requested action: continue boot CSE EOP successful, continuing boot HECI: CSE device 16.1 is disabled HECI: CSE device 16.4 is disabled HECI: CSE device 16.5 is disabled BS: BS_PAYLOAD_BOOT entry times (exec / console): 9 / 27 ms Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7 --- A src/soc/intel/common/block/notify/Kconfig A src/soc/intel/common/block/notify/Makefile.inc A src/soc/intel/common/block/notify/notify.c 3 files changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/60405/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/60405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70bde33f77026e8be165ff082defe3cab6686ec7 Gerrit-Change-Number: 60405 Gerrit-PatchSet: 17 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/cse: Add function to perform CSE lock configuration
by Subrata Banik (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Werner Zeh, Patrick Rudolph, EricR Lai. Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Werner Zeh, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61520 to look at the new patch set (#2). Change subject: soc/intel/common/cse: Add function to perform CSE lock configuration ...................................................................... soc/intel/common/cse: Add function to perform CSE lock configuration This patch implements `cse_lock_config()` to perform the required CSE lock configuration as per ME BWG (doc: 627331). BUG=b:211954778 TEST=Able to build and boot Brya. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I3894b2cd8b90dc033f475384486815ab2fadf381 --- M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/61520/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61520 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3894b2cd8b90dc033f475384486815ab2fadf381 Gerrit-Change-Number: 61520 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/tigerlake: Use PMC IPC to disable HECI1
by Subrata Banik (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Wonkyu Kim, Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai, Karthik Ramasubramanian. Hello build bot (Jenkins), Wonkyu Kim, Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61457 to look at the new patch set (#6). Change subject: soc/intel/tigerlake: Use PMC IPC to disable HECI1 ...................................................................... soc/intel/tigerlake: Use PMC IPC to disable HECI1 This patch allows common CSE block to disable HECI1 device using PMC IPC command `0xA9`. Select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC config for Tiger Lake to disable HECI1 device using PMC IPC. Additionally, remove dead code that deals with HECI1 disabling using in SMM as HECI1 disabling using PMC IPC is simpler solution. BUG=none TEST=None Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Id5f1e3f622f65cd0f892c0dc541625bfd50d038e --- M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/finalize.c M src/soc/intel/tigerlake/smihandler.c 3 files changed, 3 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/61457/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/61457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id5f1e3f622f65cd0f892c0dc541625bfd50d038e Gerrit-Change-Number: 61457 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Wonkyu Kim Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wonkyu Kim Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/{adl, common}: Add routines into CSE IA-common code
by Subrata Banik (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Jonathan Zhang, Angel Pons, Arthur Heymans, Andrey Petrov, Patrick Rudolph, Anjaneya "Reddy" Chagam, Johnny Lin, Christian Walter, Tim Wawrzynczak, Nick Vaccaro, Werner Zeh, EricR Lai, Tim Chu. Hello build bot (Jenkins), Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Werner Zeh, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61518 to look at the new patch set (#2). Change subject: soc/intel/{adl, common}: Add routines into CSE IA-common code ...................................................................... soc/intel/{adl, common}: Add routines into CSE IA-common code This patch adds routines to keep CSE and other HECI devices into the lower power device state (AKA D0I3). - cse_set_to_d0i3 => Set CSE device state to D0I3 - heci_set_to_d0i3 => Function sets D0I3 for all HECI devices Additionally, creates a config `MAX_HECI_DEVICES` to pass the HECI device count info from SoC layer to common CSE block. As per PCH EDS, the HECI device count for various SoCs are: ADL/CNL/EHL/ICL/JSL/TGL => 6 (CSE, IDE-R, KT, CSE2, CSE3 and CSE4) APL => 1 (CSE) SKL/Xeon_SP => 5 (CSE, IDE-R, KT, CSE2 and CSE3) BUG=b:211954778 TEST=Able to build and boot Brya. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ie32887196628fe6386896604e50338f4bc0bedfe --- M src/soc/intel/alderlake/finalize.c M src/soc/intel/apollolake/Kconfig M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/cse.c M src/soc/intel/common/block/include/intelblocks/cse.h M src/soc/intel/skylake/Kconfig M src/soc/intel/xeon_sp/Kconfig 7 files changed, 43 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/61518/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie32887196628fe6386896604e50338f4bc0bedfe Gerrit-Change-Number: 61518 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Anjaneya "Reddy" Chagam <anjaneya.chagam(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/cannonlake: Forbid FSP from disabling HECI1
by Subrata Banik (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai. Hello build bot (Jenkins), Maulik V Vaghela, Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Patrick Rudolph, EricR Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61455 to look at the new patch set (#6). Change subject: soc/intel/cannonlake: Forbid FSP from disabling HECI1 ...................................................................... soc/intel/cannonlake: Forbid FSP from disabling HECI1 This patch drops the unnecessary guard that allow FSP to disable HECI1 device using `Heci1Disabled` UPD. BUG=none TEST=Boot to OS, verify HECI1 is disabled on hatch system using coreboot when mainboard selects DISABLE_HECI1_AT_PRE_BOOT config. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ia8908c080ca9991e7a71e795ccb8fc76d99514f8 --- M src/soc/intel/cannonlake/fsp_params.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/61455/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/61455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8908c080ca9991e7a71e795ccb8fc76d99514f8 Gerrit-Change-Number: 61455 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/common/cse: Add `send_end_of_post_to_cse()` a public function
by Subrata Banik (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Werner Zeh, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61519 ) Change subject: soc/intel/common/cse: Add `send_end_of_post_to_cse()` a public function ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/common/block/include/intelblocks/cse.h: https://review.coreboot.org/c/coreboot/+/61519/comment/2e5ebb3b_0b402a46 PS1, Line 496: send_end_of_post_to_cse > suggestion: […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/61519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I837c5723eca766d21b191b98e39eb52889498bfc Gerrit-Change-Number: 61519 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 01 Feb 2022 10:53:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/{adl, common}: Add routines into CSE IA-common code
by Subrata Banik (Code Review) 01 Feb '22

01 Feb '22

Attention is currently required from: Tim Wawrzynczak, Angel Pons, Nick Vaccaro, Werner Zeh, Patrick Rudolph, EricR Lai. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61518 ) Change subject: soc/intel/{adl, common}: Add routines into CSE IA-common code ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/alderlake/finalize.c: https://review.coreboot.org/c/coreboot/+/61518/comment/cf1e3b88_44219363 PS1, Line 83: /* Function to set D0I3 for all HECI devices */ : void soc_set_d0i3_for_heci(void) : { : unsigned int cse_dev[] = { : PCH_DEVFN_CSE, : PCH_DEVFN_CSE_2, : PCH_DEVFN_CSE_3, : PCH_DEVFN_CSE_4 : }; : : for (int i = 0; i < ARRAY_SIZE(cse_dev); i++) { : if (!is_cse_devfn_visible(cse_dev[i])) : continue; : : set_cse_device_state(cse_dev[i], DEV_IDLE); : } : } : > > > Could this function just be moved to common code? […] Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/61518 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie32887196628fe6386896604e50338f4bc0bedfe Gerrit-Change-Number: 61518 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: EricR Lai <ericr_lai(a)compal.corp-partner.google.com> Gerrit-Comment-Date: Tue, 01 Feb 2022 10:49:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/alderlake: Add PMC register base for ADL-N
by Subrata Banik (Code Review) 01 Feb '22

01 Feb '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61148 ) Change subject: soc/intel/alderlake: Add PMC register base for ADL-N ...................................................................... soc/intel/alderlake: Add PMC register base for ADL-N Add PCR_PSF3_TO_SHDW_PMC_REG_BASE for Alderlake-N.This value is updated from the FSP code. Signed-off-by: Usha P <usha.p(a)intel.com> Change-Id: I7c788e149744bfae2c5260c996b16fc1ce2070c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61148 Reviewed-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/alderlake/bootblock/pch.c 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Rizwan Qureshi: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved Kangheui Won: Looks good to me, but someone else must approve diff --git a/src/soc/intel/alderlake/bootblock/pch.c b/src/soc/intel/alderlake/bootblock/pch.c index 6905834..60f3a85 100644 --- a/src/soc/intel/alderlake/bootblock/pch.c +++ b/src/soc/intel/alderlake/bootblock/pch.c @@ -25,7 +25,12 @@ #include <soc/pcr_ids.h> #include <soc/pm.h> +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) +#define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x1080 +#else #define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x1100 +#endif + #define PCR_PSFX_TO_SHDW_BAR0 0 #define PCR_PSFX_TO_SHDW_BAR1 0x4 #define PCR_PSFX_TO_SHDW_BAR2 0x8 -- To view, visit https://review.coreboot.org/c/coreboot/+/61148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c788e149744bfae2c5260c996b16fc1ce2070c1 Gerrit-Change-Number: 61148 Gerrit-PatchSet: 5 Gerrit-Owner: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/alderlake: Select SOC_INTEL_COMMON_BLOCK_SCS for Alder Lake N
by Subrata Banik (Code Review) 01 Feb '22

01 Feb '22

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/61128 ) Change subject: soc/intel/alderlake: Select SOC_INTEL_COMMON_BLOCK_SCS for Alder Lake N ...................................................................... soc/intel/alderlake: Select SOC_INTEL_COMMON_BLOCK_SCS for Alder Lake N Alder Lake N has eMMC storage device. Select SOC_INTEL_COMMON_BLOCK_SCS Kconfig for Alder Lake N. Change-Id: I577ffdc80ef09471309c827551a347d4397a33d1 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61128 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/common/block/scs/Makefile.inc 2 files changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Tim Wawrzynczak: Looks good to me, approved Kangheui Won: Looks good to me, approved diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index dc7d32b..fa95088 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -76,6 +76,7 @@ select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GPIO_LOCK_USING_SBI select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 + select SOC_INTEL_COMMON_BLOCK_SCS if SOC_INTEL_ALDERLAKE_PCH_N select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_IPU select SOC_INTEL_COMMON_BLOCK_IRQ diff --git a/src/soc/intel/common/block/scs/Makefile.inc b/src/soc/intel/common/block/scs/Makefile.inc index 707a334..0b77f5f 100644 --- a/src/soc/intel/common/block/scs/Makefile.inc +++ b/src/soc/intel/common/block/scs/Makefile.inc @@ -1,3 +1,5 @@ +ifneq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_N),y) ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SCS) += sd.c +endif ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SCS) += mmc.c romstage-$(CONFIG_SOC_INTEL_COMMON_EARLY_MMC_WAKE) += early_mmc.c 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. -- To view, visit https://review.coreboot.org/c/coreboot/+/61128 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I577ffdc80ef09471309c827551a347d4397a33d1 Gerrit-Change-Number: 61128 Gerrit-PatchSet: 9 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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coreboot-gerrit February 2022